Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	70908	1			T19	2146		T21	335		T15	1
class_i[0x1]	70103	1			T1	2525		T41	13		T76	1034
class_i[0x2]	53845	1			T1	1499		T15	10		T22	47
class_i[0x3]	55893	1			T1	1		T21	624		T15	4727

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	61579	1			T1	1435		T19	512		T21	252
alert[0x1]	64426	1			T1	588		T19	542		T21	239
alert[0x2]	63196	1			T1	1060		T19	527		T21	229
alert[0x3]	61548	1			T1	942		T19	565		T21	239

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

250476

1

T1

4025

T19

2146

T21

959

esc_ping_fail

273

1

T8

8

T9

8

T10

7

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	61506	1			T1	1435		T19	512		T21	252
esc_integrity_fail	alert[0x1]	64348	1			T1	588		T19	542		T21	239
esc_integrity_fail	alert[0x2]	63129	1			T1	1060		T19	527		T21	229
esc_integrity_fail	alert[0x3]	61493	1			T1	942		T19	565		T21	239
esc_ping_fail	alert[0x0]	73	1			T8	3		T9	2		T10	2
esc_ping_fail	alert[0x1]	78	1			T8	2		T9	2		T10	3
esc_ping_fail	alert[0x2]	67	1			T8	2		T9	2		T10	1
esc_ping_fail	alert[0x3]	55	1			T8	1		T9	2		T10	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	70823	1			T19	2146		T21	335		T15	1
esc_integrity_fail	class_i[0x1]	70047	1			T1	2525		T41	13		T76	1034
esc_integrity_fail	class_i[0x2]	53763	1			T1	1499		T15	10		T22	47
esc_integrity_fail	class_i[0x3]	55843	1			T1	1		T21	624		T15	4727
esc_ping_fail	class_i[0x0]	85	1			T9	8		T291	6		T303	4
esc_ping_fail	class_i[0x1]	56	1			T293	1		T304	1		T309	3
esc_ping_fail	class_i[0x2]	82	1			T8	8		T10	7		T296	5
esc_ping_fail	class_i[0x3]	50	1			T294	4		T302	5		T295	1