Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	687220843	0	0	626
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	687220843	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	687220843	687035610	0	0
tb.dut.CheckAccuCntDw	0	0	626	626	0	0
tb.dut.CheckEscCntDw	0	0	626	626	0	0
tb.dut.CheckNAlerts	0	0	626	626	0	0
tb.dut.CheckNClasses	0	0	626	626	0	0
tb.dut.CheckNEscSev	0	0	626	626	0	0
tb.dut.CrashdumpKnownO_A	0	0	687220843	687035610	0	0
tb.dut.EdnKnownO_A	0	0	687220843	687035610	0	0
tb.dut.EscPKnownO_A	0	0	687220843	687035610	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	687220843	90	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	687220843	90	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	687220843	90	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	687220843	90	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	687220843	90	0	0
tb.dut.IrqAKnownO_A	0	0	687220843	687035610	0	0
tb.dut.IrqBKnownO_A	0	0	687220843	687035610	0	0
tb.dut.IrqCKnownO_A	0	0	687220843	687035610	0	0
tb.dut.IrqDKnownO_A	0	0	687220843	687035610	0	0
tb.dut.TlAReadyKnownO_A	0	0	687220843	687035610	0	0
tb.dut.TlDValidKnownO_A	0	0	687220843	687035610	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	713841772	2669455	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	713841772	13202	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	713841772	13056	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	713841772	13116	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	713841772	13004	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	713841772	13252	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	713841772	13256	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	713841772	13247	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	713841772	13115	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	713841772	13405	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	713841772	13074	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	713841772	12745	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	713841772	13392	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	713841772	13069	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	713841772	12988	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	713841772	13310	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	713841772	13030	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	713841772	13087	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	713841772	13441	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	713841772	13392	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	713841772	13150	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	713841772	13501	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	713841772	13241	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	713841772	13386	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	713841772	12604	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	713841772	13215	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	713841772	12869	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	713841772	13027	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	713841772	13276	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	713841772	12972	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	713841772	13162	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	713841772	12931	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	713841772	12959	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	713841772	12867	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	713841772	13223	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	713841772	13239	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	713841772	13196	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	713841772	13144	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	713841772	13247	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	713841772	13383	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	713841772	13066	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	713841772	13349	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	713841772	13049	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	713841772	13048	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	713841772	13361	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	713841772	13061	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	713841772	13401	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	713841772	13245	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	713841772	12751	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	713841772	12826	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	713841772	13482	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	713841772	13377	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	713841772	13216	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	713841772	13153	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	713841772	13068	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	713841772	12799	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	713841772	13247	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	713841772	13154	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	713841772	13019	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	713841772	12973	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	713841772	13345	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	713841772	13239	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	713841772	13276	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	713841772	12969	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	713841772	13454	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	713841772	13042	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	713841772	12798	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	713841772	12831	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	713841772	13100	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	713841772	13091	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	713841772	23715	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	713841772	13878	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	713841772	12870	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	713841772	13016	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	713841772	13749	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	713841772	13012	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	713841772	12836	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	713841772	13311	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	713841772	13367	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	687220843	90	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	687220843	90	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	687220843	90	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	687220843	2724	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	687220843	256786	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	687220843	329383753	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	687220843	347	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	687220843	843	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	687220843	44	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	687220843	400	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	687040496	251022542	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	687220843	925	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	687220843	901	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	687220843	881	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	687220843	858	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	687220843	629	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	687220843	86424	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	687220843	517	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	687220843	68	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	687220843	1692	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	687220843	1422	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	687220843	687035610	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	687220843	90	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	687220843	90	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	687220843	90	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	687220843	6467	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	687220843	152247	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	687220843	418349132	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	687220843	270	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	687220843	522	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	687220843	25	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	687220843	241	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	687040496	320133668	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	687220843	608	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	687220843	598	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	687220843	590	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	687220843	577	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	687220843	600	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	687220843	85014	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	687220843	502	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	687220843	70	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	687220843	1636	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	687220843	1366	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	687220843	687035610	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	687220843	90	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	687220843	90	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	687220843	90	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	687220843	1483	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	687220843	250865	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	687220843	361245045	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	687220843	284	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	687220843	497	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	687220843	23	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	687220843	223	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	687040496	294926420	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	687220843	578	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	687220843	563	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	687220843	553	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	687220843	546	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	687220843	674	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	687220843	98768	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	687220843	577	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	687220843	71	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	687220843	1628	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	687220843	1358	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	687220843	687035610	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	687220843	90	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	687220843	90	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	687220843	90	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	687220843	3324	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	687220843	178473	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	687220843	382134699	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	687220843	328	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	687220843	511	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	687220843	21	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	687220843	224	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	687040496	313559609	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	687220843	575	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	687220843	566	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	687220843	561	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	687220843	554	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	687220843	746	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	687220843	116437	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	687220843	672	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	687220843	51	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	687220843	1597	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	687220843	1327	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	687220843	687035610	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	713841772	124887695	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	713841772	713106686	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	713841772	713106686	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	713841772	192521659	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	713841772	713106686	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	713841772	713106686	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	831	831	0	0
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