Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	2	38	95.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	2	38	95.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	68	1			T1	2		T19	1		T41	2
class_index[0x1]	70	1			T74	1		T75	4		T23	1
class_index[0x2]	71	1			T21	2		T26	3		T23	2
class_index[0x3]	51	1			T77	1		T76	1		T26	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	80	1			T1	1		T77	1		T78	1
intr_timeout_cnt[1]	59	1			T21	1		T26	1		T46	2
intr_timeout_cnt[2]	28	1			T23	1		T113	1		T52	1
intr_timeout_cnt[3]	14	1			T1	1		T21	1		T41	2
intr_timeout_cnt[4]	23	1			T19	1		T52	1		T55	1
intr_timeout_cnt[5]	13	1			T74	1		T80	1		T83	1
intr_timeout_cnt[6]	7	1			T23	1		T238	1		T242	1
intr_timeout_cnt[7]	15	1			T76	1		T46	1		T229	1
intr_timeout_cnt[8]	8	1			T32	1		T243	1		T229	1
intr_timeout_cnt[9]	13	1			T32	1		T80	1		T95	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	2	38	95.00	2

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x2] , class_index[0x3]]	[intr_timeout_cnt[6]]	--	--	2

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	23	1			T1	1		T78	1		T47	2
class_index[0x0]	intr_timeout_cnt[1]	13	1			T26	1		T46	1		T244	2
class_index[0x0]	intr_timeout_cnt[2]	8	1			T81	1		T245	1		T246	1
class_index[0x0]	intr_timeout_cnt[3]	6	1			T1	1		T41	2		T84	1
class_index[0x0]	intr_timeout_cnt[4]	4	1			T19	1		T244	1		T247	1
class_index[0x0]	intr_timeout_cnt[5]	3	1			T244	1		T248	1		T249	1
class_index[0x0]	intr_timeout_cnt[6]	2	1			T242	1		T250	1		-	-
class_index[0x0]	intr_timeout_cnt[7]	5	1			T76	1		T46	1		T25	1
class_index[0x0]	intr_timeout_cnt[8]	2	1			T243	1		T251	1		-	-
class_index[0x0]	intr_timeout_cnt[9]	2	1			T58	1		T252	1		-	-
class_index[0x1]	intr_timeout_cnt[0]	22	1			T75	4		T46	1		T82	1
class_index[0x1]	intr_timeout_cnt[1]	21	1			T54	2		T58	1		T175	1
class_index[0x1]	intr_timeout_cnt[2]	4	1			T61	2		T232	1		T253	1
class_index[0x1]	intr_timeout_cnt[3]	5	1			T58	1		T254	1		T255	1
class_index[0x1]	intr_timeout_cnt[4]	2	1			T251	1		T242	1		-	-
class_index[0x1]	intr_timeout_cnt[5]	3	1			T74	1		T83	1		T256	1
class_index[0x1]	intr_timeout_cnt[6]	5	1			T23	1		T238	1		T257	1
class_index[0x1]	intr_timeout_cnt[7]	5	1			T229	1		T242	1		T258	1
class_index[0x1]	intr_timeout_cnt[8]	1	1			T252	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[9]	2	1			T80	1		T250	1		-	-
class_index[0x2]	intr_timeout_cnt[0]	21	1			T26	3		T23	1		T45	3
class_index[0x2]	intr_timeout_cnt[1]	14	1			T21	1		T46	1		T259	1
class_index[0x2]	intr_timeout_cnt[2]	5	1			T23	1		T52	1		T58	1
class_index[0x2]	intr_timeout_cnt[3]	1	1			T21	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[4]	13	1			T52	1		T55	1		T57	1
class_index[0x2]	intr_timeout_cnt[5]	3	1			T80	1		T260	2		-	-
class_index[0x2]	intr_timeout_cnt[7]	4	1			T256	1		T261	2		T232	1
class_index[0x2]	intr_timeout_cnt[8]	3	1			T32	1		T229	1		T251	1
class_index[0x2]	intr_timeout_cnt[9]	7	1			T95	1		T258	1		T250	4
class_index[0x3]	intr_timeout_cnt[0]	14	1			T77	1		T76	1		T26	1
class_index[0x3]	intr_timeout_cnt[1]	11	1			T80	1		T175	1		T262	1
class_index[0x3]	intr_timeout_cnt[2]	11	1			T113	1		T92	1		T229	1
class_index[0x3]	intr_timeout_cnt[3]	2	1			T242	1		T232	1		-	-
class_index[0x3]	intr_timeout_cnt[4]	4	1			T83	1		T254	1		T258	1
class_index[0x3]	intr_timeout_cnt[5]	4	1			T263	1		T256	3		-	-
class_index[0x3]	intr_timeout_cnt[7]	1	1			T264	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[8]	2	1			T256	1		T265	1		-	-
class_index[0x3]	intr_timeout_cnt[9]	2	1			T32	1		T251	1		-	-