Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	340335	1			T1	1658		T5	177		T4	1177
all_values[1]	340335	1			T1	1658		T5	177		T4	1177
all_values[2]	340335	1			T1	1658		T5	177		T4	1177
all_values[3]	340335	1			T1	1658		T5	177		T4	1177

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

677216

1

T1

3285

T5

358

T4

2272

auto[1]

684124

1

T1

3347

T5

350

T4

2436

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

805043

1

T1

3516

T5

360

T4

3411

auto[1]

556297

1

T1

3116

T5

348

T4

1297

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	96584	1			T1	444		T5	42		T4	435
all_values[0]	auto[0]	auto[1]	72492	1			T1	404		T5	42		T4	139
all_values[0]	auto[1]	auto[0]	98303	1			T1	417		T5	47		T4	466
all_values[0]	auto[1]	auto[1]	72956	1			T1	393		T5	46		T4	137
all_values[1]	auto[0]	auto[0]	101690	1			T1	447		T5	42		T4	364
all_values[1]	auto[0]	auto[1]	68126	1			T1	400		T5	42		T4	218
all_values[1]	auto[1]	auto[0]	102580	1			T1	436		T5	47		T4	375
all_values[1]	auto[1]	auto[1]	67939	1			T1	375		T5	46		T4	220
all_values[2]	auto[0]	auto[0]	100274	1			T1	421		T5	51		T4	418
all_values[2]	auto[0]	auto[1]	69514	1			T1	365		T5	48		T4	131
all_values[2]	auto[1]	auto[0]	101136	1			T1	464		T5	39		T4	464
all_values[2]	auto[1]	auto[1]	69411	1			T1	408		T5	39		T4	164
all_values[3]	auto[0]	auto[0]	101136	1			T1	432		T5	47		T4	423
all_values[3]	auto[0]	auto[1]	67400	1			T1	372		T5	44		T4	144
all_values[3]	auto[1]	auto[0]	103340	1			T1	455		T5	45		T4	466
all_values[3]	auto[1]	auto[1]	68459	1			T1	399		T5	41		T4	144