Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	340335	1			T1	1658		T5	177		T4	1177
all_pins[1]	340335	1			T1	1658		T5	177		T4	1177
all_pins[2]	340335	1			T1	1658		T5	177		T4	1177
all_pins[3]	340335	1			T1	1658		T5	177		T4	1177

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1082575	1			T1	5057		T5	536		T4	4043
values[0x1]	278765	1			T1	1575		T5	172		T4	665
transitions[0x0=>0x1]	185384	1			T1	991		T5	102		T4	516
transitions[0x1=>0x0]	185627	1			T1	992		T5	102		T4	516

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	267379	1			T1	1265		T5	131		T4	1040
all_pins[0]	values[0x1]	72956	1			T1	393		T5	46		T4	137
all_pins[0]	transitions[0x0=>0x1]	72316	1			T1	389		T5	46		T4	137
all_pins[0]	transitions[0x1=>0x0]	68062	1			T1	396		T5	41		T4	144
all_pins[1]	values[0x0]	272396	1			T1	1283		T5	131		T4	957
all_pins[1]	values[0x1]	67939	1			T1	375		T5	46		T4	220
all_pins[1]	transitions[0x0=>0x1]	36841	1			T1	194		T5	20		T4	161
all_pins[1]	transitions[0x1=>0x0]	41858	1			T1	212		T5	20		T4	78
all_pins[2]	values[0x0]	270924	1			T1	1250		T5	138		T4	1013
all_pins[2]	values[0x1]	69411	1			T1	408		T5	39		T4	164
all_pins[2]	transitions[0x0=>0x1]	38746	1			T1	226		T5	16		T4	113
all_pins[2]	transitions[0x1=>0x0]	37274	1			T1	193		T5	23		T4	169
all_pins[3]	values[0x0]	271876	1			T1	1259		T5	136		T4	1033
all_pins[3]	values[0x1]	68459	1			T1	399		T5	41		T4	144
all_pins[3]	transitions[0x0=>0x1]	37481	1			T1	182		T5	20		T4	105
all_pins[3]	transitions[0x1=>0x0]	38433	1			T1	191		T5	18		T4	125