Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	90474	1			T1	444		T6	1141		T15	538
accum_cnt_1000	220613	1			T1	2113		T5	58		T4	1228
accum_cnt_100	25411	1			T1	288		T5	56		T4	248
accum_cnt_50	71008	1			T1	522		T5	204		T4	191
accum_cnt_10	158104	1			T1	437		T5	28		T4	1788
accum_cnt_0	389166	1			T1	537		T5	6		T4	25

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	250584	1			T1	1157		T5	88		T4	870
class_index[0x1]	250584	1			T1	1157		T5	88		T4	870
class_index[0x2]	250584	1			T1	1157		T5	88		T4	870
class_index[0x3]	250584	1			T1	1157		T5	88		T4	870

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	27101	1			T1	38		T29	442		T17	61
class_index[0x0]	accum_cnt_1000	60316	1			T1	598		T4	519		T21	151
class_index[0x0]	accum_cnt_100	7670	1			T1	53		T4	179		T21	88
class_index[0x0]	accum_cnt_50	21504	1			T1	236		T5	83		T4	127
class_index[0x0]	accum_cnt_10	40423	1			T1	200		T5	5		T4	30
class_index[0x0]	accum_cnt_0	78259	1			T1	32		T4	15		T19	785
class_index[0x1]	accum_cnt_2000	20178	1			T1	210		T6	641		T15	538
class_index[0x1]	accum_cnt_1000	50482	1			T1	268		T4	709		T19	55
class_index[0x1]	accum_cnt_100	6124	1			T1	70		T4	69		T19	17
class_index[0x1]	accum_cnt_50	19810	1			T1	86		T5	73		T4	64
class_index[0x1]	accum_cnt_10	39117	1			T1	153		T5	10		T4	26
class_index[0x1]	accum_cnt_0	107296	1			T1	83		T5	5		T4	2
class_index[0x2]	accum_cnt_2000	22230	1			T1	164		T6	500		T16	78
class_index[0x2]	accum_cnt_1000	55388	1			T1	573		T5	40		T19	23
class_index[0x2]	accum_cnt_100	5335	1			T1	74		T5	20		T19	32
class_index[0x2]	accum_cnt_50	14579	1			T1	127		T5	21		T19	50
class_index[0x2]	accum_cnt_10	34062	1			T1	36		T5	6		T4	868
class_index[0x2]	accum_cnt_0	102008	1			T1	183		T5	1		T4	2
class_index[0x3]	accum_cnt_2000	20965	1			T1	32		T16	31		T103	228
class_index[0x3]	accum_cnt_1000	54427	1			T1	674		T5	18		T19	48
class_index[0x3]	accum_cnt_100	6282	1			T1	91		T5	36		T19	20
class_index[0x3]	accum_cnt_50	15115	1			T1	73		T5	27		T19	61
class_index[0x3]	accum_cnt_10	44502	1			T1	48		T5	7		T4	864
class_index[0x3]	accum_cnt_0	101603	1			T1	239		T4	6		T19	776