Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	3278	1			T15	15		T77	173		T16	43
alert[0x1]	7676	1			T15	127		T77	2406		T16	13
alert[0x2]	5058	1			T15	182		T77	237		T8	1
alert[0x3]	4286	1			T21	1		T79	155		T24	2
alert[0x4]	3576	1			T21	4		T15	113		T32	20
alert[0x5]	5226	1			T1	23		T22	75		T9	1
alert[0x6]	3514	1			T19	9		T15	59		T16	2
alert[0x7]	4146	1			T15	332		T16	3		T79	46
alert[0x8]	4050	1			T16	59		T24	6		T51	230
alert[0x9]	5503	1			T1	14		T77	32		T16	34
alert[0xa]	11509	1			T16	66		T32	1		T46	9
alert[0xb]	17021	1			T21	81		T15	22		T16	77
alert[0xc]	10600	1			T21	151		T24	7		T46	49
alert[0xd]	5495	1			T21	43		T15	205		T77	275
alert[0xe]	3371	1			T77	45		T16	29		T9	1
alert[0xf]	3114	1			T15	217		T77	3		T79	15
alert[0x10]	2873	1			T19	3		T26	1		T8	1
alert[0x11]	3908	1			T21	54		T15	91		T23	60
alert[0x12]	8819	1			T16	283		T79	19		T23	9
alert[0x13]	4615	1			T1	21		T15	6		T16	117
alert[0x14]	8651	1			T79	270		T24	32		T235	1
alert[0x15]	5071	1			T16	59		T79	518		T9	1
alert[0x16]	4020	1			T77	215		T50	410		T181	1
alert[0x17]	9762	1			T16	737		T79	233		T28	3
alert[0x18]	4637	1			T1	3		T15	42		T50	138
alert[0x19]	3238	1			T21	66		T16	186		T26	5
alert[0x1a]	6618	1			T19	34		T21	7		T15	35
alert[0x1b]	11131	1			T1	21		T16	811		T79	235
alert[0x1c]	13927	1			T21	4		T77	609		T45	1
alert[0x1d]	4132	1			T15	42		T8	2		T23	9
alert[0x1e]	4435	1			T77	227		T16	11		T8	2
alert[0x1f]	4243	1			T21	17		T76	1		T23	6
alert[0x20]	7569	1			T26	5		T79	75		T291	1
alert[0x21]	5632	1			T15	20		T16	192		T23	3
alert[0x22]	11284	1			T19	2		T21	4		T15	61
alert[0x23]	4019	1			T15	41		T16	25		T79	174
alert[0x24]	7325	1			T1	5		T77	83		T76	13
alert[0x25]	10265	1			T1	1		T16	575		T79	314
alert[0x26]	6340	1			T21	5		T15	10		T16	85
alert[0x27]	3428	1			T1	10		T16	27		T79	130
alert[0x28]	2985	1			T1	1		T21	5		T16	81
alert[0x29]	3888	1			T16	78		T23	30		T45	4
alert[0x2a]	6548	1			T15	2		T16	8		T79	95
alert[0x2b]	2952	1			T16	7		T7	2		T79	51
alert[0x2c]	2592	1			T9	1		T32	11		T10	1
alert[0x2d]	2057	1			T15	357		T77	55		T79	26
alert[0x2e]	3657	1			T19	31		T16	3		T110	130
alert[0x2f]	11741	1			T16	25		T79	7		T8	2
alert[0x30]	4128	1			T1	1		T15	425		T16	56
alert[0x31]	6978	1			T15	775		T76	1		T46	440
alert[0x32]	10323	1			T1	2		T15	772		T16	18
alert[0x33]	17304	1			T21	39		T77	84		T79	19
alert[0x34]	5471	1			T8	1		T9	1		T32	4
alert[0x35]	5548	1			T16	58		T74	1		T26	2
alert[0x36]	3535	1			T15	191		T16	10		T26	36
alert[0x37]	6395	1			T19	2		T16	5		T76	2
alert[0x38]	5718	1			T1	5		T16	600		T28	47
alert[0x39]	3806	1			T1	14		T15	8		T77	105
alert[0x3a]	2758	1			T15	12		T79	14		T8	1
alert[0x3b]	6466	1			T26	1		T23	188		T9	1
alert[0x3c]	2896	1			T1	8		T19	32		T8	1
alert[0x3d]	4053	1			T19	1		T21	17		T15	134
alert[0x3e]	9335	1			T16	1216		T26	39		T79	24
alert[0x3f]	4994	1			T1	5		T26	17		T79	557
alert[0x40]	3486	1			T15	24		T77	22		T23	7

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	130748	1			T15	4305		T77	4571		T16	7445
class_i[0x1]	54879	1			T1	14		T9	2		T32	2
class_i[0x2]	119793	1			T1	17		T19	114		T15	15
class_i[0x3]	87559	1			T1	103		T21	498		T74	3

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

392278

1

T1

134

T19

114

T21

498

alert_ping_fail

701

1

T7

2

T8

18

T9

14

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	3268	1			T15	15		T77	173		T16	43
alert_integrity_fail	alert[0x1]	7666	1			T15	127		T77	2406		T16	13
alert_integrity_fail	alert[0x2]	5051	1			T15	182		T77	237		T24	3
alert_integrity_fail	alert[0x3]	4272	1			T21	1		T79	155		T24	2
alert_integrity_fail	alert[0x4]	3564	1			T21	4		T15	113		T32	20
alert_integrity_fail	alert[0x5]	5211	1			T1	23		T22	75		T24	5
alert_integrity_fail	alert[0x6]	3501	1			T19	9		T15	59		T16	2
alert_integrity_fail	alert[0x7]	4128	1			T15	332		T16	3		T79	46
alert_integrity_fail	alert[0x8]	4038	1			T16	59		T24	6		T51	230
alert_integrity_fail	alert[0x9]	5491	1			T1	14		T77	32		T16	34
alert_integrity_fail	alert[0xa]	11500	1			T16	66		T32	1		T46	9
alert_integrity_fail	alert[0xb]	17009	1			T21	81		T15	22		T16	77
alert_integrity_fail	alert[0xc]	10594	1			T21	151		T24	7		T46	49
alert_integrity_fail	alert[0xd]	5488	1			T21	43		T15	205		T77	275
alert_integrity_fail	alert[0xe]	3358	1			T77	45		T16	29		T51	9
alert_integrity_fail	alert[0xf]	3102	1			T15	217		T77	3		T79	15
alert_integrity_fail	alert[0x10]	2861	1			T19	3		T26	1		T23	97
alert_integrity_fail	alert[0x11]	3897	1			T21	54		T15	91		T23	60
alert_integrity_fail	alert[0x12]	8809	1			T16	283		T79	19		T23	9
alert_integrity_fail	alert[0x13]	4603	1			T1	21		T15	6		T16	117
alert_integrity_fail	alert[0x14]	8636	1			T79	270		T24	32		T52	80
alert_integrity_fail	alert[0x15]	5058	1			T16	59		T79	518		T46	40
alert_integrity_fail	alert[0x16]	4006	1			T77	215		T50	410		T52	38
alert_integrity_fail	alert[0x17]	9757	1			T16	737		T79	233		T28	3
alert_integrity_fail	alert[0x18]	4632	1			T1	3		T15	42		T50	138
alert_integrity_fail	alert[0x19]	3227	1			T21	66		T16	186		T26	5
alert_integrity_fail	alert[0x1a]	6604	1			T19	34		T21	7		T15	35
alert_integrity_fail	alert[0x1b]	11126	1			T1	21		T16	811		T79	235
alert_integrity_fail	alert[0x1c]	13918	1			T21	4		T77	609		T45	1
alert_integrity_fail	alert[0x1d]	4122	1			T15	42		T23	9		T32	1
alert_integrity_fail	alert[0x1e]	4420	1			T77	227		T16	11		T23	11
alert_integrity_fail	alert[0x1f]	4225	1			T21	17		T76	1		T23	6
alert_integrity_fail	alert[0x20]	7558	1			T26	5		T79	75		T50	2265
alert_integrity_fail	alert[0x21]	5619	1			T15	20		T16	192		T23	3
alert_integrity_fail	alert[0x22]	11274	1			T19	2		T21	4		T15	61
alert_integrity_fail	alert[0x23]	4005	1			T15	41		T16	25		T79	174
alert_integrity_fail	alert[0x24]	7317	1			T1	5		T77	83		T76	13
alert_integrity_fail	alert[0x25]	10258	1			T1	1		T16	575		T79	314
alert_integrity_fail	alert[0x26]	6332	1			T21	5		T15	10		T16	85
alert_integrity_fail	alert[0x27]	3420	1			T1	10		T16	27		T79	130
alert_integrity_fail	alert[0x28]	2975	1			T1	1		T21	5		T16	81
alert_integrity_fail	alert[0x29]	3876	1			T16	78		T23	30		T45	4
alert_integrity_fail	alert[0x2a]	6535	1			T15	2		T16	8		T79	95
alert_integrity_fail	alert[0x2b]	2942	1			T16	7		T79	51		T46	4
alert_integrity_fail	alert[0x2c]	2577	1			T32	11		T52	193		T54	553
alert_integrity_fail	alert[0x2d]	2046	1			T15	357		T77	55		T79	26
alert_integrity_fail	alert[0x2e]	3650	1			T19	31		T16	3		T110	130
alert_integrity_fail	alert[0x2f]	11726	1			T16	25		T79	7		T45	4
alert_integrity_fail	alert[0x30]	4121	1			T1	1		T15	425		T16	56
alert_integrity_fail	alert[0x31]	6964	1			T15	775		T76	1		T46	440
alert_integrity_fail	alert[0x32]	10314	1			T1	2		T15	772		T16	18
alert_integrity_fail	alert[0x33]	17295	1			T21	39		T77	84		T79	19
alert_integrity_fail	alert[0x34]	5456	1			T32	4		T50	36		T52	252
alert_integrity_fail	alert[0x35]	5537	1			T16	58		T74	1		T26	2
alert_integrity_fail	alert[0x36]	3527	1			T15	191		T16	10		T26	36
alert_integrity_fail	alert[0x37]	6388	1			T19	2		T16	5		T76	2
alert_integrity_fail	alert[0x38]	5706	1			T1	5		T16	600		T28	47
alert_integrity_fail	alert[0x39]	3799	1			T1	14		T15	8		T77	105
alert_integrity_fail	alert[0x3a]	2746	1			T15	12		T79	14		T23	28
alert_integrity_fail	alert[0x3b]	6452	1			T26	1		T23	188		T32	3
alert_integrity_fail	alert[0x3c]	2885	1			T1	8		T19	32		T45	2
alert_integrity_fail	alert[0x3d]	4045	1			T19	1		T21	17		T15	134
alert_integrity_fail	alert[0x3e]	9320	1			T16	1216		T26	39		T79	24
alert_integrity_fail	alert[0x3f]	4989	1			T1	5		T26	17		T79	557
alert_integrity_fail	alert[0x40]	3482	1			T15	24		T77	22		T23	7
alert_ping_fail	alert[0x0]	10	1			T8	1		T10	1		T181	1
alert_ping_fail	alert[0x1]	10	1			T8	2		T267	1		T292	1
alert_ping_fail	alert[0x2]	7	1			T8	1		T10	1		T292	2
alert_ping_fail	alert[0x3]	14	1			T181	1		T293	1		T216	1
alert_ping_fail	alert[0x4]	12	1			T181	1		T294	1		T293	1
alert_ping_fail	alert[0x5]	15	1			T9	1		T217	1		T295	1
alert_ping_fail	alert[0x6]	13	1			T283	1		T296	1		T293	1
alert_ping_fail	alert[0x7]	18	1			T10	1		T181	1		T297	1
alert_ping_fail	alert[0x8]	12	1			T293	3		T298	1		T292	1
alert_ping_fail	alert[0x9]	12	1			T293	1		T295	1		T299	1
alert_ping_fail	alert[0xa]	9	1			T235	1		T294	1		T216	1
alert_ping_fail	alert[0xb]	12	1			T285	1		T300	1		T301	1
alert_ping_fail	alert[0xc]	6	1			T10	2		T292	1		T301	1
alert_ping_fail	alert[0xd]	7	1			T294	1		T224	1		T302	1
alert_ping_fail	alert[0xe]	13	1			T9	1		T10	1		T303	1
alert_ping_fail	alert[0xf]	12	1			T10	2		T291	1		T216	1
alert_ping_fail	alert[0x10]	12	1			T8	1		T216	1		T304	1
alert_ping_fail	alert[0x11]	11	1			T216	2		T302	1		T295	1
alert_ping_fail	alert[0x12]	10	1			T10	1		T304	1		T302	1
alert_ping_fail	alert[0x13]	12	1			T9	1		T291	1		T293	1
alert_ping_fail	alert[0x14]	15	1			T235	1		T10	1		T296	1
alert_ping_fail	alert[0x15]	13	1			T9	1		T216	2		T217	1
alert_ping_fail	alert[0x16]	14	1			T181	1		T293	1		T224	1
alert_ping_fail	alert[0x17]	5	1			T291	1		T224	1		T305	1
alert_ping_fail	alert[0x18]	5	1			T306	1		T307	2		T308	1
alert_ping_fail	alert[0x19]	11	1			T303	1		T293	2		T309	1
alert_ping_fail	alert[0x1a]	14	1			T296	1		T291	1		T181	1
alert_ping_fail	alert[0x1b]	5	1			T310	1		T308	1		T311	2
alert_ping_fail	alert[0x1c]	9	1			T296	1		T217	2		T292	1
alert_ping_fail	alert[0x1d]	10	1			T8	2		T9	1		T10	1
alert_ping_fail	alert[0x1e]	15	1			T8	2		T9	1		T10	1
alert_ping_fail	alert[0x1f]	18	1			T9	1		T296	1		T224	1
alert_ping_fail	alert[0x20]	11	1			T291	1		T302	1		T285	2
alert_ping_fail	alert[0x21]	13	1			T294	1		T216	1		T304	1
alert_ping_fail	alert[0x22]	10	1			T297	1		T295	1		T97	2
alert_ping_fail	alert[0x23]	14	1			T8	1		T291	1		T224	1
alert_ping_fail	alert[0x24]	8	1			T216	1		T304	1		T312	1
alert_ping_fail	alert[0x25]	7	1			T296	1		T217	1		T313	1
alert_ping_fail	alert[0x26]	8	1			T10	1		T224	1		T302	2
alert_ping_fail	alert[0x27]	8	1			T285	1		T300	1		T301	1
alert_ping_fail	alert[0x28]	10	1			T10	1		T310	1		T314	1
alert_ping_fail	alert[0x29]	12	1			T293	1		T216	1		T304	1
alert_ping_fail	alert[0x2a]	13	1			T181	1		T294	1		T290	1
alert_ping_fail	alert[0x2b]	10	1			T7	2		T8	1		T10	1
alert_ping_fail	alert[0x2c]	15	1			T9	1		T10	1		T283	1
alert_ping_fail	alert[0x2d]	11	1			T285	1		T315	1		T299	1
alert_ping_fail	alert[0x2e]	7	1			T10	1		T216	1		T315	1
alert_ping_fail	alert[0x2f]	15	1			T8	2		T9	2		T296	1
alert_ping_fail	alert[0x30]	7	1			T224	1		T302	2		T313	1
alert_ping_fail	alert[0x31]	14	1			T10	1		T296	2		T224	1
alert_ping_fail	alert[0x32]	9	1			T293	1		T285	1		T316	1
alert_ping_fail	alert[0x33]	9	1			T224	1		T316	1		T317	1
alert_ping_fail	alert[0x34]	15	1			T8	1		T9	1		T224	2
alert_ping_fail	alert[0x35]	11	1			T296	1		T291	3		T224	1
alert_ping_fail	alert[0x36]	8	1			T9	1		T296	1		T293	1
alert_ping_fail	alert[0x37]	7	1			T294	1		T315	1		T318	1
alert_ping_fail	alert[0x38]	12	1			T10	2		T217	1		T285	1
alert_ping_fail	alert[0x39]	7	1			T293	1		T285	1		T319	1
alert_ping_fail	alert[0x3a]	12	1			T8	1		T291	1		T294	1
alert_ping_fail	alert[0x3b]	14	1			T9	1		T181	1		T303	1
alert_ping_fail	alert[0x3c]	11	1			T8	1		T181	1		T217	1
alert_ping_fail	alert[0x3d]	8	1			T10	1		T303	1		T224	1
alert_ping_fail	alert[0x3e]	15	1			T8	2		T9	1		T303	1
alert_ping_fail	alert[0x3f]	5	1			T299	1		T320	1		T319	1
alert_ping_fail	alert[0x40]	4	1			T295	1		T313	1		T321	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	130578	1			T15	4305		T77	4571		T16	7445
alert_integrity_fail	class_i[0x1]	54695	1			T1	14		T32	2		T45	54
alert_integrity_fail	class_i[0x2]	119641	1			T1	17		T19	114		T15	15
alert_integrity_fail	class_i[0x3]	87364	1			T1	103		T21	498		T74	3
alert_ping_fail	class_i[0x0]	170	1			T8	17		T9	1		T10	16
alert_ping_fail	class_i[0x1]	184	1			T9	2		T10	1		T296	13
alert_ping_fail	class_i[0x2]	152	1			T7	2		T9	2		T10	3
alert_ping_fail	class_i[0x3]	195	1			T8	1		T9	9		T235	2