Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.68 99.99 98.72 100.00 100.00 100.00 99.38 99.68


Total test records in report: 831
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T773 /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.1465558968 Apr 21 12:51:11 PM PDT 24 Apr 21 12:51:17 PM PDT 24 63697672 ps
T142 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.30053783 Apr 21 12:50:53 PM PDT 24 Apr 21 01:07:16 PM PDT 24 12843102120 ps
T774 /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.3238524800 Apr 21 12:50:54 PM PDT 24 Apr 21 12:51:29 PM PDT 24 8042679194 ps
T775 /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.4032220224 Apr 21 12:51:15 PM PDT 24 Apr 21 12:51:26 PM PDT 24 1203240725 ps
T776 /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.451792603 Apr 21 12:51:01 PM PDT 24 Apr 21 12:51:16 PM PDT 24 536336973 ps
T777 /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.2406480401 Apr 21 12:51:25 PM PDT 24 Apr 21 12:51:27 PM PDT 24 9723830 ps
T149 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.4124786740 Apr 21 12:50:55 PM PDT 24 Apr 21 01:01:52 PM PDT 24 9226563697 ps
T778 /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.697272326 Apr 21 12:51:06 PM PDT 24 Apr 21 12:51:13 PM PDT 24 142981133 ps
T779 /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.2382836677 Apr 21 12:51:18 PM PDT 24 Apr 21 12:51:21 PM PDT 24 20295030 ps
T780 /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.705694340 Apr 21 12:51:23 PM PDT 24 Apr 21 12:51:25 PM PDT 24 12268719 ps
T781 /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.3537974034 Apr 21 12:51:09 PM PDT 24 Apr 21 12:51:11 PM PDT 24 31299746 ps
T131 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.4061692155 Apr 21 12:51:09 PM PDT 24 Apr 21 12:52:43 PM PDT 24 777093015 ps
T164 /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.115973403 Apr 21 12:51:14 PM PDT 24 Apr 21 12:51:52 PM PDT 24 470967561 ps
T166 /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.4027339793 Apr 21 12:51:11 PM PDT 24 Apr 21 12:52:22 PM PDT 24 3683468908 ps
T782 /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.460322339 Apr 21 12:50:49 PM PDT 24 Apr 21 12:51:02 PM PDT 24 187071407 ps
T783 /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.1474276869 Apr 21 12:51:01 PM PDT 24 Apr 21 12:51:04 PM PDT 24 32620022 ps
T784 /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.1718065115 Apr 21 12:50:53 PM PDT 24 Apr 21 12:50:56 PM PDT 24 22029185 ps
T785 /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.1288699817 Apr 21 12:51:11 PM PDT 24 Apr 21 12:51:19 PM PDT 24 106724231 ps
T137 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.3675336392 Apr 21 12:50:58 PM PDT 24 Apr 21 12:55:03 PM PDT 24 14266918794 ps
T786 /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.1444419287 Apr 21 12:51:27 PM PDT 24 Apr 21 12:51:29 PM PDT 24 11581956 ps
T787 /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.2016969813 Apr 21 12:51:20 PM PDT 24 Apr 21 12:51:22 PM PDT 24 12363105 ps
T788 /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.4198717018 Apr 21 12:51:19 PM PDT 24 Apr 21 12:51:21 PM PDT 24 10798423 ps
T173 /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.2069530572 Apr 21 12:50:53 PM PDT 24 Apr 21 12:50:56 PM PDT 24 126458229 ps
T789 /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.1407413438 Apr 21 12:51:09 PM PDT 24 Apr 21 12:51:11 PM PDT 24 13134173 ps
T790 /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.1274137590 Apr 21 12:51:03 PM PDT 24 Apr 21 12:51:05 PM PDT 24 11108583 ps
T161 /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.3371108036 Apr 21 12:51:18 PM PDT 24 Apr 21 12:51:59 PM PDT 24 632463597 ps
T791 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.531953698 Apr 21 12:51:05 PM PDT 24 Apr 21 12:51:06 PM PDT 24 6306542 ps
T792 /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.4227419950 Apr 21 12:50:52 PM PDT 24 Apr 21 12:51:03 PM PDT 24 79676313 ps
T793 /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.49577412 Apr 21 12:51:26 PM PDT 24 Apr 21 12:51:28 PM PDT 24 10190715 ps
T794 /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.4250750260 Apr 21 12:50:57 PM PDT 24 Apr 21 12:51:04 PM PDT 24 46156666 ps
T795 /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.291361471 Apr 21 12:50:55 PM PDT 24 Apr 21 12:51:25 PM PDT 24 408602568 ps
T165 /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.4078391389 Apr 21 12:51:25 PM PDT 24 Apr 21 12:51:29 PM PDT 24 63297524 ps
T148 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2081839280 Apr 21 12:51:01 PM PDT 24 Apr 21 12:56:05 PM PDT 24 18334842558 ps
T796 /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.4198583412 Apr 21 12:50:58 PM PDT 24 Apr 21 12:51:03 PM PDT 24 158988308 ps
T797 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.2336548095 Apr 21 12:51:05 PM PDT 24 Apr 21 12:51:07 PM PDT 24 7007594 ps
T798 /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.1857837132 Apr 21 12:51:01 PM PDT 24 Apr 21 12:51:12 PM PDT 24 68344513 ps
T152 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.1560737803 Apr 21 12:51:01 PM PDT 24 Apr 21 01:00:27 PM PDT 24 16645586267 ps
T799 /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.3682345808 Apr 21 12:51:31 PM PDT 24 Apr 21 12:51:33 PM PDT 24 50188499 ps
T800 /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2373053073 Apr 21 12:51:06 PM PDT 24 Apr 21 12:51:18 PM PDT 24 532026892 ps
T141 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.4105395594 Apr 21 12:51:11 PM PDT 24 Apr 21 12:54:29 PM PDT 24 3361254029 ps
T195 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.817902269 Apr 21 12:51:09 PM PDT 24 Apr 21 12:52:52 PM PDT 24 867925254 ps
T801 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.4187177133 Apr 21 12:50:53 PM PDT 24 Apr 21 12:59:06 PM PDT 24 6458685617 ps
T802 /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.923472284 Apr 21 12:51:17 PM PDT 24 Apr 21 12:51:19 PM PDT 24 14918365 ps
T803 /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.2602436577 Apr 21 12:50:54 PM PDT 24 Apr 21 12:50:55 PM PDT 24 9468349 ps
T145 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.4246283069 Apr 21 12:51:09 PM PDT 24 Apr 21 01:00:17 PM PDT 24 9143329646 ps
T804 /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.4208982266 Apr 21 12:50:57 PM PDT 24 Apr 21 12:53:33 PM PDT 24 4397451194 ps
T159 /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.1074829109 Apr 21 12:51:06 PM PDT 24 Apr 21 12:51:13 PM PDT 24 117390155 ps
T805 /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.46081698 Apr 21 12:51:11 PM PDT 24 Apr 21 12:51:19 PM PDT 24 94272461 ps
T806 /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.748430152 Apr 21 12:51:12 PM PDT 24 Apr 21 12:51:19 PM PDT 24 135013042 ps
T151 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.193617359 Apr 21 12:51:19 PM PDT 24 Apr 21 12:57:07 PM PDT 24 3625534824 ps
T807 /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.2613009640 Apr 21 12:50:58 PM PDT 24 Apr 21 12:51:11 PM PDT 24 621123039 ps
T808 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.192175757 Apr 21 12:50:52 PM PDT 24 Apr 21 12:52:44 PM PDT 24 1095273311 ps
T809 /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.902430765 Apr 21 12:51:05 PM PDT 24 Apr 21 12:51:11 PM PDT 24 53312462 ps
T168 /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.2613108257 Apr 21 12:50:55 PM PDT 24 Apr 21 12:52:19 PM PDT 24 2388514512 ps
T810 /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.1979778492 Apr 21 12:50:55 PM PDT 24 Apr 21 12:51:35 PM PDT 24 1206859589 ps
T811 /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.574262066 Apr 21 12:50:59 PM PDT 24 Apr 21 12:51:05 PM PDT 24 33584859 ps
T147 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.796709826 Apr 21 12:51:19 PM PDT 24 Apr 21 12:58:29 PM PDT 24 6776745780 ps
T812 /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.2374292756 Apr 21 12:51:12 PM PDT 24 Apr 21 12:51:17 PM PDT 24 111785693 ps
T813 /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1550875994 Apr 21 12:51:17 PM PDT 24 Apr 21 12:51:19 PM PDT 24 11206479 ps
T160 /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.573285815 Apr 21 12:51:02 PM PDT 24 Apr 21 12:51:06 PM PDT 24 646132345 ps
T814 /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1481258884 Apr 21 12:50:57 PM PDT 24 Apr 21 12:51:15 PM PDT 24 868906471 ps
T143 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.182542249 Apr 21 12:51:14 PM PDT 24 Apr 21 01:01:22 PM PDT 24 4723667108 ps
T815 /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.4097366196 Apr 21 12:51:28 PM PDT 24 Apr 21 12:51:30 PM PDT 24 15182966 ps
T816 /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.2781000927 Apr 21 12:51:24 PM PDT 24 Apr 21 12:51:26 PM PDT 24 9365417 ps
T817 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.207017285 Apr 21 12:50:55 PM PDT 24 Apr 21 12:56:07 PM PDT 24 4163061110 ps
T818 /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.2975196937 Apr 21 12:50:54 PM PDT 24 Apr 21 12:53:45 PM PDT 24 4830005695 ps
T819 /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.3416946882 Apr 21 12:51:21 PM PDT 24 Apr 21 12:51:37 PM PDT 24 300640687 ps
T820 /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.3030595933 Apr 21 12:50:50 PM PDT 24 Apr 21 12:51:04 PM PDT 24 204444956 ps
T821 /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.3366741645 Apr 21 12:50:59 PM PDT 24 Apr 21 12:52:08 PM PDT 24 571852463 ps
T822 /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.3756219867 Apr 21 12:50:51 PM PDT 24 Apr 21 12:54:04 PM PDT 24 2975494325 ps
T823 /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.1217837098 Apr 21 12:51:07 PM PDT 24 Apr 21 12:51:28 PM PDT 24 2254735191 ps
T146 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.2825130499 Apr 21 12:51:11 PM PDT 24 Apr 21 12:56:30 PM PDT 24 16052218326 ps
T824 /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.1618937040 Apr 21 12:50:53 PM PDT 24 Apr 21 12:50:55 PM PDT 24 24192927 ps
T825 /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.3023027241 Apr 21 12:51:05 PM PDT 24 Apr 21 12:51:16 PM PDT 24 149784897 ps
T826 /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.3347197917 Apr 21 12:51:12 PM PDT 24 Apr 21 12:51:13 PM PDT 24 18643431 ps
T827 /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.3880395573 Apr 21 12:50:45 PM PDT 24 Apr 21 12:51:09 PM PDT 24 347127766 ps
T828 /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.2540656794 Apr 21 12:50:48 PM PDT 24 Apr 21 12:50:50 PM PDT 24 17206249 ps
T829 /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.51695300 Apr 21 12:50:57 PM PDT 24 Apr 21 12:51:03 PM PDT 24 97075254 ps
T150 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1980725699 Apr 21 12:50:51 PM PDT 24 Apr 21 01:07:44 PM PDT 24 15079210584 ps
T830 /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.3135907332 Apr 21 12:51:10 PM PDT 24 Apr 21 12:51:20 PM PDT 24 1336922415 ps
T831 /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.2677382035 Apr 21 12:51:04 PM PDT 24 Apr 21 12:51:29 PM PDT 24 355016541 ps

Test location /workspace/coverage/default/28.alert_handler_stress_all.3843629415
Short name T1
Test name
Test status
Simulation time 75894909411 ps
CPU time 2309.54 seconds
Started Apr 21 04:20:13 PM PDT 24
Finished Apr 21 04:58:43 PM PDT 24
Peak memory 289012 kb
Host smart-e4ced5a9-5511-4ebd-afb5-b726a7fb8e41
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843629415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.3843629415
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.3582889623
Short name T21
Test name
Test status
Simulation time 29589953475 ps
CPU time 1152.42 seconds
Started Apr 21 04:18:48 PM PDT 24
Finished Apr 21 04:38:01 PM PDT 24
Peak memory 273896 kb
Host smart-98496498-4e2c-4bfc-9429-cb4c11b2444e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582889623 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.3582889623
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.84017692
Short name T11
Test name
Test status
Simulation time 961488476 ps
CPU time 28.48 seconds
Started Apr 21 04:17:14 PM PDT 24
Finished Apr 21 04:17:42 PM PDT 24
Peak memory 269340 kb
Host smart-66c709cb-286c-48c8-898d-d9c25adb698b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=84017692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.84017692
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.531776786
Short name T153
Test name
Test status
Simulation time 294514097 ps
CPU time 22.6 seconds
Started Apr 21 12:50:49 PM PDT 24
Finished Apr 21 12:51:12 PM PDT 24
Peak memory 239916 kb
Host smart-d107f4bf-c736-430c-8c25-3f77f4a55904
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=531776786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.531776786
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.404844439
Short name T46
Test name
Test status
Simulation time 44524029456 ps
CPU time 2599.74 seconds
Started Apr 21 04:17:05 PM PDT 24
Finished Apr 21 05:00:25 PM PDT 24
Peak memory 289376 kb
Host smart-2ef8677f-4c1a-4f7a-8e8e-6c1d029bdd7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404844439 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.404844439
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.3152695882
Short name T32
Test name
Test status
Simulation time 679263440082 ps
CPU time 2781.1 seconds
Started Apr 21 04:21:09 PM PDT 24
Finished Apr 21 05:07:30 PM PDT 24
Peak memory 289412 kb
Host smart-139c4702-ee05-4438-b81c-09a4273a74d7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152695882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.3152695882
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.3804745798
Short name T90
Test name
Test status
Simulation time 14683171769 ps
CPU time 1399.82 seconds
Started Apr 21 04:19:09 PM PDT 24
Finished Apr 21 04:42:30 PM PDT 24
Peak memory 281972 kb
Host smart-6b75800a-5398-49ba-97b6-714fb3ec232d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804745798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.3804745798
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.4288349483
Short name T134
Test name
Test status
Simulation time 4197285061 ps
CPU time 305.08 seconds
Started Apr 21 12:51:07 PM PDT 24
Finished Apr 21 12:56:13 PM PDT 24
Peak memory 264820 kb
Host smart-1b99f167-bd63-42b3-a51a-5bb26c63a8c3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4288349483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.4288349483
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.2447302430
Short name T50
Test name
Test status
Simulation time 16745103527 ps
CPU time 1665 seconds
Started Apr 21 04:23:10 PM PDT 24
Finished Apr 21 04:50:55 PM PDT 24
Peak memory 289772 kb
Host smart-d102aa23-aa69-4ad3-afa0-a9e14bdfdf65
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447302430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.2447302430
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.199436137
Short name T267
Test name
Test status
Simulation time 254622706999 ps
CPU time 3581.51 seconds
Started Apr 21 04:17:50 PM PDT 24
Finished Apr 21 05:17:32 PM PDT 24
Peak memory 289548 kb
Host smart-2f8afd72-137c-43f9-aea1-d29317216222
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199436137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.199436137
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.601913406
Short name T121
Test name
Test status
Simulation time 4146291514 ps
CPU time 584.38 seconds
Started Apr 21 12:51:00 PM PDT 24
Finished Apr 21 01:00:44 PM PDT 24
Peak memory 271012 kb
Host smart-0e85e3b2-7ebf-4cc8-8142-9e4faa60fc77
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601913406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.601913406
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.3150948423
Short name T251
Test name
Test status
Simulation time 62195622107 ps
CPU time 3530.17 seconds
Started Apr 21 04:18:37 PM PDT 24
Finished Apr 21 05:17:28 PM PDT 24
Peak memory 290136 kb
Host smart-46054ce1-a58a-4808-85fd-07bd61910061
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150948423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.3150948423
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.3462096243
Short name T109
Test name
Test status
Simulation time 48848510557 ps
CPU time 1078.7 seconds
Started Apr 21 04:22:34 PM PDT 24
Finished Apr 21 04:40:33 PM PDT 24
Peak memory 284472 kb
Host smart-3e1e0fa3-c54b-46f8-89e9-daf6df41597c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462096243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.3462096243
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.1864113147
Short name T2
Test name
Test status
Simulation time 482437738 ps
CPU time 12.86 seconds
Started Apr 21 04:18:37 PM PDT 24
Finished Apr 21 04:18:50 PM PDT 24
Peak memory 240836 kb
Host smart-0704b7a9-7ddc-432f-a316-76ee4a0202f3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1864113147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.1864113147
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.3374638050
Short name T97
Test name
Test status
Simulation time 84117938757 ps
CPU time 2719.17 seconds
Started Apr 21 04:17:26 PM PDT 24
Finished Apr 21 05:02:45 PM PDT 24
Peak memory 289472 kb
Host smart-2c906432-4db8-4d03-ad39-f2b707031441
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374638050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.3374638050
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.712369491
Short name T118
Test name
Test status
Simulation time 58777127436 ps
CPU time 940.11 seconds
Started Apr 21 12:50:53 PM PDT 24
Finished Apr 21 01:06:34 PM PDT 24
Peak memory 264792 kb
Host smart-1142080f-d91f-4aed-a2c1-98eb0492a7ce
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712369491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.712369491
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.2966259813
Short name T25
Test name
Test status
Simulation time 26268349064 ps
CPU time 1767.03 seconds
Started Apr 21 04:21:32 PM PDT 24
Finished Apr 21 04:51:00 PM PDT 24
Peak memory 282084 kb
Host smart-8fb9d0c3-2659-45cc-be25-3c6e5de7ab31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966259813 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.2966259813
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.70440812
Short name T127
Test name
Test status
Simulation time 6756550460 ps
CPU time 194.96 seconds
Started Apr 21 12:50:58 PM PDT 24
Finished Apr 21 12:54:13 PM PDT 24
Peak memory 264776 kb
Host smart-3b286e36-33f4-453e-8de3-9beb3b16d18a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=70440812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_errors
.70440812
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.468998823
Short name T10
Test name
Test status
Simulation time 51079807997 ps
CPU time 585.15 seconds
Started Apr 21 04:23:05 PM PDT 24
Finished Apr 21 04:32:50 PM PDT 24
Peak memory 248320 kb
Host smart-ec17ec5b-7078-4fca-9378-d0f0e2f718ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468998823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.468998823
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.3333455713
Short name T348
Test name
Test status
Simulation time 13492129 ps
CPU time 1.38 seconds
Started Apr 21 12:51:18 PM PDT 24
Finished Apr 21 12:51:19 PM PDT 24
Peak memory 236084 kb
Host smart-6c93fd75-5247-4166-b859-a37d77a197b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3333455713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.3333455713
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.1695497378
Short name T289
Test name
Test status
Simulation time 64397875384 ps
CPU time 2240.33 seconds
Started Apr 21 04:23:18 PM PDT 24
Finished Apr 21 05:00:39 PM PDT 24
Peak memory 281968 kb
Host smart-90440510-c0b2-4888-9211-230fae08ee92
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695497378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.1695497378
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.1512749549
Short name T126
Test name
Test status
Simulation time 70851172158 ps
CPU time 941.92 seconds
Started Apr 21 12:51:12 PM PDT 24
Finished Apr 21 01:06:54 PM PDT 24
Peak memory 272252 kb
Host smart-d7120baf-e4a5-4579-8794-28d85556f8fb
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512749549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.1512749549
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.1076380113
Short name T52
Test name
Test status
Simulation time 16067610873 ps
CPU time 1812.43 seconds
Started Apr 21 04:24:44 PM PDT 24
Finished Apr 21 04:54:56 PM PDT 24
Peak memory 290152 kb
Host smart-a61b294d-f451-477a-9be8-5b23271316b3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076380113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.1076380113
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.4105395594
Short name T141
Test name
Test status
Simulation time 3361254029 ps
CPU time 197.48 seconds
Started Apr 21 12:51:11 PM PDT 24
Finished Apr 21 12:54:29 PM PDT 24
Peak memory 265080 kb
Host smart-403a5da8-628a-495e-9156-3272255be9e9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4105395594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.4105395594
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.232005482
Short name T293
Test name
Test status
Simulation time 12242967530 ps
CPU time 473.24 seconds
Started Apr 21 04:18:22 PM PDT 24
Finished Apr 21 04:26:16 PM PDT 24
Peak memory 248360 kb
Host smart-ca5716d6-56df-4277-9d01-fca0ba39d02c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232005482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.232005482
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.3881483148
Short name T326
Test name
Test status
Simulation time 218582262307 ps
CPU time 3063.86 seconds
Started Apr 21 04:23:05 PM PDT 24
Finished Apr 21 05:14:10 PM PDT 24
Peak memory 285320 kb
Host smart-f32a4f5e-3286-431e-9855-541f8125ce2a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881483148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.3881483148
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.3954170778
Short name T320
Test name
Test status
Simulation time 27548547999 ps
CPU time 628.63 seconds
Started Apr 21 04:23:49 PM PDT 24
Finished Apr 21 04:34:17 PM PDT 24
Peak memory 247244 kb
Host smart-871956ff-0497-4ffd-90b6-d4c16737f5ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954170778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.3954170778
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.1505158596
Short name T51
Test name
Test status
Simulation time 403263583096 ps
CPU time 8581.44 seconds
Started Apr 21 04:20:45 PM PDT 24
Finished Apr 21 06:43:48 PM PDT 24
Peak memory 370804 kb
Host smart-b835a74c-8c0a-48dd-8f91-b65a6cedfd41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505158596 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.1505158596
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.1014821919
Short name T123
Test name
Test status
Simulation time 5178946847 ps
CPU time 688.47 seconds
Started Apr 21 12:51:04 PM PDT 24
Finished Apr 21 01:02:33 PM PDT 24
Peak memory 264768 kb
Host smart-9c7e4325-7373-42bc-ab5b-232c33042894
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014821919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.1014821919
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.3518330080
Short name T235
Test name
Test status
Simulation time 26292080624 ps
CPU time 1468.57 seconds
Started Apr 21 04:17:05 PM PDT 24
Finished Apr 21 04:41:34 PM PDT 24
Peak memory 265544 kb
Host smart-9213fb42-8ab0-4c01-940b-4ae0107254fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518330080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.3518330080
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.220187704
Short name T256
Test name
Test status
Simulation time 39220209016 ps
CPU time 2245.79 seconds
Started Apr 21 04:24:24 PM PDT 24
Finished Apr 21 05:01:51 PM PDT 24
Peak memory 285452 kb
Host smart-4037ab83-f6e7-4055-8847-924a0e585d1d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220187704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_han
dler_stress_all.220187704
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.2843711450
Short name T119
Test name
Test status
Simulation time 11220005873 ps
CPU time 335.38 seconds
Started Apr 21 12:51:19 PM PDT 24
Finished Apr 21 12:56:55 PM PDT 24
Peak memory 264812 kb
Host smart-73f538c3-39e7-403d-9c4a-2edffa302498
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2843711450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.2843711450
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1980725699
Short name T150
Test name
Test status
Simulation time 15079210584 ps
CPU time 1012.91 seconds
Started Apr 21 12:50:51 PM PDT 24
Finished Apr 21 01:07:44 PM PDT 24
Peak memory 264824 kb
Host smart-fa609a86-154b-41ff-a8db-4d65840d2a03
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980725699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.1980725699
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.3383660052
Short name T705
Test name
Test status
Simulation time 69532322970 ps
CPU time 678.34 seconds
Started Apr 21 04:21:10 PM PDT 24
Finished Apr 21 04:32:29 PM PDT 24
Peak memory 248564 kb
Host smart-e9ddb2f0-fa26-4f97-8251-7ec2b8f4da44
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383660052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.3383660052
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.34897484
Short name T258
Test name
Test status
Simulation time 59361678801 ps
CPU time 2465.5 seconds
Started Apr 21 04:22:53 PM PDT 24
Finished Apr 21 05:03:59 PM PDT 24
Peak memory 281980 kb
Host smart-b5150afb-fd81-4e99-af62-5648b7726952
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34897484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_hand
ler_stress_all.34897484
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.2880814675
Short name T324
Test name
Test status
Simulation time 83519047967 ps
CPU time 2595.09 seconds
Started Apr 21 04:20:23 PM PDT 24
Finished Apr 21 05:03:39 PM PDT 24
Peak memory 282140 kb
Host smart-15ae531e-915b-4e82-9021-eda9d9799b51
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880814675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.2880814675
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.3519199697
Short name T8
Test name
Test status
Simulation time 51373712514 ps
CPU time 553.6 seconds
Started Apr 21 04:24:54 PM PDT 24
Finished Apr 21 04:34:08 PM PDT 24
Peak memory 248096 kb
Host smart-9ec6593b-5b4e-43bb-90af-3e7f5c20262a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519199697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.3519199697
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.3937530543
Short name T157
Test name
Test status
Simulation time 7708055 ps
CPU time 1.34 seconds
Started Apr 21 12:50:59 PM PDT 24
Finished Apr 21 12:51:01 PM PDT 24
Peak memory 236148 kb
Host smart-4fd8d237-1382-45de-b0a2-0f0225bb8040
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3937530543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.3937530543
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.1817513951
Short name T249
Test name
Test status
Simulation time 98030026728 ps
CPU time 6481.19 seconds
Started Apr 21 04:18:38 PM PDT 24
Finished Apr 21 06:06:40 PM PDT 24
Peak memory 331232 kb
Host smart-9c79c30c-6963-48de-8b1d-15550e1f9bb3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817513951 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.1817513951
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.1727466507
Short name T329
Test name
Test status
Simulation time 81004664435 ps
CPU time 2155.28 seconds
Started Apr 21 04:22:48 PM PDT 24
Finished Apr 21 04:58:43 PM PDT 24
Peak memory 271744 kb
Host smart-c692d287-c9b3-4f8b-b881-b213de008c41
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727466507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.1727466507
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.892972006
Short name T163
Test name
Test status
Simulation time 391450544 ps
CPU time 3.02 seconds
Started Apr 21 12:50:57 PM PDT 24
Finished Apr 21 12:51:00 PM PDT 24
Peak memory 236104 kb
Host smart-a4d60e08-9816-416a-ada2-597d3c015369
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=892972006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.892972006
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.3128442916
Short name T15
Test name
Test status
Simulation time 230860556504 ps
CPU time 3329.28 seconds
Started Apr 21 04:24:07 PM PDT 24
Finished Apr 21 05:19:37 PM PDT 24
Peak memory 289724 kb
Host smart-f856224a-8f68-4fe2-8860-a25f0ae6d8b2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128442916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.3128442916
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.176098427
Short name T122
Test name
Test status
Simulation time 9485774543 ps
CPU time 206.76 seconds
Started Apr 21 12:50:52 PM PDT 24
Finished Apr 21 12:54:19 PM PDT 24
Peak memory 264824 kb
Host smart-8a41d61e-1a1e-47b4-badd-40048a057563
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=176098427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_error
s.176098427
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.1278829979
Short name T186
Test name
Test status
Simulation time 7419453828 ps
CPU time 402.88 seconds
Started Apr 21 12:50:56 PM PDT 24
Finished Apr 21 12:57:39 PM PDT 24
Peak memory 235260 kb
Host smart-78017ec6-03cb-4a5a-b507-dd647d8f00d8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1278829979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.1278829979
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.2032300409
Short name T318
Test name
Test status
Simulation time 196365533557 ps
CPU time 593.97 seconds
Started Apr 21 04:18:04 PM PDT 24
Finished Apr 21 04:27:59 PM PDT 24
Peak memory 248112 kb
Host smart-79b00219-b825-4d64-9fc8-55a8ee0480df
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032300409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.2032300409
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.1518978690
Short name T299
Test name
Test status
Simulation time 16888628913 ps
CPU time 363.88 seconds
Started Apr 21 04:21:13 PM PDT 24
Finished Apr 21 04:27:17 PM PDT 24
Peak memory 247324 kb
Host smart-d18ea523-e71c-405a-b9fb-9eeb3fe7fe26
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518978690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.1518978690
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.256051089
Short name T250
Test name
Test status
Simulation time 458229335421 ps
CPU time 2163.32 seconds
Started Apr 21 04:17:49 PM PDT 24
Finished Apr 21 04:53:52 PM PDT 24
Peak memory 290260 kb
Host smart-43191bd5-cc03-4373-b046-f9b476bc36b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256051089 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.256051089
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.2382409231
Short name T129
Test name
Test status
Simulation time 8508193766 ps
CPU time 435.41 seconds
Started Apr 21 12:51:05 PM PDT 24
Finished Apr 21 12:58:21 PM PDT 24
Peak memory 264736 kb
Host smart-cbb40e10-28dd-4cf3-8579-a229b27b7315
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382409231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.2382409231
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.4107856260
Short name T207
Test name
Test status
Simulation time 122669774 ps
CPU time 2.47 seconds
Started Apr 21 04:16:54 PM PDT 24
Finished Apr 21 04:16:57 PM PDT 24
Peak memory 249388 kb
Host smart-f55c8c84-2447-49b6-975a-9811acad36eb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4107856260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.4107856260
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.1402956433
Short name T203
Test name
Test status
Simulation time 64086523 ps
CPU time 2.85 seconds
Started Apr 21 04:16:57 PM PDT 24
Finished Apr 21 04:17:00 PM PDT 24
Peak memory 249340 kb
Host smart-2f9ea994-be5e-4749-b4bc-21bc9b648729
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1402956433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.1402956433
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.625531264
Short name T212
Test name
Test status
Simulation time 136892892 ps
CPU time 3.46 seconds
Started Apr 21 04:18:13 PM PDT 24
Finished Apr 21 04:18:17 PM PDT 24
Peak memory 249340 kb
Host smart-49da92dd-e689-4e73-9759-05c9ddb9eea0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=625531264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.625531264
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.3663262154
Short name T202
Test name
Test status
Simulation time 63856716 ps
CPU time 3.68 seconds
Started Apr 21 04:18:48 PM PDT 24
Finished Apr 21 04:18:52 PM PDT 24
Peak memory 249388 kb
Host smart-e129ec0e-8605-4066-828a-b885d468c79c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3663262154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.3663262154
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.1597637717
Short name T350
Test name
Test status
Simulation time 9953071 ps
CPU time 1.4 seconds
Started Apr 21 12:51:07 PM PDT 24
Finished Apr 21 12:51:09 PM PDT 24
Peak memory 236112 kb
Host smart-8ca712c1-733b-4075-8b47-df87761854df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1597637717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.1597637717
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.1878954320
Short name T252
Test name
Test status
Simulation time 120498195 ps
CPU time 8.45 seconds
Started Apr 21 04:18:43 PM PDT 24
Finished Apr 21 04:18:52 PM PDT 24
Peak memory 251876 kb
Host smart-544fd6a4-cde1-496b-91cd-f52567e4f326
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18789
54320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.1878954320
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.478803429
Short name T334
Test name
Test status
Simulation time 38892024473 ps
CPU time 1004.75 seconds
Started Apr 21 04:19:33 PM PDT 24
Finished Apr 21 04:36:19 PM PDT 24
Peak memory 273588 kb
Host smart-e05b82dc-06fb-40c0-a049-6fd2c5b4e460
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478803429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.478803429
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.3153340148
Short name T247
Test name
Test status
Simulation time 1783604082 ps
CPU time 55.27 seconds
Started Apr 21 04:20:07 PM PDT 24
Finished Apr 21 04:21:02 PM PDT 24
Peak memory 254348 kb
Host smart-0ad6e69d-a3ff-4fec-b0cd-4d619ba75ded
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31533
40148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.3153340148
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.3980052249
Short name T232
Test name
Test status
Simulation time 267915058379 ps
CPU time 3189.26 seconds
Started Apr 21 04:21:43 PM PDT 24
Finished Apr 21 05:14:53 PM PDT 24
Peak memory 306388 kb
Host smart-6bfd74c0-ec62-4a54-aabe-eefa4d1cd0c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980052249 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.3980052249
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.3779587200
Short name T333
Test name
Test status
Simulation time 33038469083 ps
CPU time 1142.57 seconds
Started Apr 21 04:23:29 PM PDT 24
Finished Apr 21 04:42:32 PM PDT 24
Peak memory 283832 kb
Host smart-c487681a-fc97-4329-b318-622fb61a0fbc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779587200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.3779587200
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.1622401491
Short name T162
Test name
Test status
Simulation time 822660195 ps
CPU time 43.81 seconds
Started Apr 21 12:50:48 PM PDT 24
Finished Apr 21 12:51:32 PM PDT 24
Peak memory 236320 kb
Host smart-339eed20-ca46-4644-af3a-94bf19c778cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1622401491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.1622401491
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.1560737803
Short name T152
Test name
Test status
Simulation time 16645586267 ps
CPU time 565.05 seconds
Started Apr 21 12:51:01 PM PDT 24
Finished Apr 21 01:00:27 PM PDT 24
Peak memory 267240 kb
Host smart-0b414608-b600-4547-9c51-23af9bb33b57
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560737803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.1560737803
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.3303434161
Short name T276
Test name
Test status
Simulation time 2120565617 ps
CPU time 31.31 seconds
Started Apr 21 04:16:50 PM PDT 24
Finished Apr 21 04:17:21 PM PDT 24
Peak memory 255972 kb
Host smart-700b3652-50c9-459b-b114-44ff403a46ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33034
34161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.3303434161
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.3374114134
Short name T274
Test name
Test status
Simulation time 39093320930 ps
CPU time 1462.98 seconds
Started Apr 21 04:16:53 PM PDT 24
Finished Apr 21 04:41:17 PM PDT 24
Peak memory 290128 kb
Host smart-ada98478-bb1a-4611-8b2f-12bed6cfb564
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374114134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.3374114134
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.1741251912
Short name T600
Test name
Test status
Simulation time 38937134471 ps
CPU time 1142.39 seconds
Started Apr 21 04:16:59 PM PDT 24
Finished Apr 21 04:36:02 PM PDT 24
Peak memory 273524 kb
Host smart-a8532811-3a7c-414f-97f4-94f9794b9f0f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741251912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.1741251912
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.921313471
Short name T264
Test name
Test status
Simulation time 10483427068 ps
CPU time 192.21 seconds
Started Apr 21 04:17:50 PM PDT 24
Finished Apr 21 04:21:02 PM PDT 24
Peak memory 257372 kb
Host smart-7c310bd3-978c-405d-8ab3-4a67cb2b66a8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921313471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_han
dler_stress_all.921313471
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.1305161124
Short name T321
Test name
Test status
Simulation time 8820780365 ps
CPU time 376.99 seconds
Started Apr 21 04:17:57 PM PDT 24
Finished Apr 21 04:24:14 PM PDT 24
Peak memory 248004 kb
Host smart-46a33eb0-1382-4dce-b37f-fd6598e26a2a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305161124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.1305161124
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.1717201418
Short name T610
Test name
Test status
Simulation time 16396952900 ps
CPU time 354.67 seconds
Started Apr 21 04:18:15 PM PDT 24
Finished Apr 21 04:24:10 PM PDT 24
Peak memory 248412 kb
Host smart-89ea3fe7-d87c-47e5-bb1f-9394275c5de5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717201418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.1717201418
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.2507670314
Short name T80
Test name
Test status
Simulation time 1033908384 ps
CPU time 61.45 seconds
Started Apr 21 04:18:33 PM PDT 24
Finished Apr 21 04:19:35 PM PDT 24
Peak memory 247724 kb
Host smart-43d4d649-b68b-46e8-837f-6ad8a1494e97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25076
70314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.2507670314
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.3816314683
Short name T42
Test name
Test status
Simulation time 3215056550 ps
CPU time 60.18 seconds
Started Apr 21 04:18:58 PM PDT 24
Finished Apr 21 04:19:58 PM PDT 24
Peak memory 249232 kb
Host smart-6119eed8-0ba7-4080-b680-61838020fe6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38163
14683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.3816314683
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.1281544706
Short name T20
Test name
Test status
Simulation time 367772253 ps
CPU time 25.8 seconds
Started Apr 21 04:19:37 PM PDT 24
Finished Apr 21 04:20:03 PM PDT 24
Peak memory 256240 kb
Host smart-a74d790b-2559-44ac-847b-3133bf3b7620
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12815
44706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.1281544706
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.1794965139
Short name T282
Test name
Test status
Simulation time 34042582659 ps
CPU time 479.71 seconds
Started Apr 21 04:20:26 PM PDT 24
Finished Apr 21 04:28:26 PM PDT 24
Peak memory 255780 kb
Host smart-f6eaf369-1473-4dcd-a601-b9b9c46fe920
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794965139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.1794965139
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.4125428179
Short name T269
Test name
Test status
Simulation time 51561889335 ps
CPU time 1676.58 seconds
Started Apr 21 04:17:06 PM PDT 24
Finished Apr 21 04:45:03 PM PDT 24
Peak memory 273080 kb
Host smart-0b9e479e-0b89-4d0e-b023-85ad6843513e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125428179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.4125428179
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.3166869665
Short name T275
Test name
Test status
Simulation time 2851128626 ps
CPU time 103.31 seconds
Started Apr 21 04:22:05 PM PDT 24
Finished Apr 21 04:23:49 PM PDT 24
Peak memory 256972 kb
Host smart-8462ed52-fc3f-4456-b075-72a54cae905e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31668
69665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.3166869665
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.3675336392
Short name T137
Test name
Test status
Simulation time 14266918794 ps
CPU time 243.82 seconds
Started Apr 21 12:50:58 PM PDT 24
Finished Apr 21 12:55:03 PM PDT 24
Peak memory 264804 kb
Host smart-23c25f2d-3ed7-45d5-aa50-52ec97f22ec2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3675336392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.3675336392
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.4078391389
Short name T165
Test name
Test status
Simulation time 63297524 ps
CPU time 3.27 seconds
Started Apr 21 12:51:25 PM PDT 24
Finished Apr 21 12:51:29 PM PDT 24
Peak memory 235216 kb
Host smart-f54725f8-2f33-436d-ba7c-d5b47ab8c153
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4078391389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.4078391389
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.3371108036
Short name T161
Test name
Test status
Simulation time 632463597 ps
CPU time 39.76 seconds
Started Apr 21 12:51:18 PM PDT 24
Finished Apr 21 12:51:59 PM PDT 24
Peak memory 247920 kb
Host smart-ad9f9165-ad45-43b3-94c2-99e80fdc89d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3371108036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.3371108036
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.2613108257
Short name T168
Test name
Test status
Simulation time 2388514512 ps
CPU time 83.03 seconds
Started Apr 21 12:50:55 PM PDT 24
Finished Apr 21 12:52:19 PM PDT 24
Peak memory 236404 kb
Host smart-8c9b6a26-c007-45af-8b71-7b4c1e20ac77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2613108257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.2613108257
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.1470133732
Short name T169
Test name
Test status
Simulation time 2624153211 ps
CPU time 41.8 seconds
Started Apr 21 12:50:52 PM PDT 24
Finished Apr 21 12:51:34 PM PDT 24
Peak memory 239144 kb
Host smart-029aa1a9-2cfa-40bd-8ba5-2a97784915de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1470133732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.1470133732
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.1074829109
Short name T159
Test name
Test status
Simulation time 117390155 ps
CPU time 6.48 seconds
Started Apr 21 12:51:06 PM PDT 24
Finished Apr 21 12:51:13 PM PDT 24
Peak memory 236124 kb
Host smart-20eee204-2731-4c2e-a55c-52f3152f0384
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1074829109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.1074829109
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.2825130499
Short name T146
Test name
Test status
Simulation time 16052218326 ps
CPU time 319.38 seconds
Started Apr 21 12:51:11 PM PDT 24
Finished Apr 21 12:56:30 PM PDT 24
Peak memory 264752 kb
Host smart-7d283d6f-a74b-449c-8c5d-7d8e92040fca
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2825130499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.2825130499
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2081839280
Short name T148
Test name
Test status
Simulation time 18334842558 ps
CPU time 303.54 seconds
Started Apr 21 12:51:01 PM PDT 24
Finished Apr 21 12:56:05 PM PDT 24
Peak memory 264800 kb
Host smart-0e45a9f7-8e3b-424b-abc6-cf7d2bd8b622
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2081839280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.2081839280
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.1904752175
Short name T167
Test name
Test status
Simulation time 118366478 ps
CPU time 2.95 seconds
Started Apr 21 12:51:18 PM PDT 24
Finished Apr 21 12:51:21 PM PDT 24
Peak memory 236024 kb
Host smart-a40caaab-9992-47a2-a1a2-a7db4ed87acb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1904752175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.1904752175
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.4082392752
Short name T174
Test name
Test status
Simulation time 54830894 ps
CPU time 4.23 seconds
Started Apr 21 12:50:54 PM PDT 24
Finished Apr 21 12:50:59 PM PDT 24
Peak memory 236112 kb
Host smart-5e076b0e-084d-40e7-a443-8385abeb6dfd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4082392752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.4082392752
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.573285815
Short name T160
Test name
Test status
Simulation time 646132345 ps
CPU time 4.02 seconds
Started Apr 21 12:51:02 PM PDT 24
Finished Apr 21 12:51:06 PM PDT 24
Peak memory 236044 kb
Host smart-2d64db96-b530-4c2f-ba2d-b5dc832045bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=573285815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.573285815
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.1936942312
Short name T154
Test name
Test status
Simulation time 547552113 ps
CPU time 36.81 seconds
Started Apr 21 12:51:02 PM PDT 24
Finished Apr 21 12:51:39 PM PDT 24
Peak memory 239712 kb
Host smart-26b38879-4ea5-42f6-a3e0-19a2552be08a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1936942312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.1936942312
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.115973403
Short name T164
Test name
Test status
Simulation time 470967561 ps
CPU time 37.48 seconds
Started Apr 21 12:51:14 PM PDT 24
Finished Apr 21 12:51:52 PM PDT 24
Peak memory 239740 kb
Host smart-2810dc6c-cd4c-435c-bdd2-0deba9d8c39b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=115973403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.115973403
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.2446635063
Short name T155
Test name
Test status
Simulation time 183576618 ps
CPU time 26.6 seconds
Started Apr 21 12:51:03 PM PDT 24
Finished Apr 21 12:51:30 PM PDT 24
Peak memory 239036 kb
Host smart-fba50f23-950c-462c-a0e3-4e86d5a4f6fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2446635063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.2446635063
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.1351994181
Short name T735
Test name
Test status
Simulation time 36030012267 ps
CPU time 258.75 seconds
Started Apr 21 12:50:49 PM PDT 24
Finished Apr 21 12:55:09 PM PDT 24
Peak memory 239796 kb
Host smart-0b3a0002-9726-488c-bd56-a9994e2fcae6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1351994181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.1351994181
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.3756219867
Short name T822
Test name
Test status
Simulation time 2975494325 ps
CPU time 193.11 seconds
Started Apr 21 12:50:51 PM PDT 24
Finished Apr 21 12:54:04 PM PDT 24
Peak memory 236108 kb
Host smart-533012ad-54a3-4f66-8b7c-cfaebc583cff
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3756219867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.3756219867
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2333537009
Short name T156
Test name
Test status
Simulation time 70762394 ps
CPU time 3.32 seconds
Started Apr 21 12:50:47 PM PDT 24
Finished Apr 21 12:50:51 PM PDT 24
Peak memory 239708 kb
Host smart-e29d93f2-6048-4e15-8c8a-f70cdf417396
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2333537009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.2333537009
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.460322339
Short name T782
Test name
Test status
Simulation time 187071407 ps
CPU time 12.35 seconds
Started Apr 21 12:50:49 PM PDT 24
Finished Apr 21 12:51:02 PM PDT 24
Peak memory 251272 kb
Host smart-1ff09547-44bf-42ab-8473-74f24ed9afa5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460322339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.alert_handler_csr_mem_rw_with_rand_reset.460322339
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.1381232565
Short name T733
Test name
Test status
Simulation time 193768155 ps
CPU time 4.66 seconds
Started Apr 21 12:50:52 PM PDT 24
Finished Apr 21 12:50:56 PM PDT 24
Peak memory 237932 kb
Host smart-c76b4e07-9ce7-4012-a909-956789d0f9e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1381232565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.1381232565
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.557553461
Short name T771
Test name
Test status
Simulation time 17355794 ps
CPU time 1.45 seconds
Started Apr 21 12:50:45 PM PDT 24
Finished Apr 21 12:50:47 PM PDT 24
Peak memory 236116 kb
Host smart-313e9f71-41e4-4607-aea5-f9b398377fc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=557553461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.557553461
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.790524522
Short name T731
Test name
Test status
Simulation time 4984553153 ps
CPU time 53.2 seconds
Started Apr 21 12:50:46 PM PDT 24
Finished Apr 21 12:51:40 PM PDT 24
Peak memory 247996 kb
Host smart-dea79e3e-0396-4a6b-a638-675f32d968ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=790524522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_outs
tanding.790524522
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.107846150
Short name T138
Test name
Test status
Simulation time 100001502978 ps
CPU time 958.06 seconds
Started Apr 21 12:50:50 PM PDT 24
Finished Apr 21 01:06:49 PM PDT 24
Peak memory 272684 kb
Host smart-fcc13937-d7c3-44b2-bc4e-7c8cd26d30a2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107846150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.107846150
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.3030595933
Short name T820
Test name
Test status
Simulation time 204444956 ps
CPU time 12.79 seconds
Started Apr 21 12:50:50 PM PDT 24
Finished Apr 21 12:51:04 PM PDT 24
Peak memory 247952 kb
Host smart-b7bf34e0-1c37-4775-8d0b-31d07ef80bf0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3030595933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.3030595933
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.3404413355
Short name T723
Test name
Test status
Simulation time 4436319686 ps
CPU time 117.08 seconds
Started Apr 21 12:51:01 PM PDT 24
Finished Apr 21 12:52:58 PM PDT 24
Peak memory 236148 kb
Host smart-d77e99a5-9401-4be3-96e1-59900ba88d12
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3404413355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.3404413355
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.3655706967
Short name T746
Test name
Test status
Simulation time 60681766 ps
CPU time 5.32 seconds
Started Apr 21 12:50:51 PM PDT 24
Finished Apr 21 12:50:57 PM PDT 24
Peak memory 239760 kb
Host smart-440969e4-50cb-44be-bcfd-9c580431b66f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3655706967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.3655706967
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.1899159684
Short name T736
Test name
Test status
Simulation time 150012501 ps
CPU time 13.17 seconds
Started Apr 21 12:50:52 PM PDT 24
Finished Apr 21 12:51:06 PM PDT 24
Peak memory 251612 kb
Host smart-204638ce-1ea1-4203-9ddc-562e74bbcf5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899159684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.1899159684
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.1718065115
Short name T784
Test name
Test status
Simulation time 22029185 ps
CPU time 3.14 seconds
Started Apr 21 12:50:53 PM PDT 24
Finished Apr 21 12:50:56 PM PDT 24
Peak memory 235184 kb
Host smart-c982ab6a-e4b8-4b9f-8be1-ccb6e7a5efaa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1718065115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.1718065115
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.191685545
Short name T738
Test name
Test status
Simulation time 7554875 ps
CPU time 1.52 seconds
Started Apr 21 12:50:56 PM PDT 24
Finished Apr 21 12:50:57 PM PDT 24
Peak memory 235220 kb
Host smart-5380cb9f-6ea9-4313-ac99-c991322cf7ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=191685545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.191685545
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1481258884
Short name T814
Test name
Test status
Simulation time 868906471 ps
CPU time 18.57 seconds
Started Apr 21 12:50:57 PM PDT 24
Finished Apr 21 12:51:15 PM PDT 24
Peak memory 247964 kb
Host smart-b20b6013-a9d7-4b5d-b4a6-d9f49f88258e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1481258884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.1481258884
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.3880395573
Short name T827
Test name
Test status
Simulation time 347127766 ps
CPU time 23.18 seconds
Started Apr 21 12:50:45 PM PDT 24
Finished Apr 21 12:51:09 PM PDT 24
Peak memory 247968 kb
Host smart-380c4ec9-9d06-4111-bb16-429f4e5c356f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3880395573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.3880395573
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.2399282828
Short name T767
Test name
Test status
Simulation time 165166757 ps
CPU time 12.48 seconds
Started Apr 21 12:50:59 PM PDT 24
Finished Apr 21 12:51:12 PM PDT 24
Peak memory 249980 kb
Host smart-666db622-86a1-4dd0-b934-4aebbb8eb0fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399282828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.2399282828
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.4198583412
Short name T796
Test name
Test status
Simulation time 158988308 ps
CPU time 4.62 seconds
Started Apr 21 12:50:58 PM PDT 24
Finished Apr 21 12:51:03 PM PDT 24
Peak memory 237980 kb
Host smart-7235e461-d209-46be-948b-d52d717fe218
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4198583412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.4198583412
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.3537974034
Short name T781
Test name
Test status
Simulation time 31299746 ps
CPU time 1.53 seconds
Started Apr 21 12:51:09 PM PDT 24
Finished Apr 21 12:51:11 PM PDT 24
Peak memory 236044 kb
Host smart-d33bc744-935b-4bb9-94db-d9facde8eb07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3537974034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.3537974034
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.3857428582
Short name T725
Test name
Test status
Simulation time 314450438 ps
CPU time 20.76 seconds
Started Apr 21 12:50:57 PM PDT 24
Finished Apr 21 12:51:18 PM PDT 24
Peak memory 243432 kb
Host smart-755f25c9-39f2-4f4d-afb6-09b65b21d047
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3857428582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.3857428582
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.736162414
Short name T144
Test name
Test status
Simulation time 26025534091 ps
CPU time 484.54 seconds
Started Apr 21 12:50:56 PM PDT 24
Finished Apr 21 12:59:06 PM PDT 24
Peak memory 270648 kb
Host smart-0a823f4a-5476-42ca-ba5c-4ee7cec28ad0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736162414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.736162414
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.2334476426
Short name T713
Test name
Test status
Simulation time 688624748 ps
CPU time 15.06 seconds
Started Apr 21 12:51:01 PM PDT 24
Finished Apr 21 12:51:17 PM PDT 24
Peak memory 247988 kb
Host smart-b7965c6a-3990-442b-b811-f7f965972e4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2334476426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.2334476426
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.2120841348
Short name T241
Test name
Test status
Simulation time 36196334 ps
CPU time 2.6 seconds
Started Apr 21 12:51:06 PM PDT 24
Finished Apr 21 12:51:09 PM PDT 24
Peak memory 235252 kb
Host smart-d14be70e-a341-4863-a637-dd0035c8ddbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2120841348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.2120841348
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2373053073
Short name T800
Test name
Test status
Simulation time 532026892 ps
CPU time 11.28 seconds
Started Apr 21 12:51:06 PM PDT 24
Finished Apr 21 12:51:18 PM PDT 24
Peak memory 250028 kb
Host smart-e93961c0-60cc-4f0d-b5e9-4122d0218685
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373053073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.2373053073
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.733340581
Short name T737
Test name
Test status
Simulation time 219402727 ps
CPU time 8.04 seconds
Started Apr 21 12:51:07 PM PDT 24
Finished Apr 21 12:51:15 PM PDT 24
Peak memory 235212 kb
Host smart-4ee6c599-028b-42bc-884d-24001c169872
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=733340581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.733340581
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.2677382035
Short name T831
Test name
Test status
Simulation time 355016541 ps
CPU time 24.95 seconds
Started Apr 21 12:51:04 PM PDT 24
Finished Apr 21 12:51:29 PM PDT 24
Peak memory 247928 kb
Host smart-92c5ced0-3659-4fbb-a9f5-fd39a4e563c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2677382035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.2677382035
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.4124786740
Short name T149
Test name
Test status
Simulation time 9226563697 ps
CPU time 656.58 seconds
Started Apr 21 12:50:55 PM PDT 24
Finished Apr 21 01:01:52 PM PDT 24
Peak memory 272124 kb
Host smart-15430359-c57c-4f21-8443-488a2f4b8b98
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124786740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.4124786740
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.1942643863
Short name T768
Test name
Test status
Simulation time 1022891688 ps
CPU time 17.86 seconds
Started Apr 21 12:50:56 PM PDT 24
Finished Apr 21 12:51:14 PM PDT 24
Peak memory 252664 kb
Host smart-0b3a2daf-bd00-4ce6-a290-dd8557213235
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1942643863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.1942643863
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.1777761494
Short name T712
Test name
Test status
Simulation time 470466452 ps
CPU time 10.69 seconds
Started Apr 21 12:51:03 PM PDT 24
Finished Apr 21 12:51:14 PM PDT 24
Peak memory 250196 kb
Host smart-514fa204-b569-419c-9a24-64246d33cc4c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777761494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.1777761494
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.2181574522
Short name T724
Test name
Test status
Simulation time 251546092 ps
CPU time 5.7 seconds
Started Apr 21 12:51:03 PM PDT 24
Finished Apr 21 12:51:09 PM PDT 24
Peak memory 236128 kb
Host smart-567d382b-ca21-4026-86d5-83294efaa511
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2181574522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.2181574522
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.1855953947
Short name T732
Test name
Test status
Simulation time 8750088 ps
CPU time 1.56 seconds
Started Apr 21 12:51:03 PM PDT 24
Finished Apr 21 12:51:05 PM PDT 24
Peak memory 236092 kb
Host smart-89bb6aa4-1107-4e2e-b13d-76bf9abb8b1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1855953947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.1855953947
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.3789249902
Short name T726
Test name
Test status
Simulation time 273982500 ps
CPU time 12.91 seconds
Started Apr 21 12:51:11 PM PDT 24
Finished Apr 21 12:51:24 PM PDT 24
Peak memory 244292 kb
Host smart-e2c31a0a-96b9-4828-9764-87aebced474e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3789249902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.3789249902
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.1788350633
Short name T124
Test name
Test status
Simulation time 4155445699 ps
CPU time 200.45 seconds
Started Apr 21 12:51:07 PM PDT 24
Finished Apr 21 12:54:28 PM PDT 24
Peak memory 272588 kb
Host smart-9a43ca24-71bb-49ce-8455-122852312448
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1788350633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.1788350633
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.2757782519
Short name T772
Test name
Test status
Simulation time 404701694 ps
CPU time 21.48 seconds
Started Apr 21 12:51:02 PM PDT 24
Finished Apr 21 12:51:24 PM PDT 24
Peak memory 247788 kb
Host smart-8f693271-b0ce-4ed8-8a63-53fac852c1f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2757782519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.2757782519
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.697272326
Short name T778
Test name
Test status
Simulation time 142981133 ps
CPU time 6.8 seconds
Started Apr 21 12:51:06 PM PDT 24
Finished Apr 21 12:51:13 PM PDT 24
Peak memory 238764 kb
Host smart-0977e36b-f79e-4557-870f-82f178b447c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697272326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.alert_handler_csr_mem_rw_with_rand_reset.697272326
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.3135907332
Short name T830
Test name
Test status
Simulation time 1336922415 ps
CPU time 9.82 seconds
Started Apr 21 12:51:10 PM PDT 24
Finished Apr 21 12:51:20 PM PDT 24
Peak memory 239732 kb
Host smart-cb08e562-7110-4393-a116-f7640aa0ea09
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3135907332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.3135907332
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.1407413438
Short name T789
Test name
Test status
Simulation time 13134173 ps
CPU time 1.52 seconds
Started Apr 21 12:51:09 PM PDT 24
Finished Apr 21 12:51:11 PM PDT 24
Peak memory 235264 kb
Host smart-8ee0417a-7e46-4775-bc7c-4c2d9eb5e644
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1407413438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.1407413438
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.3161499498
Short name T756
Test name
Test status
Simulation time 674504770 ps
CPU time 24.07 seconds
Started Apr 21 12:51:15 PM PDT 24
Finished Apr 21 12:51:39 PM PDT 24
Peak memory 239708 kb
Host smart-e5f4d90f-9701-43ab-9b06-47f6b108ed5c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3161499498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.3161499498
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.1288699817
Short name T785
Test name
Test status
Simulation time 106724231 ps
CPU time 8.01 seconds
Started Apr 21 12:51:11 PM PDT 24
Finished Apr 21 12:51:19 PM PDT 24
Peak memory 247824 kb
Host smart-ff133b3e-921f-4f29-a3d9-103d1e1ee16e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1288699817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.1288699817
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.1474276869
Short name T783
Test name
Test status
Simulation time 32620022 ps
CPU time 2.33 seconds
Started Apr 21 12:51:01 PM PDT 24
Finished Apr 21 12:51:04 PM PDT 24
Peak memory 235252 kb
Host smart-a8e05958-9b5a-4941-83a6-26bf542ebe8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1474276869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.1474276869
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.748430152
Short name T806
Test name
Test status
Simulation time 135013042 ps
CPU time 5.96 seconds
Started Apr 21 12:51:12 PM PDT 24
Finished Apr 21 12:51:19 PM PDT 24
Peak memory 239808 kb
Host smart-f1465b6b-baf3-459f-9b76-4d9d25659f61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748430152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.alert_handler_csr_mem_rw_with_rand_reset.748430152
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.46081698
Short name T805
Test name
Test status
Simulation time 94272461 ps
CPU time 8.01 seconds
Started Apr 21 12:51:11 PM PDT 24
Finished Apr 21 12:51:19 PM PDT 24
Peak memory 239652 kb
Host smart-5f37aa4a-e21b-45df-bf67-75bc7e89c39c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=46081698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.46081698
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.3014448723
Short name T227
Test name
Test status
Simulation time 8332430 ps
CPU time 1.5 seconds
Started Apr 21 12:51:18 PM PDT 24
Finished Apr 21 12:51:19 PM PDT 24
Peak memory 236092 kb
Host smart-2346e81c-2a91-4145-802f-ef7263fc9f73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3014448723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.3014448723
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.2042654555
Short name T185
Test name
Test status
Simulation time 668406320 ps
CPU time 22.42 seconds
Started Apr 21 12:51:16 PM PDT 24
Finished Apr 21 12:51:38 PM PDT 24
Peak memory 247960 kb
Host smart-3c1adade-451a-4bae-8465-908b8c2e6ab8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2042654555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.2042654555
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.796709826
Short name T147
Test name
Test status
Simulation time 6776745780 ps
CPU time 429.24 seconds
Started Apr 21 12:51:19 PM PDT 24
Finished Apr 21 12:58:29 PM PDT 24
Peak memory 272376 kb
Host smart-65d3cfeb-2fab-4b9d-a51b-2075585e3ffe
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=796709826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_erro
rs.796709826
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.880217490
Short name T751
Test name
Test status
Simulation time 498116434 ps
CPU time 8.71 seconds
Started Apr 21 12:51:19 PM PDT 24
Finished Apr 21 12:51:28 PM PDT 24
Peak memory 247524 kb
Host smart-3c258ff8-dbf4-4b2f-a0ec-7f8fa9f75d6b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=880217490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.880217490
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.1465558968
Short name T773
Test name
Test status
Simulation time 63697672 ps
CPU time 5.04 seconds
Started Apr 21 12:51:11 PM PDT 24
Finished Apr 21 12:51:17 PM PDT 24
Peak memory 239808 kb
Host smart-e4354353-3888-45a0-b93e-5b1256308339
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465558968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.1465558968
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.3591386581
Short name T193
Test name
Test status
Simulation time 21790952 ps
CPU time 3.73 seconds
Started Apr 21 12:51:12 PM PDT 24
Finished Apr 21 12:51:17 PM PDT 24
Peak memory 236016 kb
Host smart-9f205e4d-a36b-413b-ad41-2925874865e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3591386581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.3591386581
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.413199309
Short name T769
Test name
Test status
Simulation time 52696127 ps
CPU time 1.34 seconds
Started Apr 21 12:51:22 PM PDT 24
Finished Apr 21 12:51:24 PM PDT 24
Peak memory 235288 kb
Host smart-1a5b9930-5b8a-4bb8-8736-8a6fd7a72e16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=413199309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.413199309
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.3181250901
Short name T743
Test name
Test status
Simulation time 1408115723 ps
CPU time 22.07 seconds
Started Apr 21 12:51:12 PM PDT 24
Finished Apr 21 12:51:34 PM PDT 24
Peak memory 243444 kb
Host smart-a4c1d089-1457-4525-98e0-4943d920c0e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3181250901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.3181250901
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.817902269
Short name T195
Test name
Test status
Simulation time 867925254 ps
CPU time 102.5 seconds
Started Apr 21 12:51:09 PM PDT 24
Finished Apr 21 12:52:52 PM PDT 24
Peak memory 256508 kb
Host smart-a27483e5-7c09-4741-8531-ea57cda0d570
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=817902269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_erro
rs.817902269
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.2259445962
Short name T135
Test name
Test status
Simulation time 58956393698 ps
CPU time 1084.28 seconds
Started Apr 21 12:51:12 PM PDT 24
Finished Apr 21 01:09:17 PM PDT 24
Peak memory 264964 kb
Host smart-4975f500-d862-4f1e-8fb2-733dcab46f15
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259445962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.2259445962
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.1540015447
Short name T711
Test name
Test status
Simulation time 151119895 ps
CPU time 12.49 seconds
Started Apr 21 12:51:22 PM PDT 24
Finished Apr 21 12:51:35 PM PDT 24
Peak memory 251868 kb
Host smart-8583501b-904b-4984-bb27-7e038f201023
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1540015447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.1540015447
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.4027339793
Short name T166
Test name
Test status
Simulation time 3683468908 ps
CPU time 71 seconds
Started Apr 21 12:51:11 PM PDT 24
Finished Apr 21 12:52:22 PM PDT 24
Peak memory 239852 kb
Host smart-ef881ab0-3663-408f-867f-214f14e1652f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4027339793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.4027339793
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.3173294354
Short name T197
Test name
Test status
Simulation time 34905773 ps
CPU time 5.03 seconds
Started Apr 21 12:51:07 PM PDT 24
Finished Apr 21 12:51:12 PM PDT 24
Peak memory 256204 kb
Host smart-64c8f3c5-8825-4a58-9d22-36632904a8eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173294354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.3173294354
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.3089024696
Short name T171
Test name
Test status
Simulation time 240682555 ps
CPU time 5.42 seconds
Started Apr 21 12:51:12 PM PDT 24
Finished Apr 21 12:51:17 PM PDT 24
Peak memory 235188 kb
Host smart-cc358422-4cff-4133-a178-a58bb5249b36
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3089024696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.3089024696
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.197141226
Short name T190
Test name
Test status
Simulation time 135550385 ps
CPU time 12.46 seconds
Started Apr 21 12:51:17 PM PDT 24
Finished Apr 21 12:51:29 PM PDT 24
Peak memory 243356 kb
Host smart-0978141b-6ba4-4a1a-b6ad-33b9ed52b428
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=197141226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_out
standing.197141226
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.4246283069
Short name T145
Test name
Test status
Simulation time 9143329646 ps
CPU time 547.85 seconds
Started Apr 21 12:51:09 PM PDT 24
Finished Apr 21 01:00:17 PM PDT 24
Peak memory 264780 kb
Host smart-29f01058-549b-45ce-8298-0cbc6f727e24
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246283069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.4246283069
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.575879732
Short name T757
Test name
Test status
Simulation time 204318603 ps
CPU time 7.24 seconds
Started Apr 21 12:51:11 PM PDT 24
Finished Apr 21 12:51:19 PM PDT 24
Peak memory 247816 kb
Host smart-e1299e5c-6a06-4953-b409-bf728b2981a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=575879732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.575879732
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.4144588430
Short name T717
Test name
Test status
Simulation time 211349930 ps
CPU time 8.33 seconds
Started Apr 21 12:51:18 PM PDT 24
Finished Apr 21 12:51:27 PM PDT 24
Peak memory 251148 kb
Host smart-81f67db3-2c3b-4222-afdc-d182205a38d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144588430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.4144588430
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.3596806832
Short name T354
Test name
Test status
Simulation time 261669702 ps
CPU time 4.58 seconds
Started Apr 21 12:51:18 PM PDT 24
Finished Apr 21 12:51:23 PM PDT 24
Peak memory 235180 kb
Host smart-b9032f8a-803c-4c95-9fe9-8169fe5e4464
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3596806832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.3596806832
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.2528933055
Short name T755
Test name
Test status
Simulation time 12184949 ps
CPU time 1.64 seconds
Started Apr 21 12:51:14 PM PDT 24
Finished Apr 21 12:51:16 PM PDT 24
Peak memory 236076 kb
Host smart-103a265e-8582-41d3-b443-40441313c85f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2528933055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.2528933055
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.599260547
Short name T191
Test name
Test status
Simulation time 166342295 ps
CPU time 20.6 seconds
Started Apr 21 12:51:19 PM PDT 24
Finished Apr 21 12:51:40 PM PDT 24
Peak memory 247952 kb
Host smart-6f246188-7cda-476a-9a42-75757d330fbb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=599260547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_out
standing.599260547
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.193617359
Short name T151
Test name
Test status
Simulation time 3625534824 ps
CPU time 347.76 seconds
Started Apr 21 12:51:19 PM PDT 24
Finished Apr 21 12:57:07 PM PDT 24
Peak memory 264884 kb
Host smart-5cc0ff70-dfd3-45c6-9cce-61d7a702f02c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193617359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.193617359
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.1424504303
Short name T716
Test name
Test status
Simulation time 1318066533 ps
CPU time 10.42 seconds
Started Apr 21 12:51:14 PM PDT 24
Finished Apr 21 12:51:25 PM PDT 24
Peak memory 247992 kb
Host smart-16d1b112-9a78-4a67-8359-cbd510d30751
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1424504303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.1424504303
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.4032220224
Short name T775
Test name
Test status
Simulation time 1203240725 ps
CPU time 10.88 seconds
Started Apr 21 12:51:15 PM PDT 24
Finished Apr 21 12:51:26 PM PDT 24
Peak memory 238572 kb
Host smart-3d4e2d85-076b-4122-800c-889b3f287b6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032220224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.4032220224
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.2374292756
Short name T812
Test name
Test status
Simulation time 111785693 ps
CPU time 5.45 seconds
Started Apr 21 12:51:12 PM PDT 24
Finished Apr 21 12:51:17 PM PDT 24
Peak memory 235188 kb
Host smart-4229d674-d640-4c88-9acd-0394bc296a07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2374292756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.2374292756
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.923472284
Short name T802
Test name
Test status
Simulation time 14918365 ps
CPU time 1.42 seconds
Started Apr 21 12:51:17 PM PDT 24
Finished Apr 21 12:51:19 PM PDT 24
Peak memory 234200 kb
Host smart-d1d4a1bc-a651-4a44-a1b1-5b8698c42143
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=923472284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.923472284
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.3947072066
Short name T749
Test name
Test status
Simulation time 2095412882 ps
CPU time 36.89 seconds
Started Apr 21 12:51:14 PM PDT 24
Finished Apr 21 12:51:51 PM PDT 24
Peak memory 243388 kb
Host smart-7344fd0b-f25a-465c-aa94-ce602e2f1100
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3947072066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.3947072066
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.2966407369
Short name T120
Test name
Test status
Simulation time 2951796785 ps
CPU time 191.55 seconds
Started Apr 21 12:51:14 PM PDT 24
Finished Apr 21 12:54:26 PM PDT 24
Peak memory 263756 kb
Host smart-825a306b-4272-4d86-9ad9-5fc9c42b8f8b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2966407369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.2966407369
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.182542249
Short name T143
Test name
Test status
Simulation time 4723667108 ps
CPU time 608.37 seconds
Started Apr 21 12:51:14 PM PDT 24
Finished Apr 21 01:01:22 PM PDT 24
Peak memory 264776 kb
Host smart-30d7cf6d-1d80-42b7-840f-396c3e7e4c1e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182542249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.182542249
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.3416946882
Short name T819
Test name
Test status
Simulation time 300640687 ps
CPU time 15.32 seconds
Started Apr 21 12:51:21 PM PDT 24
Finished Apr 21 12:51:37 PM PDT 24
Peak memory 253328 kb
Host smart-f0b9e13d-5cdd-4a50-8e54-ce37d0c8c4b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3416946882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.3416946882
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.710967933
Short name T764
Test name
Test status
Simulation time 152816725 ps
CPU time 5.25 seconds
Started Apr 21 12:51:19 PM PDT 24
Finished Apr 21 12:51:25 PM PDT 24
Peak memory 256100 kb
Host smart-0c53e999-fb45-4525-bb72-e1b4ad4b0a68
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710967933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.alert_handler_csr_mem_rw_with_rand_reset.710967933
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.2995056789
Short name T170
Test name
Test status
Simulation time 127156974 ps
CPU time 5.41 seconds
Started Apr 21 12:51:17 PM PDT 24
Finished Apr 21 12:51:23 PM PDT 24
Peak memory 235180 kb
Host smart-e37b8915-fd39-49e8-bcf4-0f48912ff187
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2995056789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.2995056789
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.1650318868
Short name T759
Test name
Test status
Simulation time 22737268 ps
CPU time 1.49 seconds
Started Apr 21 12:51:10 PM PDT 24
Finished Apr 21 12:51:11 PM PDT 24
Peak memory 236128 kb
Host smart-b8b203f5-c93d-49cf-a6d1-e0f7632fe662
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1650318868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.1650318868
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.2372551899
Short name T192
Test name
Test status
Simulation time 2807214232 ps
CPU time 42.9 seconds
Started Apr 21 12:51:18 PM PDT 24
Finished Apr 21 12:52:02 PM PDT 24
Peak memory 247972 kb
Host smart-14793140-6fe8-4fab-a29f-0bee686aae81
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2372551899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.2372551899
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3686262
Short name T128
Test name
Test status
Simulation time 1705709363 ps
CPU time 220.4 seconds
Started Apr 21 12:51:17 PM PDT 24
Finished Apr 21 12:54:58 PM PDT 24
Peak memory 264672 kb
Host smart-96b800b7-7ab1-4f0a-af41-4d257dbd5e21
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3686262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_errors.3686262
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.228730026
Short name T130
Test name
Test status
Simulation time 14606824551 ps
CPU time 481.53 seconds
Started Apr 21 12:51:13 PM PDT 24
Finished Apr 21 12:59:16 PM PDT 24
Peak memory 269424 kb
Host smart-5e4aa88b-2ca1-4f06-8909-f5b1ef6bb266
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228730026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.228730026
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.3829905526
Short name T714
Test name
Test status
Simulation time 138872638 ps
CPU time 10.08 seconds
Started Apr 21 12:51:21 PM PDT 24
Finished Apr 21 12:51:31 PM PDT 24
Peak memory 248036 kb
Host smart-45e5544c-d656-4263-86df-4bb8617b1a89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3829905526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.3829905526
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.3366741645
Short name T821
Test name
Test status
Simulation time 571852463 ps
CPU time 67.91 seconds
Started Apr 21 12:50:59 PM PDT 24
Finished Apr 21 12:52:08 PM PDT 24
Peak memory 236052 kb
Host smart-4dc558d8-a755-47a0-bfc4-b220cf62aa1b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3366741645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.3366741645
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.3849154631
Short name T766
Test name
Test status
Simulation time 18983070401 ps
CPU time 196.8 seconds
Started Apr 21 12:50:54 PM PDT 24
Finished Apr 21 12:54:12 PM PDT 24
Peak memory 236056 kb
Host smart-949a11eb-cd14-4f7b-8b78-506f9fc891a7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3849154631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.3849154631
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.4280307545
Short name T753
Test name
Test status
Simulation time 512057203 ps
CPU time 6.43 seconds
Started Apr 21 12:50:59 PM PDT 24
Finished Apr 21 12:51:06 PM PDT 24
Peak memory 239736 kb
Host smart-d843fc7c-face-4097-8974-9b363e574abb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4280307545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.4280307545
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.3682067992
Short name T196
Test name
Test status
Simulation time 382119610 ps
CPU time 8.43 seconds
Started Apr 21 12:50:51 PM PDT 24
Finished Apr 21 12:51:00 PM PDT 24
Peak memory 254816 kb
Host smart-902c524f-1135-4c2c-be89-aa601afa58ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682067992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.3682067992
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.902430765
Short name T809
Test name
Test status
Simulation time 53312462 ps
CPU time 5.24 seconds
Started Apr 21 12:51:05 PM PDT 24
Finished Apr 21 12:51:11 PM PDT 24
Peak memory 238040 kb
Host smart-c94bd995-f76a-49dc-ba61-6b05580d9f2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=902430765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.902430765
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.2540656794
Short name T828
Test name
Test status
Simulation time 17206249 ps
CPU time 1.37 seconds
Started Apr 21 12:50:48 PM PDT 24
Finished Apr 21 12:50:50 PM PDT 24
Peak memory 235220 kb
Host smart-c270dd77-1a50-4c9a-8b0c-7cea999cf6aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2540656794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.2540656794
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.2445144890
Short name T188
Test name
Test status
Simulation time 2574019623 ps
CPU time 47.77 seconds
Started Apr 21 12:50:59 PM PDT 24
Finished Apr 21 12:51:47 PM PDT 24
Peak memory 244348 kb
Host smart-2edcaae4-faa8-468e-9d26-cb37d3f126b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2445144890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.2445144890
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.2541442141
Short name T125
Test name
Test status
Simulation time 9386359103 ps
CPU time 290.15 seconds
Started Apr 21 12:50:54 PM PDT 24
Finished Apr 21 12:55:44 PM PDT 24
Peak memory 271948 kb
Host smart-da4546b3-2020-4381-810d-aa0ffa5607a8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2541442141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.2541442141
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.4187177133
Short name T801
Test name
Test status
Simulation time 6458685617 ps
CPU time 492.84 seconds
Started Apr 21 12:50:53 PM PDT 24
Finished Apr 21 12:59:06 PM PDT 24
Peak memory 264824 kb
Host smart-d4f9f321-eb3c-408a-90dd-254e42756a7c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187177133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.4187177133
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.451792603
Short name T776
Test name
Test status
Simulation time 536336973 ps
CPU time 15.04 seconds
Started Apr 21 12:51:01 PM PDT 24
Finished Apr 21 12:51:16 PM PDT 24
Peak memory 247832 kb
Host smart-2cb413f8-9610-449f-bd50-966bdfc0652e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=451792603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.451792603
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.2382836677
Short name T779
Test name
Test status
Simulation time 20295030 ps
CPU time 1.86 seconds
Started Apr 21 12:51:18 PM PDT 24
Finished Apr 21 12:51:21 PM PDT 24
Peak memory 235216 kb
Host smart-32b8c0c2-6c45-4149-851f-cb2bac9ca836
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2382836677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.2382836677
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.3347197917
Short name T826
Test name
Test status
Simulation time 18643431 ps
CPU time 1.3 seconds
Started Apr 21 12:51:12 PM PDT 24
Finished Apr 21 12:51:13 PM PDT 24
Peak memory 236152 kb
Host smart-6935090b-f0ba-45f8-9037-730456d18a9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3347197917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.3347197917
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1550875994
Short name T813
Test name
Test status
Simulation time 11206479 ps
CPU time 1.3 seconds
Started Apr 21 12:51:17 PM PDT 24
Finished Apr 21 12:51:19 PM PDT 24
Peak memory 235116 kb
Host smart-3bc4eed4-8b30-461e-9f59-377e8c5a2f86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1550875994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.1550875994
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.1865089824
Short name T727
Test name
Test status
Simulation time 10677165 ps
CPU time 1.32 seconds
Started Apr 21 12:51:13 PM PDT 24
Finished Apr 21 12:51:15 PM PDT 24
Peak memory 236120 kb
Host smart-d8923489-a584-4bae-adbe-773c7cd39e2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1865089824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.1865089824
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.1221759685
Short name T752
Test name
Test status
Simulation time 8658417 ps
CPU time 1.56 seconds
Started Apr 21 12:51:16 PM PDT 24
Finished Apr 21 12:51:18 PM PDT 24
Peak memory 235180 kb
Host smart-5035cc72-c16f-41ad-8af7-e441000141a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1221759685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.1221759685
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.3824109388
Short name T347
Test name
Test status
Simulation time 31097529 ps
CPU time 1.4 seconds
Started Apr 21 12:51:16 PM PDT 24
Finished Apr 21 12:51:17 PM PDT 24
Peak memory 235192 kb
Host smart-8a91f99a-f81f-4f61-9e4e-c5729b033e4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3824109388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.3824109388
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.3986878046
Short name T730
Test name
Test status
Simulation time 6307954 ps
CPU time 1.43 seconds
Started Apr 21 12:51:20 PM PDT 24
Finished Apr 21 12:51:21 PM PDT 24
Peak memory 234228 kb
Host smart-40f06d9c-4027-4056-a4db-09066b8ce79e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3986878046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.3986878046
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.2498519688
Short name T770
Test name
Test status
Simulation time 9234307 ps
CPU time 1.39 seconds
Started Apr 21 12:51:17 PM PDT 24
Finished Apr 21 12:51:18 PM PDT 24
Peak memory 236140 kb
Host smart-a14a33bb-dadf-409b-8272-4308a36b2623
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2498519688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.2498519688
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.375313168
Short name T745
Test name
Test status
Simulation time 6430173 ps
CPU time 1.43 seconds
Started Apr 21 12:51:15 PM PDT 24
Finished Apr 21 12:51:16 PM PDT 24
Peak memory 236080 kb
Host smart-8ea5b67d-a96a-416a-9e6f-91569a785259
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=375313168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.375313168
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.2975196937
Short name T818
Test name
Test status
Simulation time 4830005695 ps
CPU time 169.89 seconds
Started Apr 21 12:50:54 PM PDT 24
Finished Apr 21 12:53:45 PM PDT 24
Peak memory 239844 kb
Host smart-9cd4715f-f45b-4def-b31b-86e7771ebf12
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2975196937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.2975196937
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.482025491
Short name T728
Test name
Test status
Simulation time 2887134930 ps
CPU time 196.36 seconds
Started Apr 21 12:51:07 PM PDT 24
Finished Apr 21 12:54:23 PM PDT 24
Peak memory 236080 kb
Host smart-74a425b2-71af-48ae-80cf-2aa195d52565
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=482025491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.482025491
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.2933180000
Short name T158
Test name
Test status
Simulation time 72783454 ps
CPU time 3.55 seconds
Started Apr 21 12:50:52 PM PDT 24
Finished Apr 21 12:50:56 PM PDT 24
Peak memory 239724 kb
Host smart-99077b43-7c7f-4202-8aec-59ea84d657f5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2933180000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.2933180000
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.3911262067
Short name T198
Test name
Test status
Simulation time 33944068 ps
CPU time 5.58 seconds
Started Apr 21 12:50:55 PM PDT 24
Finished Apr 21 12:51:01 PM PDT 24
Peak memory 250052 kb
Host smart-9922a934-ab75-4d42-89fd-0a5cc6c703b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911262067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.3911262067
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.2914241081
Short name T189
Test name
Test status
Simulation time 96952776 ps
CPU time 7.46 seconds
Started Apr 21 12:50:51 PM PDT 24
Finished Apr 21 12:50:59 PM PDT 24
Peak memory 236104 kb
Host smart-0aadbe87-e01c-4e0e-802e-f2a39edd17d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2914241081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.2914241081
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.1618937040
Short name T824
Test name
Test status
Simulation time 24192927 ps
CPU time 1.38 seconds
Started Apr 21 12:50:53 PM PDT 24
Finished Apr 21 12:50:55 PM PDT 24
Peak memory 236108 kb
Host smart-196afb0e-d477-4a7a-9a4c-5767dfcc943a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1618937040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.1618937040
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.2158957834
Short name T187
Test name
Test status
Simulation time 1843185497 ps
CPU time 21.3 seconds
Started Apr 21 12:50:52 PM PDT 24
Finished Apr 21 12:51:13 PM PDT 24
Peak memory 244232 kb
Host smart-0a9cd578-1652-48a9-9954-8f4d13e15b27
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2158957834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.2158957834
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.192175757
Short name T808
Test name
Test status
Simulation time 1095273311 ps
CPU time 111.02 seconds
Started Apr 21 12:50:52 PM PDT 24
Finished Apr 21 12:52:44 PM PDT 24
Peak memory 264684 kb
Host smart-d29acd87-b02a-454f-8f84-2cc4fe14c6df
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=192175757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_error
s.192175757
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.4227419950
Short name T792
Test name
Test status
Simulation time 79676313 ps
CPU time 10.83 seconds
Started Apr 21 12:50:52 PM PDT 24
Finished Apr 21 12:51:03 PM PDT 24
Peak memory 247492 kb
Host smart-c9fb55a9-4870-41a1-89cb-e7bae104c80b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4227419950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.4227419950
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.3581267246
Short name T240
Test name
Test status
Simulation time 301856664 ps
CPU time 22.47 seconds
Started Apr 21 12:51:01 PM PDT 24
Finished Apr 21 12:51:24 PM PDT 24
Peak memory 236320 kb
Host smart-69d67903-15a5-4031-b1b1-4e3d6eaf7cc7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3581267246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.3581267246
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.344142929
Short name T349
Test name
Test status
Simulation time 15348938 ps
CPU time 1.34 seconds
Started Apr 21 12:51:26 PM PDT 24
Finished Apr 21 12:51:28 PM PDT 24
Peak memory 235284 kb
Host smart-0bf980aa-1d84-461a-b72d-513f10031928
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=344142929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.344142929
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.1444419287
Short name T786
Test name
Test status
Simulation time 11581956 ps
CPU time 1.33 seconds
Started Apr 21 12:51:27 PM PDT 24
Finished Apr 21 12:51:29 PM PDT 24
Peak memory 236100 kb
Host smart-f8ceed3b-50cc-4dc9-876e-e43a87b8f42a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1444419287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.1444419287
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.4198717018
Short name T788
Test name
Test status
Simulation time 10798423 ps
CPU time 1.33 seconds
Started Apr 21 12:51:19 PM PDT 24
Finished Apr 21 12:51:21 PM PDT 24
Peak memory 235204 kb
Host smart-49dea482-d380-42bf-b08e-a8d0f02aa485
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4198717018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.4198717018
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.1533497715
Short name T729
Test name
Test status
Simulation time 7341334 ps
CPU time 1.45 seconds
Started Apr 21 12:51:23 PM PDT 24
Finished Apr 21 12:51:25 PM PDT 24
Peak memory 236104 kb
Host smart-29029dfa-e2fd-44b2-9b8b-d46fb1ee8c94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1533497715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.1533497715
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.1284665884
Short name T228
Test name
Test status
Simulation time 13594795 ps
CPU time 1.38 seconds
Started Apr 21 12:51:20 PM PDT 24
Finished Apr 21 12:51:22 PM PDT 24
Peak memory 236108 kb
Host smart-c96b34c3-ad6d-40fb-a177-c93d99ed69c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1284665884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.1284665884
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.705694340
Short name T780
Test name
Test status
Simulation time 12268719 ps
CPU time 1.72 seconds
Started Apr 21 12:51:23 PM PDT 24
Finished Apr 21 12:51:25 PM PDT 24
Peak memory 236044 kb
Host smart-992fc261-73a3-45da-9d2b-e51357b7c055
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=705694340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.705694340
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.2016969813
Short name T787
Test name
Test status
Simulation time 12363105 ps
CPU time 1.67 seconds
Started Apr 21 12:51:20 PM PDT 24
Finished Apr 21 12:51:22 PM PDT 24
Peak memory 234232 kb
Host smart-5833c353-52c5-49f7-8fc0-46d5024c4c9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2016969813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.2016969813
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.3682345808
Short name T799
Test name
Test status
Simulation time 50188499 ps
CPU time 1.3 seconds
Started Apr 21 12:51:31 PM PDT 24
Finished Apr 21 12:51:33 PM PDT 24
Peak memory 234132 kb
Host smart-4b973032-ca84-4d75-8762-e248f8566a04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3682345808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.3682345808
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.1453536253
Short name T739
Test name
Test status
Simulation time 10443224 ps
CPU time 1.72 seconds
Started Apr 21 12:51:21 PM PDT 24
Finished Apr 21 12:51:23 PM PDT 24
Peak memory 236112 kb
Host smart-37c6c3e3-0296-470f-b25e-3fc9372c236d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1453536253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.1453536253
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.855236197
Short name T346
Test name
Test status
Simulation time 6495788 ps
CPU time 1.41 seconds
Started Apr 21 12:51:26 PM PDT 24
Finished Apr 21 12:51:28 PM PDT 24
Peak memory 236152 kb
Host smart-06dca2c1-4c60-439e-8df5-50ce137709ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=855236197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.855236197
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.4208982266
Short name T804
Test name
Test status
Simulation time 4397451194 ps
CPU time 155.09 seconds
Started Apr 21 12:50:57 PM PDT 24
Finished Apr 21 12:53:33 PM PDT 24
Peak memory 239840 kb
Host smart-2d0b47d9-1560-4592-93c0-1d19a779c142
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4208982266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.4208982266
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.3953711761
Short name T719
Test name
Test status
Simulation time 3814935522 ps
CPU time 210.22 seconds
Started Apr 21 12:50:53 PM PDT 24
Finished Apr 21 12:54:23 PM PDT 24
Peak memory 235248 kb
Host smart-79931732-ffe8-4e31-863a-70a8d4499292
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3953711761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.3953711761
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2714672363
Short name T765
Test name
Test status
Simulation time 145696274 ps
CPU time 5.66 seconds
Started Apr 21 12:50:51 PM PDT 24
Finished Apr 21 12:50:57 PM PDT 24
Peak memory 239772 kb
Host smart-b889c207-1723-461b-97e4-2f387ed9dfb9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2714672363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.2714672363
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.3117181092
Short name T172
Test name
Test status
Simulation time 624916067 ps
CPU time 8.82 seconds
Started Apr 21 12:50:57 PM PDT 24
Finished Apr 21 12:51:06 PM PDT 24
Peak memory 239096 kb
Host smart-221c6744-eabd-4973-9def-3da9bf078035
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117181092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.3117181092
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.3250624797
Short name T720
Test name
Test status
Simulation time 34988931 ps
CPU time 3.34 seconds
Started Apr 21 12:50:56 PM PDT 24
Finished Apr 21 12:51:00 PM PDT 24
Peak memory 235204 kb
Host smart-26d47edb-65a2-48aa-bd27-2761e3c7e146
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3250624797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.3250624797
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.531953698
Short name T791
Test name
Test status
Simulation time 6306542 ps
CPU time 1.42 seconds
Started Apr 21 12:51:05 PM PDT 24
Finished Apr 21 12:51:06 PM PDT 24
Peak memory 234252 kb
Host smart-26ce62ac-ece0-453c-99f3-8d522e4f5d50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=531953698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.531953698
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.1071885939
Short name T740
Test name
Test status
Simulation time 613555426 ps
CPU time 23.29 seconds
Started Apr 21 12:51:00 PM PDT 24
Finished Apr 21 12:51:24 PM PDT 24
Peak memory 244208 kb
Host smart-2fdc6cdb-4a38-4ba3-b101-5d49de36876b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1071885939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.1071885939
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.207017285
Short name T817
Test name
Test status
Simulation time 4163061110 ps
CPU time 311.86 seconds
Started Apr 21 12:50:55 PM PDT 24
Finished Apr 21 12:56:07 PM PDT 24
Peak memory 265808 kb
Host smart-1b43a922-2d91-42db-872b-f2050cf1e416
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=207017285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_error
s.207017285
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.2208676219
Short name T140
Test name
Test status
Simulation time 30631604869 ps
CPU time 526.05 seconds
Started Apr 21 12:50:55 PM PDT 24
Finished Apr 21 12:59:41 PM PDT 24
Peak memory 268788 kb
Host smart-f2fe9cb1-d280-48c4-ab4c-710421e5cc69
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208676219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.2208676219
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.1560753691
Short name T750
Test name
Test status
Simulation time 286814126 ps
CPU time 17.82 seconds
Started Apr 21 12:50:46 PM PDT 24
Finished Apr 21 12:51:04 PM PDT 24
Peak memory 252172 kb
Host smart-95fa87fa-a172-4c0c-8f6c-8768ebc8b1f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1560753691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.1560753691
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.65994639
Short name T763
Test name
Test status
Simulation time 6729989 ps
CPU time 1.44 seconds
Started Apr 21 12:51:26 PM PDT 24
Finished Apr 21 12:51:28 PM PDT 24
Peak memory 236028 kb
Host smart-cb8b5748-6022-408a-86b6-b8b1b5fcc754
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=65994639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.65994639
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.401400368
Short name T352
Test name
Test status
Simulation time 8506345 ps
CPU time 1.53 seconds
Started Apr 21 12:51:20 PM PDT 24
Finished Apr 21 12:51:21 PM PDT 24
Peak memory 234196 kb
Host smart-296aeb42-7420-448a-b818-e17d9fa1bff5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=401400368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.401400368
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.49577412
Short name T793
Test name
Test status
Simulation time 10190715 ps
CPU time 1.48 seconds
Started Apr 21 12:51:26 PM PDT 24
Finished Apr 21 12:51:28 PM PDT 24
Peak memory 236028 kb
Host smart-193bc95d-c923-49eb-a55c-96c6fad41f11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=49577412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.49577412
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.309797875
Short name T761
Test name
Test status
Simulation time 15974398 ps
CPU time 1.39 seconds
Started Apr 21 12:51:29 PM PDT 24
Finished Apr 21 12:51:31 PM PDT 24
Peak memory 235236 kb
Host smart-db9ce864-9ff0-46cb-8b01-53d17ec0d323
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=309797875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.309797875
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.4191973159
Short name T747
Test name
Test status
Simulation time 9984668 ps
CPU time 1.63 seconds
Started Apr 21 12:51:27 PM PDT 24
Finished Apr 21 12:51:30 PM PDT 24
Peak memory 235236 kb
Host smart-a367e103-f2e3-479a-a143-8d5c52b84acd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4191973159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.4191973159
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.3888878094
Short name T758
Test name
Test status
Simulation time 12968511 ps
CPU time 1.24 seconds
Started Apr 21 12:51:27 PM PDT 24
Finished Apr 21 12:51:29 PM PDT 24
Peak memory 236092 kb
Host smart-df150bab-3079-48e1-a9eb-fbce82a7a9ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3888878094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.3888878094
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.2406480401
Short name T777
Test name
Test status
Simulation time 9723830 ps
CPU time 1.61 seconds
Started Apr 21 12:51:25 PM PDT 24
Finished Apr 21 12:51:27 PM PDT 24
Peak memory 236108 kb
Host smart-9c316789-5ac7-4b38-85f0-5a9897791487
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2406480401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.2406480401
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.2781000927
Short name T816
Test name
Test status
Simulation time 9365417 ps
CPU time 1.24 seconds
Started Apr 21 12:51:24 PM PDT 24
Finished Apr 21 12:51:26 PM PDT 24
Peak memory 236116 kb
Host smart-e5e322d6-b199-4dcd-8118-fcb4ec00b026
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2781000927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.2781000927
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.4097366196
Short name T815
Test name
Test status
Simulation time 15182966 ps
CPU time 1.32 seconds
Started Apr 21 12:51:28 PM PDT 24
Finished Apr 21 12:51:30 PM PDT 24
Peak memory 236132 kb
Host smart-a27e8229-0156-45a0-a915-94525d55bec3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4097366196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.4097366196
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.2458171706
Short name T351
Test name
Test status
Simulation time 11332772 ps
CPU time 1.3 seconds
Started Apr 21 12:51:24 PM PDT 24
Finished Apr 21 12:51:25 PM PDT 24
Peak memory 236100 kb
Host smart-5c841382-8b01-48e1-a9b6-8edaa4972e6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2458171706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.2458171706
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.372063934
Short name T718
Test name
Test status
Simulation time 50543644 ps
CPU time 5.44 seconds
Started Apr 21 12:50:54 PM PDT 24
Finished Apr 21 12:50:59 PM PDT 24
Peak memory 239760 kb
Host smart-1d64df2f-2628-46ae-8f95-f6d907a80769
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372063934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.alert_handler_csr_mem_rw_with_rand_reset.372063934
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.2442600537
Short name T721
Test name
Test status
Simulation time 42919474 ps
CPU time 6.41 seconds
Started Apr 21 12:50:59 PM PDT 24
Finished Apr 21 12:51:06 PM PDT 24
Peak memory 236076 kb
Host smart-e07f8abc-bf6e-47af-80a8-0bab44e683fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2442600537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.2442600537
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.2074289976
Short name T744
Test name
Test status
Simulation time 9161868 ps
CPU time 1.39 seconds
Started Apr 21 12:50:53 PM PDT 24
Finished Apr 21 12:50:54 PM PDT 24
Peak memory 236132 kb
Host smart-282786b1-54d5-4b9f-bffb-fa9bd0117bfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2074289976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.2074289976
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.3238524800
Short name T774
Test name
Test status
Simulation time 8042679194 ps
CPU time 34.39 seconds
Started Apr 21 12:50:54 PM PDT 24
Finished Apr 21 12:51:29 PM PDT 24
Peak memory 248004 kb
Host smart-4ad89d83-9803-4bde-a8bc-09bb899a9248
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3238524800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.3238524800
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.3939654303
Short name T139
Test name
Test status
Simulation time 5318028638 ps
CPU time 358.92 seconds
Started Apr 21 12:51:09 PM PDT 24
Finished Apr 21 12:57:08 PM PDT 24
Peak memory 264924 kb
Host smart-3dfda7cc-1cff-46dc-938c-89112374d7ae
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3939654303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.3939654303
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.30053783
Short name T142
Test name
Test status
Simulation time 12843102120 ps
CPU time 982.33 seconds
Started Apr 21 12:50:53 PM PDT 24
Finished Apr 21 01:07:16 PM PDT 24
Peak memory 272156 kb
Host smart-b99f9264-cb66-4825-b8b5-4e423795a5b2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30053783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.30053783
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.291361471
Short name T795
Test name
Test status
Simulation time 408602568 ps
CPU time 28.81 seconds
Started Apr 21 12:50:55 PM PDT 24
Finished Apr 21 12:51:25 PM PDT 24
Peak memory 247772 kb
Host smart-250129f5-0fdd-43c5-9cf8-797ab741a0d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=291361471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.291361471
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.1979778492
Short name T810
Test name
Test status
Simulation time 1206859589 ps
CPU time 40.49 seconds
Started Apr 21 12:50:55 PM PDT 24
Finished Apr 21 12:51:35 PM PDT 24
Peak memory 239728 kb
Host smart-97ec4dbb-c07b-4739-8b70-e866711122ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1979778492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.1979778492
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.3113370657
Short name T353
Test name
Test status
Simulation time 623489813 ps
CPU time 12.46 seconds
Started Apr 21 12:50:56 PM PDT 24
Finished Apr 21 12:51:09 PM PDT 24
Peak memory 251688 kb
Host smart-2da8a5b5-41aa-4f61-bf29-65623f9d54de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113370657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.3113370657
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.377024571
Short name T748
Test name
Test status
Simulation time 50764616 ps
CPU time 4.41 seconds
Started Apr 21 12:51:04 PM PDT 24
Finished Apr 21 12:51:09 PM PDT 24
Peak memory 235236 kb
Host smart-a43b22bb-49eb-4cf2-8049-3efbe2433e09
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=377024571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.377024571
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.2602436577
Short name T803
Test name
Test status
Simulation time 9468349 ps
CPU time 1.26 seconds
Started Apr 21 12:50:54 PM PDT 24
Finished Apr 21 12:50:55 PM PDT 24
Peak memory 235272 kb
Host smart-d12b3b61-6d94-47b4-9cfc-6403df1daccc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2602436577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.2602436577
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.2502761337
Short name T741
Test name
Test status
Simulation time 172863759 ps
CPU time 19.09 seconds
Started Apr 21 12:51:02 PM PDT 24
Finished Apr 21 12:51:21 PM PDT 24
Peak memory 243404 kb
Host smart-2f090956-98de-4993-a995-da68a97deb90
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2502761337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.2502761337
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.222289108
Short name T754
Test name
Test status
Simulation time 111291960 ps
CPU time 8.58 seconds
Started Apr 21 12:50:53 PM PDT 24
Finished Apr 21 12:51:02 PM PDT 24
Peak memory 253156 kb
Host smart-76e9c4bf-5b38-4fe5-a595-333a3a6b1804
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=222289108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.222289108
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.2069530572
Short name T173
Test name
Test status
Simulation time 126458229 ps
CPU time 2.73 seconds
Started Apr 21 12:50:53 PM PDT 24
Finished Apr 21 12:50:56 PM PDT 24
Peak memory 237120 kb
Host smart-33a2cbac-e9b2-4da5-bcc1-e296a4f177c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2069530572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.2069530572
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.2613009640
Short name T807
Test name
Test status
Simulation time 621123039 ps
CPU time 12.79 seconds
Started Apr 21 12:50:58 PM PDT 24
Finished Apr 21 12:51:11 PM PDT 24
Peak memory 251412 kb
Host smart-1ec2a6ca-72a2-405c-9e47-cbca0208adb1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613009640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.2613009640
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.4153767350
Short name T722
Test name
Test status
Simulation time 130669404 ps
CPU time 5.39 seconds
Started Apr 21 12:51:08 PM PDT 24
Finished Apr 21 12:51:13 PM PDT 24
Peak memory 236108 kb
Host smart-8e0f08c1-26f1-492e-bafc-0a5f7dd707b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4153767350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.4153767350
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.3059022302
Short name T760
Test name
Test status
Simulation time 10914444 ps
CPU time 1.3 seconds
Started Apr 21 12:50:57 PM PDT 24
Finished Apr 21 12:50:58 PM PDT 24
Peak memory 235272 kb
Host smart-3a3113fe-bc0e-4e9a-9457-b6886a3c57d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3059022302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.3059022302
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.1223837734
Short name T742
Test name
Test status
Simulation time 1069950022 ps
CPU time 17.87 seconds
Started Apr 21 12:51:06 PM PDT 24
Finished Apr 21 12:51:24 PM PDT 24
Peak memory 239804 kb
Host smart-c57694ac-36c0-4d8b-ae5c-3415e403cbd8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1223837734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.1223837734
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.4061692155
Short name T131
Test name
Test status
Simulation time 777093015 ps
CPU time 94.09 seconds
Started Apr 21 12:51:09 PM PDT 24
Finished Apr 21 12:52:43 PM PDT 24
Peak memory 256496 kb
Host smart-b73cbdc1-5335-4569-a5a4-8caa2dad00a1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4061692155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.4061692155
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.3023027241
Short name T825
Test name
Test status
Simulation time 149784897 ps
CPU time 10.06 seconds
Started Apr 21 12:51:05 PM PDT 24
Finished Apr 21 12:51:16 PM PDT 24
Peak memory 248024 kb
Host smart-78eeac43-e1a5-40eb-8e86-c481239a5b3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3023027241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.3023027241
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.1857837132
Short name T798
Test name
Test status
Simulation time 68344513 ps
CPU time 10.3 seconds
Started Apr 21 12:51:01 PM PDT 24
Finished Apr 21 12:51:12 PM PDT 24
Peak memory 251536 kb
Host smart-56655159-89db-4ae6-a1e2-33b9066854fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857837132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.1857837132
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.51695300
Short name T829
Test name
Test status
Simulation time 97075254 ps
CPU time 5.44 seconds
Started Apr 21 12:50:57 PM PDT 24
Finished Apr 21 12:51:03 PM PDT 24
Peak memory 236104 kb
Host smart-7163d810-64f6-4495-8449-c26e7921870c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=51695300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.51695300
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.1274137590
Short name T790
Test name
Test status
Simulation time 11108583 ps
CPU time 1.36 seconds
Started Apr 21 12:51:03 PM PDT 24
Finished Apr 21 12:51:05 PM PDT 24
Peak memory 235224 kb
Host smart-7a40bf2f-0766-4574-ac48-5a65c0f23fde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1274137590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.1274137590
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.1217837098
Short name T823
Test name
Test status
Simulation time 2254735191 ps
CPU time 21.64 seconds
Started Apr 21 12:51:07 PM PDT 24
Finished Apr 21 12:51:28 PM PDT 24
Peak memory 245064 kb
Host smart-4f4bd53b-4957-4f48-bcac-5ae5d7a08285
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1217837098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.1217837098
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.1690026673
Short name T136
Test name
Test status
Simulation time 21738815997 ps
CPU time 334.51 seconds
Started Apr 21 12:50:57 PM PDT 24
Finished Apr 21 12:56:32 PM PDT 24
Peak memory 270176 kb
Host smart-a88d76b9-00c6-4656-876a-aae30c5c56be
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1690026673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.1690026673
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.1204509230
Short name T132
Test name
Test status
Simulation time 9085089890 ps
CPU time 586.73 seconds
Started Apr 21 12:50:58 PM PDT 24
Finished Apr 21 01:00:45 PM PDT 24
Peak memory 267384 kb
Host smart-86a9937d-b934-42b5-a4a8-73e1afdfc227
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204509230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.1204509230
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.4250750260
Short name T794
Test name
Test status
Simulation time 46156666 ps
CPU time 6.52 seconds
Started Apr 21 12:50:57 PM PDT 24
Finished Apr 21 12:51:04 PM PDT 24
Peak memory 252936 kb
Host smart-1389f22b-9c70-4503-a823-c52155ee1c55
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4250750260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.4250750260
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.3792720796
Short name T734
Test name
Test status
Simulation time 264516513 ps
CPU time 9.44 seconds
Started Apr 21 12:51:10 PM PDT 24
Finished Apr 21 12:51:20 PM PDT 24
Peak memory 251384 kb
Host smart-8a579667-661f-4e08-ac2b-fdc7294cec55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792720796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.3792720796
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.574262066
Short name T811
Test name
Test status
Simulation time 33584859 ps
CPU time 5.74 seconds
Started Apr 21 12:50:59 PM PDT 24
Finished Apr 21 12:51:05 PM PDT 24
Peak memory 236116 kb
Host smart-1628ac00-0372-4e2b-8f49-424efff1f548
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=574262066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.574262066
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.2336548095
Short name T797
Test name
Test status
Simulation time 7007594 ps
CPU time 1.35 seconds
Started Apr 21 12:51:05 PM PDT 24
Finished Apr 21 12:51:07 PM PDT 24
Peak memory 236128 kb
Host smart-796a772e-0574-494d-bbd6-a5acb8bcad4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2336548095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.2336548095
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.11032261
Short name T715
Test name
Test status
Simulation time 4696697701 ps
CPU time 47.64 seconds
Started Apr 21 12:51:02 PM PDT 24
Finished Apr 21 12:51:50 PM PDT 24
Peak memory 244388 kb
Host smart-25f407f9-bd96-4ba6-afad-97a614a69a4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=11032261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_outst
anding.11032261
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.1262647911
Short name T133
Test name
Test status
Simulation time 6390935120 ps
CPU time 142.65 seconds
Started Apr 21 12:50:58 PM PDT 24
Finished Apr 21 12:53:26 PM PDT 24
Peak memory 266288 kb
Host smart-e0e40c2b-8c42-4389-8415-0b8056eba29c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1262647911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.1262647911
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.418652106
Short name T117
Test name
Test status
Simulation time 6146994072 ps
CPU time 459.08 seconds
Started Apr 21 12:50:57 PM PDT 24
Finished Apr 21 12:58:37 PM PDT 24
Peak memory 268756 kb
Host smart-56a216f8-6b3d-47be-af2e-1ca75b5e7b9c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418652106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.418652106
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.1865591324
Short name T762
Test name
Test status
Simulation time 712926839 ps
CPU time 13.5 seconds
Started Apr 21 12:50:58 PM PDT 24
Finished Apr 21 12:51:11 PM PDT 24
Peak memory 251160 kb
Host smart-599e6d0e-9b1f-4119-8bc0-2f3c3cd0ef05
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1865591324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.1865591324
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.3357038126
Short name T79
Test name
Test status
Simulation time 115179840322 ps
CPU time 1860.17 seconds
Started Apr 21 04:16:51 PM PDT 24
Finished Apr 21 04:47:52 PM PDT 24
Peak memory 273776 kb
Host smart-eb17daab-e16f-41cb-88b5-ae4d6a3c9faf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357038126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.3357038126
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.2946465105
Short name T405
Test name
Test status
Simulation time 1320122662 ps
CPU time 18.78 seconds
Started Apr 21 04:16:53 PM PDT 24
Finished Apr 21 04:17:13 PM PDT 24
Peak memory 240884 kb
Host smart-74249c64-4b22-48a9-a9fe-845956f3c39e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2946465105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.2946465105
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.4132275119
Short name T697
Test name
Test status
Simulation time 3661926169 ps
CPU time 244.02 seconds
Started Apr 21 04:16:49 PM PDT 24
Finished Apr 21 04:20:54 PM PDT 24
Peak memory 256892 kb
Host smart-5597f868-2bb9-4e26-89cf-42e4fba96665
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41322
75119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.4132275119
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.185940426
Short name T536
Test name
Test status
Simulation time 535644795 ps
CPU time 15.46 seconds
Started Apr 21 04:16:49 PM PDT 24
Finished Apr 21 04:17:05 PM PDT 24
Peak memory 254968 kb
Host smart-08e3d692-b2dd-4327-9ad2-ba4b91666c9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18594
0426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.185940426
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.2917187892
Short name T7
Test name
Test status
Simulation time 15527084912 ps
CPU time 1153.42 seconds
Started Apr 21 04:16:51 PM PDT 24
Finished Apr 21 04:36:05 PM PDT 24
Peak memory 272256 kb
Host smart-ce98c6d6-ca11-4cb2-a1ca-c8823013c223
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917187892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.2917187892
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.3979537858
Short name T570
Test name
Test status
Simulation time 14534043898 ps
CPU time 1247.92 seconds
Started Apr 21 04:16:53 PM PDT 24
Finished Apr 21 04:37:42 PM PDT 24
Peak memory 281940 kb
Host smart-9600b3a9-a9f9-4f2a-be2b-4fbf9373ee59
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979537858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.3979537858
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.3524945437
Short name T294
Test name
Test status
Simulation time 7323188584 ps
CPU time 169.18 seconds
Started Apr 21 04:16:52 PM PDT 24
Finished Apr 21 04:19:41 PM PDT 24
Peak memory 247428 kb
Host smart-849cba9d-b1a2-4c8d-af2b-886edfea20de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524945437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.3524945437
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.2880621985
Short name T420
Test name
Test status
Simulation time 175562461 ps
CPU time 16.3 seconds
Started Apr 21 04:16:49 PM PDT 24
Finished Apr 21 04:17:06 PM PDT 24
Peak memory 249124 kb
Host smart-5e233113-2228-4c6a-8f0b-8cbfb0d36f3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28806
21985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.2880621985
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.1154698793
Short name T34
Test name
Test status
Simulation time 823568871 ps
CPU time 24.99 seconds
Started Apr 21 04:16:55 PM PDT 24
Finished Apr 21 04:17:20 PM PDT 24
Peak memory 278028 kb
Host smart-b1a9f0dd-b749-4742-ad4c-d9bce5d709b1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1154698793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.1154698793
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.2465215175
Short name T95
Test name
Test status
Simulation time 905603737 ps
CPU time 43.24 seconds
Started Apr 21 04:16:50 PM PDT 24
Finished Apr 21 04:17:33 PM PDT 24
Peak memory 249436 kb
Host smart-c855baf5-3457-432e-ad16-e9ad515af3d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24652
15175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.2465215175
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.1934010969
Short name T377
Test name
Test status
Simulation time 4006777295 ps
CPU time 59.85 seconds
Started Apr 21 04:16:50 PM PDT 24
Finished Apr 21 04:17:50 PM PDT 24
Peak memory 256592 kb
Host smart-c9f77321-78cd-48d8-8605-68ae376d1d6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19340
10969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.1934010969
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.3421819647
Short name T47
Test name
Test status
Simulation time 78255200623 ps
CPU time 2611.11 seconds
Started Apr 21 04:16:58 PM PDT 24
Finished Apr 21 05:00:30 PM PDT 24
Peak memory 281984 kb
Host smart-fcf336b0-5680-4672-8a1c-774420ef9327
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421819647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.3421819647
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.4291544275
Short name T582
Test name
Test status
Simulation time 4646672781 ps
CPU time 49.19 seconds
Started Apr 21 04:16:59 PM PDT 24
Finished Apr 21 04:17:49 PM PDT 24
Peak memory 248904 kb
Host smart-75a822a3-7c1a-4eeb-9403-cb8c6e6b9d09
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4291544275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.4291544275
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.488819425
Short name T467
Test name
Test status
Simulation time 6913182489 ps
CPU time 247.42 seconds
Started Apr 21 04:16:58 PM PDT 24
Finished Apr 21 04:21:05 PM PDT 24
Peak memory 250216 kb
Host smart-3211a189-6716-42a0-b25b-8f3c3093c3ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48881
9425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.488819425
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.1959237903
Short name T548
Test name
Test status
Simulation time 991199722 ps
CPU time 32.04 seconds
Started Apr 21 04:16:59 PM PDT 24
Finished Apr 21 04:17:31 PM PDT 24
Peak memory 249160 kb
Host smart-a3fa88eb-e774-4a41-b298-8004c175111d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19592
37903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.1959237903
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.2137858501
Short name T676
Test name
Test status
Simulation time 130941763230 ps
CPU time 1571.19 seconds
Started Apr 21 04:16:59 PM PDT 24
Finished Apr 21 04:43:11 PM PDT 24
Peak memory 265580 kb
Host smart-1158aa0f-9d29-4fc2-a8e8-a2c6c624fa23
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137858501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.2137858501
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.2737436017
Short name T302
Test name
Test status
Simulation time 7975758778 ps
CPU time 329.94 seconds
Started Apr 21 04:16:59 PM PDT 24
Finished Apr 21 04:22:29 PM PDT 24
Peak memory 255500 kb
Host smart-01c1e894-b01b-44aa-bd68-547309af493f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737436017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.2737436017
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.3918424363
Short name T641
Test name
Test status
Simulation time 371189690 ps
CPU time 34.31 seconds
Started Apr 21 04:16:57 PM PDT 24
Finished Apr 21 04:17:32 PM PDT 24
Peak memory 249092 kb
Host smart-d43f2bd4-ae80-4c69-b062-474cb37f1c85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39184
24363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.3918424363
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.2078946075
Short name T485
Test name
Test status
Simulation time 201950039 ps
CPU time 20.97 seconds
Started Apr 21 04:16:54 PM PDT 24
Finished Apr 21 04:17:15 PM PDT 24
Peak memory 255040 kb
Host smart-adaea73c-b026-4798-9c23-141603721191
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20789
46075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.2078946075
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.1244321748
Short name T33
Test name
Test status
Simulation time 1318132050 ps
CPU time 19.5 seconds
Started Apr 21 04:16:58 PM PDT 24
Finished Apr 21 04:17:18 PM PDT 24
Peak memory 265676 kb
Host smart-a33067eb-c9ae-47d0-8d5e-51e0fa2c2f67
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1244321748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.1244321748
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.3325494310
Short name T74
Test name
Test status
Simulation time 1055592812 ps
CPU time 31.1 seconds
Started Apr 21 04:17:02 PM PDT 24
Finished Apr 21 04:17:33 PM PDT 24
Peak memory 255760 kb
Host smart-8fcd3945-88ed-449b-b8c1-7b4fd1860197
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33254
94310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.3325494310
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.260038041
Short name T355
Test name
Test status
Simulation time 2927043104 ps
CPU time 26.23 seconds
Started Apr 21 04:16:53 PM PDT 24
Finished Apr 21 04:17:20 PM PDT 24
Peak memory 249192 kb
Host smart-4c909515-9bc2-4fc6-a9a5-6825f55e3e17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26003
8041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.260038041
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.2682905066
Short name T28
Test name
Test status
Simulation time 52217912554 ps
CPU time 1640.77 seconds
Started Apr 21 04:17:02 PM PDT 24
Finished Apr 21 04:44:23 PM PDT 24
Peak memory 290120 kb
Host smart-5362558e-29d5-491d-a977-7bac70c87c00
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682905066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.2682905066
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.4211007258
Short name T23
Test name
Test status
Simulation time 53894107597 ps
CPU time 3289.74 seconds
Started Apr 21 04:16:59 PM PDT 24
Finished Apr 21 05:11:49 PM PDT 24
Peak memory 306032 kb
Host smart-501d7a62-4b90-4433-b001-74f219eb284d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211007258 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.4211007258
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.1306302749
Short name T213
Test name
Test status
Simulation time 105410210 ps
CPU time 3.32 seconds
Started Apr 21 04:17:56 PM PDT 24
Finished Apr 21 04:18:00 PM PDT 24
Peak memory 249344 kb
Host smart-3c5466f9-9579-4a57-bdaf-0f4d4ab8f710
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1306302749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.1306302749
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.1419011037
Short name T522
Test name
Test status
Simulation time 187738033503 ps
CPU time 2564.32 seconds
Started Apr 21 04:17:51 PM PDT 24
Finished Apr 21 05:00:36 PM PDT 24
Peak memory 281972 kb
Host smart-e447044d-c9aa-4d45-9db0-0d2564f1f4cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419011037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.1419011037
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.2554659581
Short name T637
Test name
Test status
Simulation time 506471941 ps
CPU time 23.98 seconds
Started Apr 21 04:17:51 PM PDT 24
Finished Apr 21 04:18:15 PM PDT 24
Peak memory 240876 kb
Host smart-07e6f49c-5643-42e7-8adc-2370c788b2d1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2554659581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.2554659581
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.1939645398
Short name T452
Test name
Test status
Simulation time 5032222987 ps
CPU time 160.4 seconds
Started Apr 21 04:17:50 PM PDT 24
Finished Apr 21 04:20:31 PM PDT 24
Peak memory 250432 kb
Host smart-4d6fead4-fbba-4d4c-99f6-27fa4f8fe884
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19396
45398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.1939645398
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.1393896058
Short name T245
Test name
Test status
Simulation time 2271589343 ps
CPU time 82.88 seconds
Started Apr 21 04:17:52 PM PDT 24
Finished Apr 21 04:19:15 PM PDT 24
Peak memory 249236 kb
Host smart-05b5dbe3-9d6e-414a-9c85-a1a09ba02acf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13938
96058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.1393896058
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.2535184100
Short name T314
Test name
Test status
Simulation time 156717528963 ps
CPU time 2535.7 seconds
Started Apr 21 04:17:52 PM PDT 24
Finished Apr 21 05:00:08 PM PDT 24
Peak memory 282984 kb
Host smart-b707c4bc-785d-475a-b405-2f94ff0ca36e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535184100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.2535184100
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.3366032610
Short name T18
Test name
Test status
Simulation time 123902733099 ps
CPU time 1816.98 seconds
Started Apr 21 04:17:53 PM PDT 24
Finished Apr 21 04:48:11 PM PDT 24
Peak memory 273740 kb
Host smart-e0bc3325-d556-4881-b9af-825781c4e26c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366032610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.3366032610
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.3480792596
Short name T315
Test name
Test status
Simulation time 7989968536 ps
CPU time 184.62 seconds
Started Apr 21 04:17:52 PM PDT 24
Finished Apr 21 04:20:57 PM PDT 24
Peak memory 248240 kb
Host smart-e7c698c1-6dff-444d-afe6-b7997e59ff4f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480792596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.3480792596
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.1262043183
Short name T424
Test name
Test status
Simulation time 231850823 ps
CPU time 6.01 seconds
Started Apr 21 04:17:48 PM PDT 24
Finished Apr 21 04:17:54 PM PDT 24
Peak memory 240856 kb
Host smart-ce5b12de-083d-43f9-a44e-be0efcf55b84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12620
43183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.1262043183
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.1115309734
Short name T653
Test name
Test status
Simulation time 353128443 ps
CPU time 20.62 seconds
Started Apr 21 04:17:48 PM PDT 24
Finished Apr 21 04:18:08 PM PDT 24
Peak memory 255516 kb
Host smart-6a234e3e-21ae-4417-adae-39b12fe79ccb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11153
09734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.1115309734
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.2050039435
Short name T242
Test name
Test status
Simulation time 2666566943 ps
CPU time 41.86 seconds
Started Apr 21 04:17:53 PM PDT 24
Finished Apr 21 04:18:35 PM PDT 24
Peak memory 249464 kb
Host smart-c1db9406-ce75-415a-babf-1f8d78b129fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20500
39435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.2050039435
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.1041207695
Short name T357
Test name
Test status
Simulation time 1157989193 ps
CPU time 20.92 seconds
Started Apr 21 04:17:48 PM PDT 24
Finished Apr 21 04:18:09 PM PDT 24
Peak memory 249304 kb
Host smart-94a93671-aad6-411a-830a-7f77c2affaf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10412
07695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.1041207695
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.1882266448
Short name T184
Test name
Test status
Simulation time 45136600990 ps
CPU time 5060.08 seconds
Started Apr 21 04:17:56 PM PDT 24
Finished Apr 21 05:42:17 PM PDT 24
Peak memory 339456 kb
Host smart-1f744aa6-b302-4529-b08e-71850b1efd0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882266448 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.1882266448
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.3577903541
Short name T210
Test name
Test status
Simulation time 446368470 ps
CPU time 4.2 seconds
Started Apr 21 04:17:57 PM PDT 24
Finished Apr 21 04:18:02 PM PDT 24
Peak memory 249364 kb
Host smart-c2d67e1f-4748-4fd8-b4b8-fc802e6cb51e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3577903541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.3577903541
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.642060153
Short name T499
Test name
Test status
Simulation time 25723098217 ps
CPU time 1520.81 seconds
Started Apr 21 04:17:55 PM PDT 24
Finished Apr 21 04:43:17 PM PDT 24
Peak memory 273076 kb
Host smart-a1a7dca4-bb14-4b5d-8980-1a2aa308c1a4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642060153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.642060153
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.3141558017
Short name T496
Test name
Test status
Simulation time 264883635 ps
CPU time 8.68 seconds
Started Apr 21 04:17:58 PM PDT 24
Finished Apr 21 04:18:06 PM PDT 24
Peak memory 240836 kb
Host smart-41ebf96d-8f69-4d42-a172-a431b405a528
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3141558017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.3141558017
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.3732587534
Short name T429
Test name
Test status
Simulation time 617577346 ps
CPU time 22.79 seconds
Started Apr 21 04:17:56 PM PDT 24
Finished Apr 21 04:18:19 PM PDT 24
Peak memory 256180 kb
Host smart-f8ca88e1-b347-4729-a657-a8ca2fa10f21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37325
87534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.3732587534
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.3190330650
Short name T246
Test name
Test status
Simulation time 1143897969 ps
CPU time 36.76 seconds
Started Apr 21 04:17:55 PM PDT 24
Finished Apr 21 04:18:32 PM PDT 24
Peak memory 249080 kb
Host smart-9adef5b4-303b-48ca-af6a-2ce3221e8891
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31903
30650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.3190330650
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.4222252673
Short name T310
Test name
Test status
Simulation time 78422770568 ps
CPU time 1381.41 seconds
Started Apr 21 04:17:57 PM PDT 24
Finished Apr 21 04:40:59 PM PDT 24
Peak memory 288584 kb
Host smart-41f1b9f9-4c8a-4b4c-bb0e-cd630e7c3357
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222252673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.4222252673
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.3044364302
Short name T364
Test name
Test status
Simulation time 37284138843 ps
CPU time 876.78 seconds
Started Apr 21 04:17:57 PM PDT 24
Finished Apr 21 04:32:34 PM PDT 24
Peak memory 273404 kb
Host smart-0a625133-4181-475a-8011-3c0c150415d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044364302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.3044364302
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.1870112192
Short name T518
Test name
Test status
Simulation time 5139684781 ps
CPU time 46.49 seconds
Started Apr 21 04:17:54 PM PDT 24
Finished Apr 21 04:18:41 PM PDT 24
Peak memory 256396 kb
Host smart-0ca9a874-c130-41bd-bbad-d837a8322d72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18701
12192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.1870112192
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.1928983966
Short name T521
Test name
Test status
Simulation time 750808538 ps
CPU time 50.53 seconds
Started Apr 21 04:17:58 PM PDT 24
Finished Apr 21 04:18:48 PM PDT 24
Peak memory 248852 kb
Host smart-8f00975b-55a3-4898-9ba5-2c0e9584311c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19289
83966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.1928983966
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.1773962241
Short name T492
Test name
Test status
Simulation time 31783709 ps
CPU time 5.22 seconds
Started Apr 21 04:17:57 PM PDT 24
Finished Apr 21 04:18:03 PM PDT 24
Peak memory 251236 kb
Host smart-9d26bb5a-2bdb-471b-a5f3-ab91823a0482
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17739
62241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.1773962241
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.2412252729
Short name T360
Test name
Test status
Simulation time 494628862 ps
CPU time 32.31 seconds
Started Apr 21 04:17:55 PM PDT 24
Finished Apr 21 04:18:27 PM PDT 24
Peak memory 256264 kb
Host smart-da76274f-902f-4f7c-8462-3fbc1c64fe1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24122
52729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.2412252729
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.2141944213
Short name T532
Test name
Test status
Simulation time 61924965650 ps
CPU time 3587.9 seconds
Started Apr 21 04:17:55 PM PDT 24
Finished Apr 21 05:17:43 PM PDT 24
Peak memory 289812 kb
Host smart-a5127ae3-5258-4fbf-9538-02baab1ab2ec
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141944213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.2141944213
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.3104202911
Short name T569
Test name
Test status
Simulation time 154768579136 ps
CPU time 3305.67 seconds
Started Apr 21 04:17:55 PM PDT 24
Finished Apr 21 05:13:01 PM PDT 24
Peak memory 322644 kb
Host smart-d7a3af56-4145-4225-b952-c741d1706212
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104202911 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.3104202911
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.8126441
Short name T208
Test name
Test status
Simulation time 52503064 ps
CPU time 2.72 seconds
Started Apr 21 04:18:08 PM PDT 24
Finished Apr 21 04:18:11 PM PDT 24
Peak memory 249252 kb
Host smart-3403065d-0776-499f-bd2e-c924970a3637
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=8126441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.8126441
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.540131718
Short name T542
Test name
Test status
Simulation time 45790717796 ps
CPU time 1559.01 seconds
Started Apr 21 04:18:06 PM PDT 24
Finished Apr 21 04:44:06 PM PDT 24
Peak memory 265596 kb
Host smart-8dd9abe4-841b-44b8-aba4-27469366ad73
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540131718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.540131718
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.3931799356
Short name T71
Test name
Test status
Simulation time 172852866 ps
CPU time 11.26 seconds
Started Apr 21 04:18:01 PM PDT 24
Finished Apr 21 04:18:13 PM PDT 24
Peak memory 240852 kb
Host smart-fb7a99d7-6d3e-4318-8859-54223c5425a2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3931799356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.3931799356
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.4012650147
Short name T572
Test name
Test status
Simulation time 2439863964 ps
CPU time 72.09 seconds
Started Apr 21 04:18:03 PM PDT 24
Finished Apr 21 04:19:15 PM PDT 24
Peak memory 257136 kb
Host smart-cfef8252-c632-44f4-bb3c-fe58ad888dd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40126
50147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.4012650147
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.3427916247
Short name T407
Test name
Test status
Simulation time 384805025 ps
CPU time 14.81 seconds
Started Apr 21 04:18:02 PM PDT 24
Finished Apr 21 04:18:17 PM PDT 24
Peak memory 254772 kb
Host smart-3284e312-be13-4088-b8eb-285eff50b5e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34279
16247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.3427916247
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.1689193149
Short name T342
Test name
Test status
Simulation time 24409086873 ps
CPU time 1614.78 seconds
Started Apr 21 04:18:05 PM PDT 24
Finished Apr 21 04:45:00 PM PDT 24
Peak memory 272988 kb
Host smart-a4fdcab8-0c75-459a-9fec-381f126faafe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689193149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.1689193149
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.1689709680
Short name T487
Test name
Test status
Simulation time 26344591419 ps
CPU time 818.34 seconds
Started Apr 21 04:18:02 PM PDT 24
Finished Apr 21 04:31:41 PM PDT 24
Peak memory 273704 kb
Host smart-92390cd2-51b3-46f2-ba7b-974f46b9da05
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689709680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.1689709680
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.2955771554
Short name T437
Test name
Test status
Simulation time 173191553 ps
CPU time 5.38 seconds
Started Apr 21 04:17:59 PM PDT 24
Finished Apr 21 04:18:05 PM PDT 24
Peak memory 250820 kb
Host smart-42938282-b58f-4eb7-b40c-bd71a635d626
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29557
71554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.2955771554
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.1249987034
Short name T567
Test name
Test status
Simulation time 4945186182 ps
CPU time 49.02 seconds
Started Apr 21 04:18:02 PM PDT 24
Finished Apr 21 04:18:51 PM PDT 24
Peak memory 249232 kb
Host smart-f4d2571d-9638-4a90-aab3-f9c3d5dc95c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12499
87034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.1249987034
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.69141844
Short name T684
Test name
Test status
Simulation time 127508176 ps
CPU time 9.76 seconds
Started Apr 21 04:18:02 PM PDT 24
Finished Apr 21 04:18:12 PM PDT 24
Peak memory 249364 kb
Host smart-79bb73dc-1056-4d4b-b7c1-1a0a9a4cd5fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69141
844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.69141844
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.2901922955
Short name T489
Test name
Test status
Simulation time 3218329940 ps
CPU time 51.89 seconds
Started Apr 21 04:18:00 PM PDT 24
Finished Apr 21 04:18:52 PM PDT 24
Peak memory 249516 kb
Host smart-80aed9b8-d5ad-41ba-9e22-7c6538b06a9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29019
22955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.2901922955
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.368405267
Short name T58
Test name
Test status
Simulation time 45917655607 ps
CPU time 2858.12 seconds
Started Apr 21 04:18:06 PM PDT 24
Finished Apr 21 05:05:45 PM PDT 24
Peak memory 298344 kb
Host smart-687830ca-86f7-4ff1-90ee-ac507c66ffc4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368405267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_han
dler_stress_all.368405267
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.1556823325
Short name T60
Test name
Test status
Simulation time 32576668087 ps
CPU time 1248.54 seconds
Started Apr 21 04:18:08 PM PDT 24
Finished Apr 21 04:38:56 PM PDT 24
Peak memory 289060 kb
Host smart-867b3fce-e3be-43f0-8e26-b12d8af7a27a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556823325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.1556823325
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.3158349652
Short name T669
Test name
Test status
Simulation time 994106212 ps
CPU time 13 seconds
Started Apr 21 04:18:11 PM PDT 24
Finished Apr 21 04:18:25 PM PDT 24
Peak memory 240872 kb
Host smart-9a94fe60-d694-47fc-a039-471262598b24
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3158349652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.3158349652
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.1727353275
Short name T371
Test name
Test status
Simulation time 22472540658 ps
CPU time 363.44 seconds
Started Apr 21 04:18:09 PM PDT 24
Finished Apr 21 04:24:12 PM PDT 24
Peak memory 257120 kb
Host smart-04a63493-4db4-430a-8179-f7705f1b9930
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17273
53275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.1727353275
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.2009771930
Short name T608
Test name
Test status
Simulation time 281595201 ps
CPU time 23.19 seconds
Started Apr 21 04:18:07 PM PDT 24
Finished Apr 21 04:18:30 PM PDT 24
Peak memory 254344 kb
Host smart-87727aa8-8118-448f-b57b-bcb3866f95c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20097
71930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.2009771930
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.2065428613
Short name T341
Test name
Test status
Simulation time 44328754456 ps
CPU time 808.39 seconds
Started Apr 21 04:18:07 PM PDT 24
Finished Apr 21 04:31:36 PM PDT 24
Peak memory 273616 kb
Host smart-283fb8ad-2c1d-4caf-a46b-3d2e9ba02f27
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065428613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.2065428613
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.2035836036
Short name T675
Test name
Test status
Simulation time 81955220850 ps
CPU time 2584.91 seconds
Started Apr 21 04:18:09 PM PDT 24
Finished Apr 21 05:01:14 PM PDT 24
Peak memory 281980 kb
Host smart-272cf2a5-8393-4220-872e-083fafdb5d2e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035836036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.2035836036
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.894232212
Short name T313
Test name
Test status
Simulation time 6024007715 ps
CPU time 257.1 seconds
Started Apr 21 04:18:09 PM PDT 24
Finished Apr 21 04:22:27 PM PDT 24
Peak memory 248276 kb
Host smart-b953be0f-c9cb-4f8e-8439-61f80ca0a7ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894232212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.894232212
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.3766006858
Short name T667
Test name
Test status
Simulation time 2782139041 ps
CPU time 51.61 seconds
Started Apr 21 04:18:06 PM PDT 24
Finished Apr 21 04:18:58 PM PDT 24
Peak memory 249188 kb
Host smart-4bfec5af-3e1d-4f47-8b41-a8c353483722
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37660
06858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.3766006858
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.1654572012
Short name T376
Test name
Test status
Simulation time 72274931 ps
CPU time 10.69 seconds
Started Apr 21 04:18:07 PM PDT 24
Finished Apr 21 04:18:18 PM PDT 24
Peak memory 254252 kb
Host smart-27d317a5-c905-4c3d-92dc-daa124aec025
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16545
72012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.1654572012
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.3167127794
Short name T400
Test name
Test status
Simulation time 228602105 ps
CPU time 23.09 seconds
Started Apr 21 04:18:07 PM PDT 24
Finished Apr 21 04:18:30 PM PDT 24
Peak memory 255776 kb
Host smart-46a1ef03-0e59-4081-8c9d-2e4bbbc90a4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31671
27794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.3167127794
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.2443510005
Short name T706
Test name
Test status
Simulation time 3748163123 ps
CPU time 43.97 seconds
Started Apr 21 04:18:05 PM PDT 24
Finished Apr 21 04:18:49 PM PDT 24
Peak memory 249200 kb
Host smart-6cfef293-ec4b-4764-8b58-d569caba9fc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24435
10005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.2443510005
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.868765835
Short name T553
Test name
Test status
Simulation time 10472522705 ps
CPU time 204.95 seconds
Started Apr 21 04:18:11 PM PDT 24
Finished Apr 21 04:21:36 PM PDT 24
Peak memory 257412 kb
Host smart-2f4b0fe9-2967-43cc-8932-d3a51c611e78
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868765835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_han
dler_stress_all.868765835
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.1324586910
Short name T229
Test name
Test status
Simulation time 305919236835 ps
CPU time 4708.73 seconds
Started Apr 21 04:18:14 PM PDT 24
Finished Apr 21 05:36:44 PM PDT 24
Peak memory 289976 kb
Host smart-c2ab63db-b156-49e6-affc-eef5177f0a99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324586910 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.1324586910
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.1722792814
Short name T211
Test name
Test status
Simulation time 51356600 ps
CPU time 4.22 seconds
Started Apr 21 04:18:18 PM PDT 24
Finished Apr 21 04:18:23 PM PDT 24
Peak memory 257564 kb
Host smart-597a1eb8-0771-41e8-af17-65a37fb9b8b5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1722792814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.1722792814
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.2446583936
Short name T443
Test name
Test status
Simulation time 135839237972 ps
CPU time 2111.32 seconds
Started Apr 21 04:18:16 PM PDT 24
Finished Apr 21 04:53:28 PM PDT 24
Peak memory 289488 kb
Host smart-ce361d02-23cb-4a7d-b267-0533dde58af0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446583936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.2446583936
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.731246948
Short name T39
Test name
Test status
Simulation time 1007989624 ps
CPU time 23.58 seconds
Started Apr 21 04:18:19 PM PDT 24
Finished Apr 21 04:18:44 PM PDT 24
Peak memory 249108 kb
Host smart-a05a8f22-ce91-4408-a4e8-eb6f7567905d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=731246948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.731246948
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.317480806
Short name T640
Test name
Test status
Simulation time 819551440 ps
CPU time 23.78 seconds
Started Apr 21 04:18:14 PM PDT 24
Finished Apr 21 04:18:38 PM PDT 24
Peak memory 249076 kb
Host smart-b07ff7e7-6787-4015-8366-522c74ba2668
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31748
0806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.317480806
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.4155173050
Short name T559
Test name
Test status
Simulation time 310515604 ps
CPU time 21.2 seconds
Started Apr 21 04:18:15 PM PDT 24
Finished Apr 21 04:18:37 PM PDT 24
Peak memory 255804 kb
Host smart-d216bd10-3090-4deb-bcd0-3cb8dd69a32d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41551
73050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.4155173050
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.710650560
Short name T332
Test name
Test status
Simulation time 33333231100 ps
CPU time 1610.88 seconds
Started Apr 21 04:18:16 PM PDT 24
Finished Apr 21 04:45:07 PM PDT 24
Peak memory 290180 kb
Host smart-9f885a2f-9220-464f-a366-1d1b981ecc43
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710650560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.710650560
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.1651050767
Short name T374
Test name
Test status
Simulation time 25086005682 ps
CPU time 1667.35 seconds
Started Apr 21 04:18:19 PM PDT 24
Finished Apr 21 04:46:07 PM PDT 24
Peak memory 273736 kb
Host smart-47a11ba3-bb89-48b8-9f6a-15862c65e0ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651050767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.1651050767
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.1697484851
Short name T464
Test name
Test status
Simulation time 3263452076 ps
CPU time 23.43 seconds
Started Apr 21 04:18:18 PM PDT 24
Finished Apr 21 04:18:42 PM PDT 24
Peak memory 249380 kb
Host smart-6bd53996-61a4-4a4b-a0d9-829cc3024c1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16974
84851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.1697484851
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.704202176
Short name T31
Test name
Test status
Simulation time 62793462 ps
CPU time 6.29 seconds
Started Apr 21 04:18:15 PM PDT 24
Finished Apr 21 04:18:22 PM PDT 24
Peak memory 249456 kb
Host smart-27939692-709f-4fd5-899f-e167d2769506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70420
2176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.704202176
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.801224722
Short name T546
Test name
Test status
Simulation time 825592761 ps
CPU time 30.04 seconds
Started Apr 21 04:18:18 PM PDT 24
Finished Apr 21 04:18:48 PM PDT 24
Peak memory 255140 kb
Host smart-7a1f013a-eaf9-4578-83a1-8d72c5cf96ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80122
4722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.801224722
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.2577685595
Short name T455
Test name
Test status
Simulation time 1512972564 ps
CPU time 47.23 seconds
Started Apr 21 04:18:15 PM PDT 24
Finished Apr 21 04:19:02 PM PDT 24
Peak memory 256328 kb
Host smart-a4513b59-37b2-4441-be98-89a3db04641e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25776
85595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.2577685595
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.1868306856
Short name T244
Test name
Test status
Simulation time 20609365307 ps
CPU time 1050.84 seconds
Started Apr 21 04:18:18 PM PDT 24
Finished Apr 21 04:35:50 PM PDT 24
Peak memory 265596 kb
Host smart-68feb56e-2578-4150-8b33-933106bcab0b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868306856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.1868306856
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.2733690853
Short name T209
Test name
Test status
Simulation time 166340365 ps
CPU time 3.66 seconds
Started Apr 21 04:18:26 PM PDT 24
Finished Apr 21 04:18:29 PM PDT 24
Peak memory 249380 kb
Host smart-34610459-4ff6-455c-9f32-b63893181dbe
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2733690853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.2733690853
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.3496356637
Short name T432
Test name
Test status
Simulation time 45928136746 ps
CPU time 2708.92 seconds
Started Apr 21 04:18:21 PM PDT 24
Finished Apr 21 05:03:31 PM PDT 24
Peak memory 289540 kb
Host smart-54bd6a2b-ac4d-4f1c-9c33-541fd3241351
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496356637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.3496356637
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.1480587079
Short name T683
Test name
Test status
Simulation time 763905877 ps
CPU time 10.96 seconds
Started Apr 21 04:18:23 PM PDT 24
Finished Apr 21 04:18:35 PM PDT 24
Peak memory 240884 kb
Host smart-06299629-e9ae-45df-b0b4-470aaf0fd2f4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1480587079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.1480587079
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.2933409070
Short name T617
Test name
Test status
Simulation time 22371857162 ps
CPU time 365.5 seconds
Started Apr 21 04:18:20 PM PDT 24
Finished Apr 21 04:24:26 PM PDT 24
Peak memory 257376 kb
Host smart-afce87b8-1db6-4fbd-9d0a-b9e739e285ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29334
09070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.2933409070
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.2572333804
Short name T448
Test name
Test status
Simulation time 178080779 ps
CPU time 22.61 seconds
Started Apr 21 04:18:23 PM PDT 24
Finished Apr 21 04:18:46 PM PDT 24
Peak memory 255896 kb
Host smart-1407dfad-c570-403c-949f-432311d5202a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25723
33804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.2572333804
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.763519597
Short name T298
Test name
Test status
Simulation time 9442468303 ps
CPU time 1071.9 seconds
Started Apr 21 04:18:24 PM PDT 24
Finished Apr 21 04:36:16 PM PDT 24
Peak memory 273760 kb
Host smart-9a8c9e52-20e2-4915-8d65-aec4871bd262
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763519597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.763519597
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.2083432788
Short name T382
Test name
Test status
Simulation time 50086415781 ps
CPU time 3164.65 seconds
Started Apr 21 04:18:24 PM PDT 24
Finished Apr 21 05:11:09 PM PDT 24
Peak memory 289596 kb
Host smart-570af643-3c7d-489f-aae6-71c6c20c2120
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083432788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.2083432788
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.3262235291
Short name T356
Test name
Test status
Simulation time 557189628 ps
CPU time 16.73 seconds
Started Apr 21 04:18:20 PM PDT 24
Finished Apr 21 04:18:37 PM PDT 24
Peak memory 249116 kb
Host smart-c3f3fd57-49f2-435d-8a85-dc2d129fedf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32622
35291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.3262235291
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.2104035061
Short name T580
Test name
Test status
Simulation time 574164695 ps
CPU time 23.26 seconds
Started Apr 21 04:18:22 PM PDT 24
Finished Apr 21 04:18:46 PM PDT 24
Peak memory 254952 kb
Host smart-643bce7c-c61b-4f55-9009-b0b80e293298
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21040
35061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.2104035061
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.3231147497
Short name T416
Test name
Test status
Simulation time 794524176 ps
CPU time 45.47 seconds
Started Apr 21 04:18:22 PM PDT 24
Finished Apr 21 04:19:08 PM PDT 24
Peak memory 255788 kb
Host smart-99201418-a873-49c4-971b-8f2af7f61d78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32311
47497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.3231147497
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.2077683100
Short name T381
Test name
Test status
Simulation time 823226718 ps
CPU time 48.24 seconds
Started Apr 21 04:18:20 PM PDT 24
Finished Apr 21 04:19:08 PM PDT 24
Peak memory 256216 kb
Host smart-f9bbc7a3-5f9c-4bee-a690-de8af5f4f136
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20776
83100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.2077683100
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.643505661
Short name T477
Test name
Test status
Simulation time 10208755189 ps
CPU time 230.73 seconds
Started Apr 21 04:18:24 PM PDT 24
Finished Apr 21 04:22:15 PM PDT 24
Peak memory 257400 kb
Host smart-8392b59c-26bd-42b6-bc23-131e649e4eb0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643505661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_han
dler_stress_all.643505661
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.1812566740
Short name T233
Test name
Test status
Simulation time 70590686467 ps
CPU time 964.58 seconds
Started Apr 21 04:18:27 PM PDT 24
Finished Apr 21 04:34:32 PM PDT 24
Peak memory 282088 kb
Host smart-21238684-4bd6-4252-a086-590cd64862e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812566740 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.1812566740
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.3771535814
Short name T214
Test name
Test status
Simulation time 29911983 ps
CPU time 3.26 seconds
Started Apr 21 04:18:33 PM PDT 24
Finished Apr 21 04:18:37 PM PDT 24
Peak memory 249408 kb
Host smart-dd91120c-fc10-4789-a4dd-f57d23e3ca2d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3771535814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.3771535814
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.282449199
Short name T107
Test name
Test status
Simulation time 40487739174 ps
CPU time 2038.3 seconds
Started Apr 21 04:18:30 PM PDT 24
Finished Apr 21 04:52:28 PM PDT 24
Peak memory 281972 kb
Host smart-d8b75032-c2f7-4489-b575-61f1f542596b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282449199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.282449199
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.2532542934
Short name T613
Test name
Test status
Simulation time 2076533178 ps
CPU time 90.08 seconds
Started Apr 21 04:18:31 PM PDT 24
Finished Apr 21 04:20:01 PM PDT 24
Peak memory 249052 kb
Host smart-81a02a50-dfd0-48f6-af19-219fb10e4496
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2532542934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.2532542934
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.3224765092
Short name T88
Test name
Test status
Simulation time 3516532375 ps
CPU time 91.15 seconds
Started Apr 21 04:18:26 PM PDT 24
Finished Apr 21 04:19:58 PM PDT 24
Peak memory 257208 kb
Host smart-5f21694c-58a8-4095-b92f-9d44542732a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32247
65092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.3224765092
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.1128926898
Short name T562
Test name
Test status
Simulation time 855945126 ps
CPU time 62.66 seconds
Started Apr 21 04:18:28 PM PDT 24
Finished Apr 21 04:19:31 PM PDT 24
Peak memory 255592 kb
Host smart-e0d0844b-fdc7-499b-8c45-cd8188a25858
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11289
26898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.1128926898
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.140682047
Short name T710
Test name
Test status
Simulation time 41976355899 ps
CPU time 1619.94 seconds
Started Apr 21 04:18:29 PM PDT 24
Finished Apr 21 04:45:29 PM PDT 24
Peak memory 273376 kb
Host smart-8c138a94-f2bd-42ca-8108-9d4d15ca7929
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140682047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.140682047
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.2218665162
Short name T14
Test name
Test status
Simulation time 41487343658 ps
CPU time 1267.55 seconds
Started Apr 21 04:18:33 PM PDT 24
Finished Apr 21 04:39:41 PM PDT 24
Peak memory 289572 kb
Host smart-0ff7eea8-d5d2-4fde-822a-58595c321443
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218665162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.2218665162
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.1475078289
Short name T305
Test name
Test status
Simulation time 12469805247 ps
CPU time 519.11 seconds
Started Apr 21 04:18:30 PM PDT 24
Finished Apr 21 04:27:09 PM PDT 24
Peak memory 248344 kb
Host smart-7cbe7680-f36b-4031-84c8-fc7ab6404bad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475078289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.1475078289
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.3074175347
Short name T35
Test name
Test status
Simulation time 1555605391 ps
CPU time 20.77 seconds
Started Apr 21 04:18:28 PM PDT 24
Finished Apr 21 04:18:48 PM PDT 24
Peak memory 249088 kb
Host smart-fe371cb4-3f89-423f-ac57-d5a78f8b1976
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30741
75347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.3074175347
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.2321839918
Short name T466
Test name
Test status
Simulation time 1074539938 ps
CPU time 16.72 seconds
Started Apr 21 04:18:28 PM PDT 24
Finished Apr 21 04:18:45 PM PDT 24
Peak memory 249336 kb
Host smart-fd5adfbd-a159-4f5b-a8fc-56b11a72de2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23218
39918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.2321839918
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.1380331446
Short name T408
Test name
Test status
Simulation time 1609419289 ps
CPU time 38.15 seconds
Started Apr 21 04:18:27 PM PDT 24
Finished Apr 21 04:19:05 PM PDT 24
Peak memory 249104 kb
Host smart-a71d19b9-52ec-4c13-a43e-9ebfc258c20a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13803
31446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.1380331446
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.424867033
Short name T403
Test name
Test status
Simulation time 47660211647 ps
CPU time 2909.76 seconds
Started Apr 21 04:18:33 PM PDT 24
Finished Apr 21 05:07:03 PM PDT 24
Peak memory 287080 kb
Host smart-15db3a19-d113-42d9-8055-eb1a98fbc7fa
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424867033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_han
dler_stress_all.424867033
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.1663784236
Short name T55
Test name
Test status
Simulation time 42964103135 ps
CPU time 3304.88 seconds
Started Apr 21 04:18:31 PM PDT 24
Finished Apr 21 05:13:37 PM PDT 24
Peak memory 305976 kb
Host smart-7617f775-3610-4e4e-a340-d047ed321b12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663784236 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.1663784236
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.1710826077
Short name T205
Test name
Test status
Simulation time 108541922 ps
CPU time 4.26 seconds
Started Apr 21 04:18:36 PM PDT 24
Finished Apr 21 04:18:41 PM PDT 24
Peak memory 249364 kb
Host smart-ed3ee910-54db-49ed-82f6-f6c750c61cd1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1710826077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.1710826077
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.3619839812
Short name T491
Test name
Test status
Simulation time 26076715767 ps
CPU time 1206.24 seconds
Started Apr 21 04:18:34 PM PDT 24
Finished Apr 21 04:38:41 PM PDT 24
Peak memory 273348 kb
Host smart-84438bde-e3b1-4484-aa38-74688cf4b66a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619839812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.3619839812
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.1695059019
Short name T387
Test name
Test status
Simulation time 3981734108 ps
CPU time 146.89 seconds
Started Apr 21 04:18:34 PM PDT 24
Finished Apr 21 04:21:01 PM PDT 24
Peak memory 256752 kb
Host smart-d01d8398-51bd-46f9-8146-1c3322d436c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16950
59019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.1695059019
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.3490893544
Short name T481
Test name
Test status
Simulation time 2938231403 ps
CPU time 46.75 seconds
Started Apr 21 04:18:36 PM PDT 24
Finished Apr 21 04:19:23 PM PDT 24
Peak memory 249104 kb
Host smart-0ce21027-3e57-45e0-aef8-83e2e9ec26d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34908
93544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.3490893544
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.3553240208
Short name T545
Test name
Test status
Simulation time 31603841145 ps
CPU time 708.75 seconds
Started Apr 21 04:18:37 PM PDT 24
Finished Apr 21 04:30:26 PM PDT 24
Peak memory 265600 kb
Host smart-b7b8f8c5-00a5-47ba-8048-cad90c61c713
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553240208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.3553240208
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.437268532
Short name T519
Test name
Test status
Simulation time 36317880039 ps
CPU time 2464.12 seconds
Started Apr 21 04:18:38 PM PDT 24
Finished Apr 21 04:59:42 PM PDT 24
Peak memory 290144 kb
Host smart-216f18c2-bf70-46b8-b481-dc3d6afe4e67
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437268532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.437268532
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.2933214272
Short name T594
Test name
Test status
Simulation time 1340918564 ps
CPU time 59.27 seconds
Started Apr 21 04:18:35 PM PDT 24
Finished Apr 21 04:19:34 PM PDT 24
Peak memory 249104 kb
Host smart-3545afb5-dad6-4c82-a411-7f224bdaf606
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933214272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.2933214272
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.394855120
Short name T48
Test name
Test status
Simulation time 474405866 ps
CPU time 15.9 seconds
Started Apr 21 04:18:34 PM PDT 24
Finished Apr 21 04:18:50 PM PDT 24
Peak memory 249132 kb
Host smart-e0c4983c-32e5-4352-96c3-0cf871335e29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39485
5120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.394855120
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.3421467593
Short name T390
Test name
Test status
Simulation time 526298003 ps
CPU time 36.56 seconds
Started Apr 21 04:18:34 PM PDT 24
Finished Apr 21 04:19:11 PM PDT 24
Peak memory 255144 kb
Host smart-54067d82-2e09-4ec9-8b44-14407a11d7b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34214
67593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.3421467593
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.2147541790
Short name T618
Test name
Test status
Simulation time 3337076511 ps
CPU time 58.94 seconds
Started Apr 21 04:18:34 PM PDT 24
Finished Apr 21 04:19:34 PM PDT 24
Peak memory 256088 kb
Host smart-54108f7f-3512-4afb-8eff-4a4bd5998bd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21475
41790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.2147541790
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.1221065652
Short name T579
Test name
Test status
Simulation time 1011718768 ps
CPU time 61.65 seconds
Started Apr 21 04:18:33 PM PDT 24
Finished Apr 21 04:19:35 PM PDT 24
Peak memory 249076 kb
Host smart-f482af15-62ef-4fa6-870c-9e12d5c98a6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12210
65652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.1221065652
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.3478189234
Short name T16
Test name
Test status
Simulation time 20568182409 ps
CPU time 1145.87 seconds
Started Apr 21 04:18:42 PM PDT 24
Finished Apr 21 04:37:49 PM PDT 24
Peak memory 265780 kb
Host smart-e0089827-83ed-4425-9b73-41b32cb40d18
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478189234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.3478189234
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.1154663695
Short name T447
Test name
Test status
Simulation time 870160777 ps
CPU time 21.55 seconds
Started Apr 21 04:18:46 PM PDT 24
Finished Apr 21 04:19:08 PM PDT 24
Peak memory 250844 kb
Host smart-c1c5fb21-c278-4792-b629-387d1aa5ba98
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1154663695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.1154663695
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.212829111
Short name T451
Test name
Test status
Simulation time 7840367051 ps
CPU time 117.95 seconds
Started Apr 21 04:18:43 PM PDT 24
Finished Apr 21 04:20:41 PM PDT 24
Peak memory 248952 kb
Host smart-bbd78e1b-b19e-4c0b-a4d6-b5e083d6dcff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21282
9111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.212829111
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.33916060
Short name T450
Test name
Test status
Simulation time 274593393 ps
CPU time 10.99 seconds
Started Apr 21 04:18:43 PM PDT 24
Finished Apr 21 04:18:55 PM PDT 24
Peak memory 249272 kb
Host smart-bba9539e-fdb1-47fe-aed6-e85f2a206390
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33916
060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.33916060
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.582146871
Short name T219
Test name
Test status
Simulation time 9750554121 ps
CPU time 778.31 seconds
Started Apr 21 04:18:47 PM PDT 24
Finished Apr 21 04:31:46 PM PDT 24
Peak memory 265492 kb
Host smart-f476fdb9-880a-4bb0-8b68-ac4df717c505
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582146871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.582146871
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.1718051186
Short name T64
Test name
Test status
Simulation time 16297421155 ps
CPU time 613.61 seconds
Started Apr 21 04:18:45 PM PDT 24
Finished Apr 21 04:28:59 PM PDT 24
Peak memory 273624 kb
Host smart-8b133788-eaf1-42ec-a760-ccd9c5c2be11
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718051186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.1718051186
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.684452616
Short name T217
Test name
Test status
Simulation time 21285463694 ps
CPU time 240.67 seconds
Started Apr 21 04:18:44 PM PDT 24
Finished Apr 21 04:22:45 PM PDT 24
Peak memory 247316 kb
Host smart-6716cacc-e6dc-4cdf-a41c-d7830afc1895
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684452616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.684452616
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.1074638197
Short name T609
Test name
Test status
Simulation time 234245380 ps
CPU time 31.89 seconds
Started Apr 21 04:18:40 PM PDT 24
Finished Apr 21 04:19:12 PM PDT 24
Peak memory 255848 kb
Host smart-0eaa7657-a692-4ac7-ba2a-03e85e228f86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10746
38197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.1074638197
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.2522460991
Short name T602
Test name
Test status
Simulation time 4201580513 ps
CPU time 27.87 seconds
Started Apr 21 04:18:42 PM PDT 24
Finished Apr 21 04:19:10 PM PDT 24
Peak memory 249188 kb
Host smart-47872fd4-f9c4-451d-babd-b24f562a5c6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25224
60991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.2522460991
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.2761840659
Short name T220
Test name
Test status
Simulation time 1298962280 ps
CPU time 22.42 seconds
Started Apr 21 04:18:37 PM PDT 24
Finished Apr 21 04:19:00 PM PDT 24
Peak memory 255772 kb
Host smart-87a02b41-d3de-48a5-8793-0bf415335ac1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27618
40659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.2761840659
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.485885748
Short name T22
Test name
Test status
Simulation time 13054421340 ps
CPU time 611.78 seconds
Started Apr 21 04:18:46 PM PDT 24
Finished Apr 21 04:28:58 PM PDT 24
Peak memory 265588 kb
Host smart-7f7f2582-bc8d-4f8a-8827-da91433dbb15
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485885748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_han
dler_stress_all.485885748
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.657234793
Short name T204
Test name
Test status
Simulation time 16234668 ps
CPU time 2.81 seconds
Started Apr 21 04:18:57 PM PDT 24
Finished Apr 21 04:19:00 PM PDT 24
Peak memory 249376 kb
Host smart-8c0a5459-5a59-45b5-8caa-fa3f407feded
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=657234793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.657234793
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.1598603264
Short name T645
Test name
Test status
Simulation time 10094009737 ps
CPU time 1271.72 seconds
Started Apr 21 04:18:54 PM PDT 24
Finished Apr 21 04:40:06 PM PDT 24
Peak memory 281880 kb
Host smart-d6d71ad7-5f4d-45c7-bca8-9e95431504ff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598603264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.1598603264
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.4175035437
Short name T472
Test name
Test status
Simulation time 3959034929 ps
CPU time 47.83 seconds
Started Apr 21 04:18:54 PM PDT 24
Finished Apr 21 04:19:42 PM PDT 24
Peak memory 249188 kb
Host smart-4112ef97-0a80-44f2-b5ce-6ba6249d66a4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4175035437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.4175035437
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.1826569718
Short name T237
Test name
Test status
Simulation time 13797861863 ps
CPU time 201.95 seconds
Started Apr 21 04:18:52 PM PDT 24
Finished Apr 21 04:22:14 PM PDT 24
Peak memory 250560 kb
Host smart-947bd18f-15bb-4136-bef9-1fd683f49776
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18265
69718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.1826569718
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.3082558797
Short name T82
Test name
Test status
Simulation time 238371816 ps
CPU time 20.68 seconds
Started Apr 21 04:18:52 PM PDT 24
Finished Apr 21 04:19:13 PM PDT 24
Peak memory 255760 kb
Host smart-99ade5ba-594e-46b3-8938-5f011421c4c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30825
58797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.3082558797
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.1272032719
Short name T218
Test name
Test status
Simulation time 68062037931 ps
CPU time 1519.64 seconds
Started Apr 21 04:18:56 PM PDT 24
Finished Apr 21 04:44:16 PM PDT 24
Peak memory 289440 kb
Host smart-63f12a98-014e-4c7f-87da-af87558d6d30
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272032719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.1272032719
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.3689565951
Short name T27
Test name
Test status
Simulation time 77510451705 ps
CPU time 1183.46 seconds
Started Apr 21 04:18:54 PM PDT 24
Finished Apr 21 04:38:38 PM PDT 24
Peak memory 288820 kb
Host smart-4910f5e2-e640-4332-954a-0399817e6c96
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689565951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.3689565951
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.3464718115
Short name T308
Test name
Test status
Simulation time 32816798934 ps
CPU time 353.03 seconds
Started Apr 21 04:18:55 PM PDT 24
Finished Apr 21 04:24:48 PM PDT 24
Peak memory 248440 kb
Host smart-21f5249c-70e9-47df-b5bd-2f25398acf24
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464718115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.3464718115
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.1748222028
Short name T575
Test name
Test status
Simulation time 207107936 ps
CPU time 24.82 seconds
Started Apr 21 04:18:50 PM PDT 24
Finished Apr 21 04:19:15 PM PDT 24
Peak memory 249088 kb
Host smart-b5a8d051-2abd-4aeb-9e7e-0844788162c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17482
22028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.1748222028
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.1331761713
Short name T631
Test name
Test status
Simulation time 871068146 ps
CPU time 64.45 seconds
Started Apr 21 04:18:50 PM PDT 24
Finished Apr 21 04:19:55 PM PDT 24
Peak memory 255108 kb
Host smart-aa3d176d-174c-4218-8344-e5ebfb677c5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13317
61713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.1331761713
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.2844674322
Short name T449
Test name
Test status
Simulation time 1845544581 ps
CPU time 32.6 seconds
Started Apr 21 04:18:53 PM PDT 24
Finished Apr 21 04:19:25 PM PDT 24
Peak memory 247708 kb
Host smart-ba8c642f-943e-4283-8d06-de2347ccd96d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28446
74322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.2844674322
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.1477437771
Short name T478
Test name
Test status
Simulation time 1193790296 ps
CPU time 26.57 seconds
Started Apr 21 04:18:48 PM PDT 24
Finished Apr 21 04:19:15 PM PDT 24
Peak memory 249032 kb
Host smart-737dd359-31ad-4d70-b756-846bb8e56187
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14774
37771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.1477437771
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.2696276338
Short name T26
Test name
Test status
Simulation time 44326130805 ps
CPU time 709.41 seconds
Started Apr 21 04:18:53 PM PDT 24
Finished Apr 21 04:30:43 PM PDT 24
Peak memory 257352 kb
Host smart-1cb60838-bd58-4fc1-85e2-9e6d0fa4129c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696276338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.2696276338
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.1288311858
Short name T287
Test name
Test status
Simulation time 56511698233 ps
CPU time 3587.04 seconds
Started Apr 21 04:18:58 PM PDT 24
Finished Apr 21 05:18:45 PM PDT 24
Peak memory 306020 kb
Host smart-950b1928-35f9-450e-942d-1e93841dce42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288311858 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.1288311858
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.2840448072
Short name T3
Test name
Test status
Simulation time 40405442 ps
CPU time 2.23 seconds
Started Apr 21 04:17:04 PM PDT 24
Finished Apr 21 04:17:06 PM PDT 24
Peak memory 249404 kb
Host smart-5b42d5e4-d165-4a97-bcb4-281e5ac5a74c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2840448072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.2840448072
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.1065861567
Short name T459
Test name
Test status
Simulation time 14385639445 ps
CPU time 1571.36 seconds
Started Apr 21 04:17:01 PM PDT 24
Finished Apr 21 04:43:12 PM PDT 24
Peak memory 289492 kb
Host smart-11d6f1ba-7841-4a02-b0c6-72e439826864
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065861567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.1065861567
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.1675350364
Short name T552
Test name
Test status
Simulation time 234951025 ps
CPU time 14.06 seconds
Started Apr 21 04:17:05 PM PDT 24
Finished Apr 21 04:17:19 PM PDT 24
Peak memory 249252 kb
Host smart-01225c50-54f5-44c0-9302-1e7e78bf28c9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1675350364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.1675350364
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.2945142840
Short name T657
Test name
Test status
Simulation time 4096770395 ps
CPU time 266.68 seconds
Started Apr 21 04:17:01 PM PDT 24
Finished Apr 21 04:21:28 PM PDT 24
Peak memory 256928 kb
Host smart-0fe58f97-1c65-4789-ab70-9b7f0561c38a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29451
42840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.2945142840
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.624475181
Short name T494
Test name
Test status
Simulation time 612811380 ps
CPU time 41.93 seconds
Started Apr 21 04:17:03 PM PDT 24
Finished Apr 21 04:17:45 PM PDT 24
Peak memory 255916 kb
Host smart-8973fb74-4c35-479f-8828-1942222d180a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62447
5181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.624475181
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.3002218031
Short name T323
Test name
Test status
Simulation time 67754448074 ps
CPU time 1265.69 seconds
Started Apr 21 04:16:59 PM PDT 24
Finished Apr 21 04:38:05 PM PDT 24
Peak memory 285872 kb
Host smart-cd569478-8b0f-4195-93df-53de9bcd6cca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002218031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.3002218031
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.3765610942
Short name T461
Test name
Test status
Simulation time 137964025469 ps
CPU time 2195.35 seconds
Started Apr 21 04:17:03 PM PDT 24
Finished Apr 21 04:53:39 PM PDT 24
Peak memory 268640 kb
Host smart-15e07144-c9e0-4c83-89f5-13dccc2cc2fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765610942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.3765610942
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.1361026350
Short name T291
Test name
Test status
Simulation time 27976974282 ps
CPU time 325.63 seconds
Started Apr 21 04:16:59 PM PDT 24
Finished Apr 21 04:22:25 PM PDT 24
Peak memory 248056 kb
Host smart-8955468e-5fe4-4a79-a7f5-dd9abe5468f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361026350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.1361026350
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.1262175090
Short name T225
Test name
Test status
Simulation time 659064835 ps
CPU time 12.6 seconds
Started Apr 21 04:17:02 PM PDT 24
Finished Apr 21 04:17:15 PM PDT 24
Peak memory 254448 kb
Host smart-230037f5-99a8-4922-a247-43aaf5c6c7d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12621
75090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.1262175090
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.1199467367
Short name T268
Test name
Test status
Simulation time 809112235 ps
CPU time 56.29 seconds
Started Apr 21 04:16:57 PM PDT 24
Finished Apr 21 04:17:53 PM PDT 24
Peak memory 255784 kb
Host smart-117916c8-6565-4a21-ab43-0ea7202c9187
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11994
67367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.1199467367
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.3698627792
Short name T12
Test name
Test status
Simulation time 2289724646 ps
CPU time 28.15 seconds
Started Apr 21 04:17:04 PM PDT 24
Finished Apr 21 04:17:33 PM PDT 24
Peak memory 271536 kb
Host smart-76813644-6534-45f0-9407-e542af547a92
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3698627792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.3698627792
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.3766636075
Short name T495
Test name
Test status
Simulation time 11697742676 ps
CPU time 33.41 seconds
Started Apr 21 04:16:56 PM PDT 24
Finished Apr 21 04:17:30 PM PDT 24
Peak memory 249236 kb
Host smart-a9cf49af-3cd8-44f6-9109-db693de6f2c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37666
36075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.3766636075
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.3892244673
Short name T493
Test name
Test status
Simulation time 22987707784 ps
CPU time 1308.3 seconds
Started Apr 21 04:17:02 PM PDT 24
Finished Apr 21 04:38:50 PM PDT 24
Peak memory 285960 kb
Host smart-837d7e52-ad23-4894-9f7a-aeaf3fb85c11
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892244673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.3892244673
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.1287736260
Short name T615
Test name
Test status
Simulation time 28402539407 ps
CPU time 1604.87 seconds
Started Apr 21 04:19:05 PM PDT 24
Finished Apr 21 04:45:50 PM PDT 24
Peak memory 289256 kb
Host smart-39ffa500-7a4e-4b87-9e97-11b5d06a5565
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287736260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.1287736260
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.1772791378
Short name T369
Test name
Test status
Simulation time 117893911 ps
CPU time 8.37 seconds
Started Apr 21 04:19:00 PM PDT 24
Finished Apr 21 04:19:09 PM PDT 24
Peak memory 251036 kb
Host smart-d74a3ae8-27b6-448e-9d11-ac747f88614a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17727
91378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.1772791378
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.3940179694
Short name T236
Test name
Test status
Simulation time 328846729 ps
CPU time 40.94 seconds
Started Apr 21 04:19:00 PM PDT 24
Finished Apr 21 04:19:41 PM PDT 24
Peak memory 255616 kb
Host smart-d86298aa-0b6e-4bc0-8465-b83876bca322
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39401
79694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.3940179694
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.2928990964
Short name T331
Test name
Test status
Simulation time 107552653502 ps
CPU time 3158.09 seconds
Started Apr 21 04:19:08 PM PDT 24
Finished Apr 21 05:11:47 PM PDT 24
Peak memory 289048 kb
Host smart-3f78115f-463d-43cf-8491-882d26d5ff76
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928990964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.2928990964
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.2236607787
Short name T67
Test name
Test status
Simulation time 191725355992 ps
CPU time 2325.12 seconds
Started Apr 21 04:19:03 PM PDT 24
Finished Apr 21 04:57:48 PM PDT 24
Peak memory 273360 kb
Host smart-5b42293a-d1cd-42c7-8d64-eef102a849ee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236607787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.2236607787
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.3539748235
Short name T565
Test name
Test status
Simulation time 8552120031 ps
CPU time 356.27 seconds
Started Apr 21 04:19:02 PM PDT 24
Finished Apr 21 04:24:59 PM PDT 24
Peak memory 248128 kb
Host smart-68cceb42-691a-4588-8c0a-1a958859040c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539748235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.3539748235
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.761906565
Short name T621
Test name
Test status
Simulation time 846897366 ps
CPU time 60.96 seconds
Started Apr 21 04:18:56 PM PDT 24
Finished Apr 21 04:19:57 PM PDT 24
Peak memory 257212 kb
Host smart-1529aea6-ffce-4151-b9b9-10456700aae3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76190
6565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.761906565
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.424774900
Short name T43
Test name
Test status
Simulation time 1199748967 ps
CPU time 78.81 seconds
Started Apr 21 04:19:00 PM PDT 24
Finished Apr 21 04:20:19 PM PDT 24
Peak memory 256288 kb
Host smart-564fdc8c-68f4-448d-8be3-c49a08ee968e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42477
4900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.424774900
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.390464635
Short name T24
Test name
Test status
Simulation time 2389715915 ps
CPU time 36.45 seconds
Started Apr 21 04:18:59 PM PDT 24
Finished Apr 21 04:19:35 PM PDT 24
Peak memory 248212 kb
Host smart-b4930d31-e5ff-42ff-a7d8-b9459a3fe668
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39046
4635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.390464635
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.652996137
Short name T77
Test name
Test status
Simulation time 200912697319 ps
CPU time 2975.5 seconds
Started Apr 21 04:19:06 PM PDT 24
Finished Apr 21 05:08:41 PM PDT 24
Peak memory 289524 kb
Host smart-fd8faae6-5a39-41b8-9b92-bc9277d695b2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652996137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_han
dler_stress_all.652996137
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.386884041
Short name T111
Test name
Test status
Simulation time 142040932228 ps
CPU time 989.05 seconds
Started Apr 21 04:19:05 PM PDT 24
Finished Apr 21 04:35:34 PM PDT 24
Peak memory 284084 kb
Host smart-a5eb988c-28bf-418d-a653-447f00eaa17a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386884041 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.386884041
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.441095854
Short name T601
Test name
Test status
Simulation time 7503395293 ps
CPU time 142.68 seconds
Started Apr 21 04:19:09 PM PDT 24
Finished Apr 21 04:21:32 PM PDT 24
Peak memory 257076 kb
Host smart-87041d03-2a50-4249-a3aa-0a1e5e48428b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44109
5854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.441095854
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.561077588
Short name T590
Test name
Test status
Simulation time 2703654244 ps
CPU time 28.88 seconds
Started Apr 21 04:19:07 PM PDT 24
Finished Apr 21 04:19:36 PM PDT 24
Peak memory 255804 kb
Host smart-0cdc8dc7-c600-4e13-ba1c-a0d722958034
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56107
7588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.561077588
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.3259449821
Short name T339
Test name
Test status
Simulation time 12747757374 ps
CPU time 1223.33 seconds
Started Apr 21 04:19:10 PM PDT 24
Finished Apr 21 04:39:34 PM PDT 24
Peak memory 271728 kb
Host smart-994ebc3e-81f0-402d-a4e8-a91f5aa3e078
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259449821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.3259449821
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.2870896122
Short name T453
Test name
Test status
Simulation time 23940681050 ps
CPU time 1409.57 seconds
Started Apr 21 04:19:10 PM PDT 24
Finished Apr 21 04:42:40 PM PDT 24
Peak memory 289572 kb
Host smart-e162571d-415b-4c5c-b105-1860a9952dec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870896122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.2870896122
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.3029327350
Short name T296
Test name
Test status
Simulation time 14943366321 ps
CPU time 304.3 seconds
Started Apr 21 04:19:10 PM PDT 24
Finished Apr 21 04:24:15 PM PDT 24
Peak memory 248116 kb
Host smart-eb410d1e-3996-45ab-a1fa-1e1be5faa4b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029327350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.3029327350
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.4048056018
Short name T623
Test name
Test status
Simulation time 28939841 ps
CPU time 5.56 seconds
Started Apr 21 04:19:07 PM PDT 24
Finished Apr 21 04:19:13 PM PDT 24
Peak memory 240868 kb
Host smart-86d41d7e-d9ba-4cf8-a151-cdf382a7b62c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40480
56018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.4048056018
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.3659330876
Short name T534
Test name
Test status
Simulation time 240649556 ps
CPU time 25.71 seconds
Started Apr 21 04:19:09 PM PDT 24
Finished Apr 21 04:19:35 PM PDT 24
Peak memory 247660 kb
Host smart-34b0e67b-a563-447a-949d-6288487c9040
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36593
30876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.3659330876
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.1236231570
Short name T632
Test name
Test status
Simulation time 1624528951 ps
CPU time 34.45 seconds
Started Apr 21 04:19:07 PM PDT 24
Finished Apr 21 04:19:41 PM PDT 24
Peak memory 255660 kb
Host smart-7bb84777-752c-493e-b691-6ba291db0e20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12362
31570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.1236231570
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.2514857562
Short name T36
Test name
Test status
Simulation time 5576625922 ps
CPU time 21.65 seconds
Started Apr 21 04:19:08 PM PDT 24
Finished Apr 21 04:19:30 PM PDT 24
Peak memory 249216 kb
Host smart-723d7b1c-6d1a-4ad8-ad9f-5672503292ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25148
57562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.2514857562
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.1736814309
Short name T110
Test name
Test status
Simulation time 56263015705 ps
CPU time 3053.18 seconds
Started Apr 21 04:19:10 PM PDT 24
Finished Apr 21 05:10:03 PM PDT 24
Peak memory 289676 kb
Host smart-1171b6cf-8147-4930-8342-2cb9eeb69840
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736814309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.1736814309
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.114286330
Short name T178
Test name
Test status
Simulation time 91139391580 ps
CPU time 1566.6 seconds
Started Apr 21 04:19:18 PM PDT 24
Finished Apr 21 04:45:25 PM PDT 24
Peak memory 273240 kb
Host smart-33945f4d-482d-47ee-892d-b2220ed94b80
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114286330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.114286330
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.2353879106
Short name T611
Test name
Test status
Simulation time 2172254134 ps
CPU time 138.51 seconds
Started Apr 21 04:19:16 PM PDT 24
Finished Apr 21 04:21:34 PM PDT 24
Peak memory 248552 kb
Host smart-c9c452f1-252b-43ca-8e2d-3bf053e684cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23538
79106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.2353879106
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.982886389
Short name T445
Test name
Test status
Simulation time 1331320019 ps
CPU time 85.88 seconds
Started Apr 21 04:19:17 PM PDT 24
Finished Apr 21 04:20:43 PM PDT 24
Peak memory 249108 kb
Host smart-ec4b1f4e-d0a1-4304-914b-74f25550d7e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98288
6389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.982886389
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.539438648
Short name T337
Test name
Test status
Simulation time 50703886558 ps
CPU time 1179.95 seconds
Started Apr 21 04:19:19 PM PDT 24
Finished Apr 21 04:39:00 PM PDT 24
Peak memory 289128 kb
Host smart-8b547781-b134-4ed4-9561-0c048116b21e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539438648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.539438648
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.4250816951
Short name T698
Test name
Test status
Simulation time 23539825109 ps
CPU time 1234.98 seconds
Started Apr 21 04:19:23 PM PDT 24
Finished Apr 21 04:39:58 PM PDT 24
Peak memory 266620 kb
Host smart-a5e9ff8c-acdd-4f2d-958e-2827242a6a03
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250816951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.4250816951
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.4123011020
Short name T307
Test name
Test status
Simulation time 38927987184 ps
CPU time 416.2 seconds
Started Apr 21 04:19:17 PM PDT 24
Finished Apr 21 04:26:14 PM PDT 24
Peak memory 256364 kb
Host smart-5b819472-76a1-48a4-8b7b-5e22ae48afd1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123011020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.4123011020
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.4000834296
Short name T589
Test name
Test status
Simulation time 2200202043 ps
CPU time 73.94 seconds
Started Apr 21 04:19:14 PM PDT 24
Finished Apr 21 04:20:28 PM PDT 24
Peak memory 255988 kb
Host smart-f9066d03-6ae6-4719-80f9-0979ddb978ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40008
34296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.4000834296
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.2909508315
Short name T577
Test name
Test status
Simulation time 740091810 ps
CPU time 16.61 seconds
Started Apr 21 04:19:16 PM PDT 24
Finished Apr 21 04:19:33 PM PDT 24
Peak memory 249036 kb
Host smart-84c60a70-a35d-4bdf-a384-913d9bf2dc9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29095
08315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.2909508315
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.1623026786
Short name T41
Test name
Test status
Simulation time 452241516 ps
CPU time 16.23 seconds
Started Apr 21 04:19:15 PM PDT 24
Finished Apr 21 04:19:32 PM PDT 24
Peak memory 255932 kb
Host smart-dd41ea5a-6b84-4cda-83f3-87baecb0bef9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16230
26786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.1623026786
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.4250533639
Short name T505
Test name
Test status
Simulation time 26549183 ps
CPU time 3.29 seconds
Started Apr 21 04:19:15 PM PDT 24
Finished Apr 21 04:19:18 PM PDT 24
Peak memory 240772 kb
Host smart-7d80901d-e895-403f-b8eb-effbaf3d54b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42505
33639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.4250533639
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.1999842212
Short name T709
Test name
Test status
Simulation time 6497200392 ps
CPU time 704.35 seconds
Started Apr 21 04:19:23 PM PDT 24
Finished Apr 21 04:31:08 PM PDT 24
Peak memory 270304 kb
Host smart-787992b2-4135-4ee1-81bb-d69f29959a0a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999842212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.1999842212
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.829947211
Short name T265
Test name
Test status
Simulation time 300427724973 ps
CPU time 5079.32 seconds
Started Apr 21 04:19:22 PM PDT 24
Finished Apr 21 05:44:02 PM PDT 24
Peak memory 321484 kb
Host smart-ae922e47-1c32-4297-9cf1-8b56cce02a3b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829947211 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.829947211
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.3426031230
Short name T401
Test name
Test status
Simulation time 257029393878 ps
CPU time 1479.34 seconds
Started Apr 21 04:19:22 PM PDT 24
Finished Apr 21 04:44:01 PM PDT 24
Peak memory 273460 kb
Host smart-dc548341-e854-4b41-80fc-fa76071d1f3f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426031230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.3426031230
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.2866486951
Short name T531
Test name
Test status
Simulation time 497854091 ps
CPU time 13.32 seconds
Started Apr 21 04:19:21 PM PDT 24
Finished Apr 21 04:19:35 PM PDT 24
Peak memory 256624 kb
Host smart-66d723da-1f7e-4cf2-8c74-4ccfbed05e33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28664
86951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.2866486951
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.1027135528
Short name T397
Test name
Test status
Simulation time 1298563423 ps
CPU time 43.41 seconds
Started Apr 21 04:19:23 PM PDT 24
Finished Apr 21 04:20:06 PM PDT 24
Peak memory 255760 kb
Host smart-9a7f7074-e989-4787-ada1-a715167d24c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10271
35528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.1027135528
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.4255077481
Short name T624
Test name
Test status
Simulation time 75900866369 ps
CPU time 2276.51 seconds
Started Apr 21 04:19:25 PM PDT 24
Finished Apr 21 04:57:22 PM PDT 24
Peak memory 273780 kb
Host smart-a85f8e35-73dc-402a-89d0-4a636c00f00f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255077481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.4255077481
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.2186742245
Short name T693
Test name
Test status
Simulation time 74337704067 ps
CPU time 1279.05 seconds
Started Apr 21 04:19:28 PM PDT 24
Finished Apr 21 04:40:47 PM PDT 24
Peak memory 273784 kb
Host smart-c45d99ef-0b36-415d-8ac9-28bb47b60844
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186742245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.2186742245
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.3131276575
Short name T673
Test name
Test status
Simulation time 55342089666 ps
CPU time 304.29 seconds
Started Apr 21 04:19:24 PM PDT 24
Finished Apr 21 04:24:29 PM PDT 24
Peak memory 248092 kb
Host smart-d49c655a-3802-4ddb-b4c2-dff8042f2037
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131276575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.3131276575
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.722148140
Short name T441
Test name
Test status
Simulation time 822298798 ps
CPU time 47.83 seconds
Started Apr 21 04:19:22 PM PDT 24
Finished Apr 21 04:20:10 PM PDT 24
Peak memory 249084 kb
Host smart-3b38ec03-2985-42d1-8fe1-96f3df944fbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72214
8140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.722148140
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.2693019543
Short name T418
Test name
Test status
Simulation time 966321490 ps
CPU time 67.72 seconds
Started Apr 21 04:19:22 PM PDT 24
Finished Apr 21 04:20:30 PM PDT 24
Peak memory 254524 kb
Host smart-2433f5d5-3c66-41e4-9331-02be467e8dc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26930
19543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.2693019543
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.3752937405
Short name T279
Test name
Test status
Simulation time 3747431036 ps
CPU time 53.55 seconds
Started Apr 21 04:19:24 PM PDT 24
Finished Apr 21 04:20:18 PM PDT 24
Peak memory 249576 kb
Host smart-87ef1dd2-ab20-4ee7-b56b-9efffc2bc244
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37529
37405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.3752937405
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.424452490
Short name T681
Test name
Test status
Simulation time 2585714999 ps
CPU time 42.45 seconds
Started Apr 21 04:19:23 PM PDT 24
Finished Apr 21 04:20:05 PM PDT 24
Peak memory 249436 kb
Host smart-fcb87564-9f3a-4a22-af63-a2a40ef158dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42445
2490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.424452490
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.2957236414
Short name T551
Test name
Test status
Simulation time 2303663934 ps
CPU time 39.67 seconds
Started Apr 21 04:19:27 PM PDT 24
Finished Apr 21 04:20:06 PM PDT 24
Peak memory 256516 kb
Host smart-09b7b4c1-26f5-427f-875c-cec5d18b91c1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957236414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.2957236414
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.3616802963
Short name T106
Test name
Test status
Simulation time 67669898639 ps
CPU time 586.64 seconds
Started Apr 21 04:19:34 PM PDT 24
Finished Apr 21 04:29:21 PM PDT 24
Peak memory 265584 kb
Host smart-c3b0fc62-6046-481a-a4a5-fc7a006e6e60
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616802963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.3616802963
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.2063241060
Short name T554
Test name
Test status
Simulation time 3223102370 ps
CPU time 172.07 seconds
Started Apr 21 04:19:30 PM PDT 24
Finished Apr 21 04:22:23 PM PDT 24
Peak memory 250484 kb
Host smart-dc1492fe-f6d7-4407-8f8f-0adf063d7a94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20632
41060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.2063241060
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.121548627
Short name T557
Test name
Test status
Simulation time 3490203727 ps
CPU time 48.64 seconds
Started Apr 21 04:19:30 PM PDT 24
Finished Apr 21 04:20:19 PM PDT 24
Peak memory 249548 kb
Host smart-85719edc-f2bf-4801-9557-a8033d4730d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12154
8627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.121548627
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.1116618060
Short name T103
Test name
Test status
Simulation time 128983318627 ps
CPU time 2020.08 seconds
Started Apr 21 04:19:35 PM PDT 24
Finished Apr 21 04:53:16 PM PDT 24
Peak memory 284964 kb
Host smart-03e7023c-da3e-4400-81e7-a7acff369002
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116618060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.1116618060
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.2760408875
Short name T317
Test name
Test status
Simulation time 37235665351 ps
CPU time 493.47 seconds
Started Apr 21 04:19:31 PM PDT 24
Finished Apr 21 04:27:45 PM PDT 24
Peak memory 248220 kb
Host smart-e3803cb1-744e-43af-9121-f6d531e81c73
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760408875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.2760408875
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.3155222171
Short name T73
Test name
Test status
Simulation time 363810372 ps
CPU time 12.13 seconds
Started Apr 21 04:19:29 PM PDT 24
Finished Apr 21 04:19:41 PM PDT 24
Peak memory 253388 kb
Host smart-e977352b-e14e-430c-addb-ebdccfb5eaf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31552
22171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.3155222171
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.29916334
Short name T497
Test name
Test status
Simulation time 298083371 ps
CPU time 32.23 seconds
Started Apr 21 04:19:30 PM PDT 24
Finished Apr 21 04:20:03 PM PDT 24
Peak memory 249448 kb
Host smart-47be69f8-ce52-40a0-a46a-001ee838adc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29916
334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.29916334
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.3557469822
Short name T654
Test name
Test status
Simulation time 298334235 ps
CPU time 15.86 seconds
Started Apr 21 04:19:31 PM PDT 24
Finished Apr 21 04:19:47 PM PDT 24
Peak memory 249516 kb
Host smart-ab5aa4ed-68de-4168-aa28-1e8c29dfb44e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35574
69822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.3557469822
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.2516281674
Short name T479
Test name
Test status
Simulation time 517670327 ps
CPU time 69.1 seconds
Started Apr 21 04:19:30 PM PDT 24
Finished Apr 21 04:20:40 PM PDT 24
Peak memory 249032 kb
Host smart-4760c6bb-d376-4eea-8380-a4b06bf09afb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25162
81674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.2516281674
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.375479867
Short name T588
Test name
Test status
Simulation time 121158820374 ps
CPU time 1290.34 seconds
Started Apr 21 04:19:35 PM PDT 24
Finished Apr 21 04:41:06 PM PDT 24
Peak memory 287260 kb
Host smart-fcffcb37-d804-4b8a-9975-caae7791db11
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375479867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_han
dler_stress_all.375479867
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.4061246603
Short name T560
Test name
Test status
Simulation time 66425469403 ps
CPU time 1951.82 seconds
Started Apr 21 04:19:40 PM PDT 24
Finished Apr 21 04:52:13 PM PDT 24
Peak memory 269816 kb
Host smart-fc120744-8b5d-44c3-86e7-d1382421549a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061246603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.4061246603
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.1795463840
Short name T428
Test name
Test status
Simulation time 8086867968 ps
CPU time 146.51 seconds
Started Apr 21 04:19:41 PM PDT 24
Finished Apr 21 04:22:08 PM PDT 24
Peak memory 256852 kb
Host smart-09b4ed47-08ab-4c77-83aa-1d69e30d63c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17954
63840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.1795463840
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.1264425346
Short name T607
Test name
Test status
Simulation time 1028511931 ps
CPU time 31.3 seconds
Started Apr 21 04:19:42 PM PDT 24
Finished Apr 21 04:20:14 PM PDT 24
Peak memory 255616 kb
Host smart-8ea2a3ac-217f-451d-b947-56685579b34f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12644
25346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.1264425346
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.1416553019
Short name T70
Test name
Test status
Simulation time 58767437932 ps
CPU time 1343.55 seconds
Started Apr 21 04:19:46 PM PDT 24
Finished Apr 21 04:42:10 PM PDT 24
Peak memory 281940 kb
Host smart-6ac26804-0d0d-49c4-96c7-51ce4f4e6876
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416553019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.1416553019
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.2514735586
Short name T234
Test name
Test status
Simulation time 47290880758 ps
CPU time 1503.95 seconds
Started Apr 21 04:19:42 PM PDT 24
Finished Apr 21 04:44:47 PM PDT 24
Peak memory 273600 kb
Host smart-cd4178e7-1eaa-469e-8672-0df85f75aaa6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514735586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.2514735586
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.512711439
Short name T690
Test name
Test status
Simulation time 3677422486 ps
CPU time 80.65 seconds
Started Apr 21 04:19:40 PM PDT 24
Finished Apr 21 04:21:01 PM PDT 24
Peak memory 248324 kb
Host smart-5bbacd8c-7fb2-485d-b76d-c005d36bbcdc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512711439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.512711439
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.3822793593
Short name T523
Test name
Test status
Simulation time 219536852 ps
CPU time 16.3 seconds
Started Apr 21 04:19:37 PM PDT 24
Finished Apr 21 04:19:54 PM PDT 24
Peak memory 247428 kb
Host smart-ce950826-8cf4-4735-813b-c5e1cdc38a69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38227
93593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.3822793593
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.941503417
Short name T458
Test name
Test status
Simulation time 424900557 ps
CPU time 20.99 seconds
Started Apr 21 04:19:40 PM PDT 24
Finished Apr 21 04:20:02 PM PDT 24
Peak memory 254688 kb
Host smart-786a55b3-e4bd-41c1-a019-d4f7228256f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94150
3417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.941503417
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.2889848489
Short name T688
Test name
Test status
Simulation time 265203404 ps
CPU time 23.25 seconds
Started Apr 21 04:19:38 PM PDT 24
Finished Apr 21 04:20:02 PM PDT 24
Peak memory 249068 kb
Host smart-a959e857-ceb7-4b2e-b7d7-124fece3c839
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28898
48489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.2889848489
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.3721405895
Short name T92
Test name
Test status
Simulation time 78829385637 ps
CPU time 2494.83 seconds
Started Apr 21 04:19:44 PM PDT 24
Finished Apr 21 05:01:20 PM PDT 24
Peak memory 284860 kb
Host smart-34676ad9-99b3-46cb-ada8-6ff4ec57772f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721405895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.3721405895
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.2617366919
Short name T639
Test name
Test status
Simulation time 30427711199 ps
CPU time 3508.15 seconds
Started Apr 21 04:19:44 PM PDT 24
Finished Apr 21 05:18:13 PM PDT 24
Peak memory 322708 kb
Host smart-f7499a85-83a7-4f85-9343-7f83655ee1c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617366919 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.2617366919
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.1681726313
Short name T671
Test name
Test status
Simulation time 16735054900 ps
CPU time 867.64 seconds
Started Apr 21 04:19:49 PM PDT 24
Finished Apr 21 04:34:17 PM PDT 24
Peak memory 267808 kb
Host smart-55d6f65d-faea-4499-8057-b90fecd68e33
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681726313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.1681726313
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.3923315046
Short name T66
Test name
Test status
Simulation time 1169953852 ps
CPU time 104.44 seconds
Started Apr 21 04:19:48 PM PDT 24
Finished Apr 21 04:21:32 PM PDT 24
Peak memory 257224 kb
Host smart-cda982cb-4886-4984-9c9a-e0940280f25a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39233
15046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.3923315046
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.2488729156
Short name T392
Test name
Test status
Simulation time 5134337581 ps
CPU time 57.33 seconds
Started Apr 21 04:19:47 PM PDT 24
Finished Apr 21 04:20:44 PM PDT 24
Peak memory 257052 kb
Host smart-930ad1ee-4b0c-4975-aef9-2a38d18880ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24887
29156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.2488729156
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.3014736760
Short name T344
Test name
Test status
Simulation time 482149016362 ps
CPU time 2131.91 seconds
Started Apr 21 04:19:57 PM PDT 24
Finished Apr 21 04:55:29 PM PDT 24
Peak memory 268712 kb
Host smart-515fbf91-3062-429b-aaa8-b4f4d9792f3e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014736760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.3014736760
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.3590471251
Short name T362
Test name
Test status
Simulation time 46283997197 ps
CPU time 1574.89 seconds
Started Apr 21 04:19:54 PM PDT 24
Finished Apr 21 04:46:09 PM PDT 24
Peak memory 267656 kb
Host smart-51d75df2-73c2-4bc8-8fbf-d6367432feba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590471251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.3590471251
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.1347808609
Short name T304
Test name
Test status
Simulation time 61473020207 ps
CPU time 503.05 seconds
Started Apr 21 04:19:52 PM PDT 24
Finished Apr 21 04:28:15 PM PDT 24
Peak memory 248504 kb
Host smart-c902228d-e582-45e1-b3ad-b2d31e8c07f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347808609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.1347808609
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.3904124583
Short name T366
Test name
Test status
Simulation time 185830112 ps
CPU time 11.92 seconds
Started Apr 21 04:19:47 PM PDT 24
Finished Apr 21 04:19:59 PM PDT 24
Peak memory 249068 kb
Host smart-c1dbcafb-4a3d-47b8-8faa-93388eda5e2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39041
24583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.3904124583
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.751879259
Short name T439
Test name
Test status
Simulation time 60717576 ps
CPU time 3.61 seconds
Started Apr 21 04:19:47 PM PDT 24
Finished Apr 21 04:19:51 PM PDT 24
Peak memory 239252 kb
Host smart-ac699c36-b54c-47e1-8e4e-e61aeff57ec6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75187
9259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.751879259
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.142849992
Short name T650
Test name
Test status
Simulation time 214236997 ps
CPU time 16.6 seconds
Started Apr 21 04:19:47 PM PDT 24
Finished Apr 21 04:20:04 PM PDT 24
Peak memory 249392 kb
Host smart-0044a979-ebb3-4e2b-8261-fb07b3051352
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14284
9992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.142849992
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.1925937422
Short name T182
Test name
Test status
Simulation time 1106334612 ps
CPU time 38.66 seconds
Started Apr 21 04:19:48 PM PDT 24
Finished Apr 21 04:20:27 PM PDT 24
Peak memory 256380 kb
Host smart-62cbb6e7-9bb6-47b7-bcba-67198c8b533d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19259
37422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.1925937422
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.2417457013
Short name T104
Test name
Test status
Simulation time 16342769141 ps
CPU time 1567.73 seconds
Started Apr 21 04:19:57 PM PDT 24
Finished Apr 21 04:46:05 PM PDT 24
Peak memory 289624 kb
Host smart-59907540-90d1-45c9-8e70-824aba001383
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417457013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.2417457013
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.2274747687
Short name T415
Test name
Test status
Simulation time 89877614363 ps
CPU time 4326.34 seconds
Started Apr 21 04:19:56 PM PDT 24
Finished Apr 21 05:32:03 PM PDT 24
Peak memory 338400 kb
Host smart-684951a6-f710-41bc-b485-a7725045797e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274747687 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.2274747687
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.2219701738
Short name T574
Test name
Test status
Simulation time 24454427442 ps
CPU time 1546.94 seconds
Started Apr 21 04:20:04 PM PDT 24
Finished Apr 21 04:45:52 PM PDT 24
Peak memory 289648 kb
Host smart-7b077ae0-a507-44a1-bd41-644ae80b084f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219701738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.2219701738
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.2570798120
Short name T38
Test name
Test status
Simulation time 8075985503 ps
CPU time 126.68 seconds
Started Apr 21 04:20:03 PM PDT 24
Finished Apr 21 04:22:10 PM PDT 24
Peak memory 257408 kb
Host smart-b795e6d9-dcc9-4573-b9d0-e63f03632046
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25707
98120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.2570798120
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.2615071179
Short name T573
Test name
Test status
Simulation time 1267588987 ps
CPU time 25 seconds
Started Apr 21 04:20:03 PM PDT 24
Finished Apr 21 04:20:28 PM PDT 24
Peak memory 248804 kb
Host smart-29bdc00f-729f-4739-8381-65a0321046c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26150
71179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.2615071179
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.2412176767
Short name T606
Test name
Test status
Simulation time 16848126550 ps
CPU time 1321.13 seconds
Started Apr 21 04:20:04 PM PDT 24
Finished Apr 21 04:42:05 PM PDT 24
Peak memory 289104 kb
Host smart-e7591346-2aee-4557-9d08-a3f315227fac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412176767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.2412176767
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.1908353353
Short name T484
Test name
Test status
Simulation time 92519475992 ps
CPU time 1656.51 seconds
Started Apr 21 04:20:09 PM PDT 24
Finished Apr 21 04:47:46 PM PDT 24
Peak memory 265648 kb
Host smart-61b4166a-7881-4784-969e-e40b3d9a16e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908353353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.1908353353
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.411071913
Short name T285
Test name
Test status
Simulation time 28112238799 ps
CPU time 572.35 seconds
Started Apr 21 04:20:05 PM PDT 24
Finished Apr 21 04:29:38 PM PDT 24
Peak memory 248052 kb
Host smart-a0d839c8-998b-4d1f-af45-434fda768b74
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411071913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.411071913
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.4290874873
Short name T678
Test name
Test status
Simulation time 119298800 ps
CPU time 16.13 seconds
Started Apr 21 04:20:03 PM PDT 24
Finished Apr 21 04:20:19 PM PDT 24
Peak memory 249020 kb
Host smart-39f642de-fe48-49b9-943e-95190c7b0b8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42908
74873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.4290874873
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.1082631777
Short name T99
Test name
Test status
Simulation time 1479896458 ps
CPU time 45.03 seconds
Started Apr 21 04:20:08 PM PDT 24
Finished Apr 21 04:20:53 PM PDT 24
Peak memory 256212 kb
Host smart-ce905b19-889a-4075-ba6b-2c595c6184f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10826
31777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.1082631777
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.3062298156
Short name T646
Test name
Test status
Simulation time 52018883 ps
CPU time 8.31 seconds
Started Apr 21 04:20:00 PM PDT 24
Finished Apr 21 04:20:09 PM PDT 24
Peak memory 249112 kb
Host smart-66f86e43-7d6c-4b03-9c1f-9324f5343792
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30622
98156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.3062298156
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.2418789877
Short name T501
Test name
Test status
Simulation time 52317781028 ps
CPU time 3030.27 seconds
Started Apr 21 04:20:06 PM PDT 24
Finished Apr 21 05:10:37 PM PDT 24
Peak memory 289980 kb
Host smart-f82fdc69-e9c0-42b7-92b4-102619d1e098
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418789877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.2418789877
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.3338073831
Short name T100
Test name
Test status
Simulation time 7087403588 ps
CPU time 746.37 seconds
Started Apr 21 04:20:12 PM PDT 24
Finished Apr 21 04:32:38 PM PDT 24
Peak memory 265728 kb
Host smart-20b8144c-205d-44cd-9936-860799e7b4ef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338073831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.3338073831
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.399639889
Short name T539
Test name
Test status
Simulation time 12471109014 ps
CPU time 132.17 seconds
Started Apr 21 04:20:07 PM PDT 24
Finished Apr 21 04:22:19 PM PDT 24
Peak memory 256980 kb
Host smart-6bc98f13-4076-4e10-ad2a-d159a6362234
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39963
9889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.399639889
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.2771566437
Short name T482
Test name
Test status
Simulation time 1398211470 ps
CPU time 26.05 seconds
Started Apr 21 04:20:08 PM PDT 24
Finished Apr 21 04:20:35 PM PDT 24
Peak memory 247904 kb
Host smart-7f9d9208-9ed5-482d-a3b1-765a60fb01b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27715
66437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.2771566437
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.457943206
Short name T4
Test name
Test status
Simulation time 17580626282 ps
CPU time 1002.05 seconds
Started Apr 21 04:20:11 PM PDT 24
Finished Apr 21 04:36:54 PM PDT 24
Peak memory 269672 kb
Host smart-b8a63d50-12d9-45bf-970d-47b6c7950800
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457943206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.457943206
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.3657367474
Short name T266
Test name
Test status
Simulation time 158757708217 ps
CPU time 2195.89 seconds
Started Apr 21 04:20:14 PM PDT 24
Finished Apr 21 04:56:50 PM PDT 24
Peak memory 283912 kb
Host smart-6c5b9fad-9f7b-4dea-98ef-17a568ee0fbe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657367474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.3657367474
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.606922767
Short name T216
Test name
Test status
Simulation time 12832861739 ps
CPU time 528.65 seconds
Started Apr 21 04:20:10 PM PDT 24
Finished Apr 21 04:28:59 PM PDT 24
Peak memory 247128 kb
Host smart-3614e86a-ff9f-47de-80c0-7375c5f77e13
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606922767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.606922767
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.2593827164
Short name T661
Test name
Test status
Simulation time 64989515 ps
CPU time 6.08 seconds
Started Apr 21 04:20:08 PM PDT 24
Finished Apr 21 04:20:14 PM PDT 24
Peak memory 240892 kb
Host smart-1621deae-9fd9-4b4b-ae27-b9bfc1d2af02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25938
27164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.2593827164
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.3104917862
Short name T98
Test name
Test status
Simulation time 956427816 ps
CPU time 57.19 seconds
Started Apr 21 04:20:08 PM PDT 24
Finished Apr 21 04:21:06 PM PDT 24
Peak memory 249088 kb
Host smart-688d4db8-3207-44cf-89b2-4a54613f72dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31049
17862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.3104917862
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.735815594
Short name T509
Test name
Test status
Simulation time 1951167153 ps
CPU time 26.44 seconds
Started Apr 21 04:20:10 PM PDT 24
Finished Apr 21 04:20:37 PM PDT 24
Peak memory 255752 kb
Host smart-7e2df3dd-7e7f-4bab-aaf5-0119dd3e358b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73581
5594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.735815594
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.2228663187
Short name T37
Test name
Test status
Simulation time 146666746 ps
CPU time 12.55 seconds
Started Apr 21 04:20:09 PM PDT 24
Finished Apr 21 04:20:22 PM PDT 24
Peak memory 257276 kb
Host smart-ba534843-1631-4385-82b9-857504d7aaa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22286
63187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.2228663187
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.234332958
Short name T105
Test name
Test status
Simulation time 188847273946 ps
CPU time 3083.43 seconds
Started Apr 21 04:20:14 PM PDT 24
Finished Apr 21 05:11:38 PM PDT 24
Peak memory 290244 kb
Host smart-cdb8c29b-0a5a-470a-bb73-0a0f9cb446db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234332958 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.234332958
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.542374637
Short name T622
Test name
Test status
Simulation time 143600410062 ps
CPU time 2197.5 seconds
Started Apr 21 04:20:21 PM PDT 24
Finished Apr 21 04:56:59 PM PDT 24
Peak memory 271196 kb
Host smart-9b8609ae-a0e7-4f30-bc1c-80dd9035f96c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542374637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.542374637
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.2117615638
Short name T89
Test name
Test status
Simulation time 2215334355 ps
CPU time 183.1 seconds
Started Apr 21 04:20:19 PM PDT 24
Finished Apr 21 04:23:23 PM PDT 24
Peak memory 251240 kb
Host smart-9551779b-9199-4e87-8cbb-6ddc93a4df5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21176
15638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.2117615638
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.2878224242
Short name T436
Test name
Test status
Simulation time 924085668 ps
CPU time 23.57 seconds
Started Apr 21 04:20:20 PM PDT 24
Finished Apr 21 04:20:44 PM PDT 24
Peak memory 254832 kb
Host smart-c73af2cb-1ac4-4c62-acd8-3ec61ce8a0d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28782
24242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.2878224242
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.2172179254
Short name T476
Test name
Test status
Simulation time 93264984791 ps
CPU time 1716.23 seconds
Started Apr 21 04:20:26 PM PDT 24
Finished Apr 21 04:49:03 PM PDT 24
Peak memory 273788 kb
Host smart-0f1e401d-e671-45b0-8fbb-8b43505d2d6f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172179254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.2172179254
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.3786209680
Short name T9
Test name
Test status
Simulation time 13580025439 ps
CPU time 388.81 seconds
Started Apr 21 04:20:24 PM PDT 24
Finished Apr 21 04:26:54 PM PDT 24
Peak memory 248092 kb
Host smart-33d1d1eb-ab93-4d9b-9d2e-12ed177abe8a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786209680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.3786209680
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.1608768007
Short name T507
Test name
Test status
Simulation time 1456204373 ps
CPU time 48.34 seconds
Started Apr 21 04:20:12 PM PDT 24
Finished Apr 21 04:21:01 PM PDT 24
Peak memory 249096 kb
Host smart-b1f2044f-1dfb-41ce-bdc2-4506de631d0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16087
68007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.1608768007
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.1815519960
Short name T674
Test name
Test status
Simulation time 262424059 ps
CPU time 24.09 seconds
Started Apr 21 04:20:15 PM PDT 24
Finished Apr 21 04:20:40 PM PDT 24
Peak memory 255080 kb
Host smart-9aeecdd6-8d36-45d3-afcc-95c2532f3b22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18155
19960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.1815519960
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.829505515
Short name T261
Test name
Test status
Simulation time 3059216225 ps
CPU time 56.28 seconds
Started Apr 21 04:20:20 PM PDT 24
Finished Apr 21 04:21:17 PM PDT 24
Peak memory 248136 kb
Host smart-d90a6db0-c391-440b-898d-1fb0b4901bf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82950
5515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.829505515
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.821671118
Short name T656
Test name
Test status
Simulation time 74884342 ps
CPU time 12.59 seconds
Started Apr 21 04:20:12 PM PDT 24
Finished Apr 21 04:20:25 PM PDT 24
Peak memory 255412 kb
Host smart-0a9da00e-22b3-4ad7-b867-4be146f03495
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82167
1118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.821671118
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.949013195
Short name T91
Test name
Test status
Simulation time 399396683819 ps
CPU time 3223.51 seconds
Started Apr 21 04:20:29 PM PDT 24
Finished Apr 21 05:14:13 PM PDT 24
Peak memory 314880 kb
Host smart-374beb35-2bea-4ae0-9218-d9f48c3361a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949013195 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.949013195
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.1114444667
Short name T102
Test name
Test status
Simulation time 66661838 ps
CPU time 2.77 seconds
Started Apr 21 04:17:13 PM PDT 24
Finished Apr 21 04:17:16 PM PDT 24
Peak memory 249320 kb
Host smart-6deaacce-1b55-4783-baeb-7a9334eaa200
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1114444667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.1114444667
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.1037587178
Short name T108
Test name
Test status
Simulation time 39434250509 ps
CPU time 659.84 seconds
Started Apr 21 04:17:07 PM PDT 24
Finished Apr 21 04:28:07 PM PDT 24
Peak memory 273136 kb
Host smart-f3fb1bc9-f8a3-4451-8f7f-33a67a83f600
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037587178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.1037587178
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.1071492701
Short name T438
Test name
Test status
Simulation time 3466042554 ps
CPU time 38 seconds
Started Apr 21 04:17:16 PM PDT 24
Finished Apr 21 04:17:54 PM PDT 24
Peak memory 240984 kb
Host smart-c0ee5653-2fcb-4b2c-b449-78eada9f6cb4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1071492701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.1071492701
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.674180387
Short name T500
Test name
Test status
Simulation time 2201555285 ps
CPU time 141.78 seconds
Started Apr 21 04:17:05 PM PDT 24
Finished Apr 21 04:19:27 PM PDT 24
Peak memory 249412 kb
Host smart-1d74e136-6ee9-4e5f-adcb-31ce79f32452
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67418
0387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.674180387
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.3173268245
Short name T359
Test name
Test status
Simulation time 2701960779 ps
CPU time 16.14 seconds
Started Apr 21 04:17:06 PM PDT 24
Finished Apr 21 04:17:22 PM PDT 24
Peak memory 253316 kb
Host smart-9af0245e-8f79-473d-aa9d-329b8e30fb87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31732
68245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.3173268245
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.3532422090
Short name T311
Test name
Test status
Simulation time 42571036717 ps
CPU time 459.92 seconds
Started Apr 21 04:17:04 PM PDT 24
Finished Apr 21 04:24:44 PM PDT 24
Peak memory 248008 kb
Host smart-57b908ed-9d76-4c92-8219-268e19c0bbb0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532422090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.3532422090
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.63569566
Short name T555
Test name
Test status
Simulation time 152419500 ps
CPU time 9.85 seconds
Started Apr 21 04:17:04 PM PDT 24
Finished Apr 21 04:17:14 PM PDT 24
Peak memory 249044 kb
Host smart-44763c51-10e7-487d-990b-7ca2c849cb58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63569
566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.63569566
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.4078221785
Short name T563
Test name
Test status
Simulation time 4745527026 ps
CPU time 79.08 seconds
Started Apr 21 04:17:05 PM PDT 24
Finished Apr 21 04:18:25 PM PDT 24
Peak memory 249068 kb
Host smart-feb8a223-c070-4cb8-b1d5-d97311bebfcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40782
21785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.4078221785
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.55233365
Short name T13
Test name
Test status
Simulation time 350564736 ps
CPU time 12.55 seconds
Started Apr 21 04:17:14 PM PDT 24
Finished Apr 21 04:17:27 PM PDT 24
Peak memory 270024 kb
Host smart-3f837ee5-ab68-4efd-8aa0-c1a8524da837
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=55233365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.55233365
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.455054328
Short name T263
Test name
Test status
Simulation time 1491412135 ps
CPU time 52.57 seconds
Started Apr 21 04:17:07 PM PDT 24
Finished Apr 21 04:18:00 PM PDT 24
Peak memory 255732 kb
Host smart-ac6d1c19-0002-468d-b6bc-99dc6b55a195
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45505
4328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.455054328
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.3800973575
Short name T468
Test name
Test status
Simulation time 42154745 ps
CPU time 6.54 seconds
Started Apr 21 04:17:04 PM PDT 24
Finished Apr 21 04:17:10 PM PDT 24
Peak memory 249040 kb
Host smart-b62f6e76-5210-4e0e-a79a-4d79b89059a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38009
73575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.3800973575
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.189400811
Short name T440
Test name
Test status
Simulation time 1447756912 ps
CPU time 145.84 seconds
Started Apr 21 04:17:12 PM PDT 24
Finished Apr 21 04:19:38 PM PDT 24
Peak memory 257160 kb
Host smart-0e23a89d-1512-4b92-ab3b-333b4acc4401
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189400811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_hand
ler_stress_all.189400811
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.1551979492
Short name T96
Test name
Test status
Simulation time 63767276132 ps
CPU time 1807.13 seconds
Started Apr 21 04:20:32 PM PDT 24
Finished Apr 21 04:50:40 PM PDT 24
Peak memory 282768 kb
Host smart-b1bfaade-2c77-439a-9820-aead884ba804
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551979492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.1551979492
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.1464566737
Short name T543
Test name
Test status
Simulation time 7953408219 ps
CPU time 221.4 seconds
Started Apr 21 04:20:32 PM PDT 24
Finished Apr 21 04:24:13 PM PDT 24
Peak memory 251616 kb
Host smart-6b8cde56-1159-48fb-998d-4e346a48ce03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14645
66737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.1464566737
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.3890296476
Short name T75
Test name
Test status
Simulation time 444737185 ps
CPU time 39.22 seconds
Started Apr 21 04:20:28 PM PDT 24
Finished Apr 21 04:21:08 PM PDT 24
Peak memory 255656 kb
Host smart-6ff769bc-4fe0-4e08-9d31-4b49b64d8ca1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38902
96476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.3890296476
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.1527835456
Short name T583
Test name
Test status
Simulation time 28208724694 ps
CPU time 1226.89 seconds
Started Apr 21 04:20:31 PM PDT 24
Finished Apr 21 04:40:58 PM PDT 24
Peak memory 273180 kb
Host smart-e5aa1efc-f6cf-4731-b65d-074f2021080c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527835456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.1527835456
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.413937261
Short name T372
Test name
Test status
Simulation time 17970696203 ps
CPU time 1233.51 seconds
Started Apr 21 04:20:35 PM PDT 24
Finished Apr 21 04:41:09 PM PDT 24
Peak memory 272992 kb
Host smart-9a6e3c97-19a2-4071-9e27-3ed12e60c3ab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413937261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.413937261
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.3087181392
Short name T544
Test name
Test status
Simulation time 44699329883 ps
CPU time 513.57 seconds
Started Apr 21 04:20:31 PM PDT 24
Finished Apr 21 04:29:05 PM PDT 24
Peak memory 248312 kb
Host smart-c2d3633b-dd2b-4d34-ad06-2549baf9d0c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087181392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.3087181392
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.2114396410
Short name T682
Test name
Test status
Simulation time 400925633 ps
CPU time 26.79 seconds
Started Apr 21 04:20:29 PM PDT 24
Finished Apr 21 04:20:56 PM PDT 24
Peak memory 249048 kb
Host smart-41ff7d40-9d72-45a4-a6e0-6d225da18349
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21143
96410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.2114396410
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.166810718
Short name T503
Test name
Test status
Simulation time 18207284375 ps
CPU time 67.29 seconds
Started Apr 21 04:20:28 PM PDT 24
Finished Apr 21 04:21:36 PM PDT 24
Peak memory 256916 kb
Host smart-c0156672-f1a9-4064-b80c-dab28c023c4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16681
0718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.166810718
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.396878507
Short name T183
Test name
Test status
Simulation time 97099952 ps
CPU time 8.83 seconds
Started Apr 21 04:20:28 PM PDT 24
Finished Apr 21 04:20:37 PM PDT 24
Peak memory 249084 kb
Host smart-15935a64-132b-4c9f-a994-c509eade0e06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39687
8507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.396878507
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.3530200987
Short name T30
Test name
Test status
Simulation time 14115203172 ps
CPU time 90.19 seconds
Started Apr 21 04:20:34 PM PDT 24
Finished Apr 21 04:22:04 PM PDT 24
Peak memory 256352 kb
Host smart-c858dcbd-a1c3-45c9-88d3-e4701a721a73
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530200987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.3530200987
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.2906137383
Short name T231
Test name
Test status
Simulation time 58182695097 ps
CPU time 1115.29 seconds
Started Apr 21 04:20:34 PM PDT 24
Finished Apr 21 04:39:10 PM PDT 24
Peak memory 273920 kb
Host smart-46b9529b-5fe9-4620-bd48-2786cb9a5023
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906137383 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.2906137383
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.1677387957
Short name T368
Test name
Test status
Simulation time 20378845962 ps
CPU time 864.2 seconds
Started Apr 21 04:20:39 PM PDT 24
Finished Apr 21 04:35:03 PM PDT 24
Peak memory 268648 kb
Host smart-013dc4f7-8a2b-41aa-9a39-60e748dfeb82
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677387957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.1677387957
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.1298116362
Short name T430
Test name
Test status
Simulation time 5211110499 ps
CPU time 141.1 seconds
Started Apr 21 04:20:36 PM PDT 24
Finished Apr 21 04:22:58 PM PDT 24
Peak memory 256932 kb
Host smart-ce7c1ed0-45ba-4dda-84be-278cfb6f110b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12981
16362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.1298116362
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.2013542888
Short name T365
Test name
Test status
Simulation time 1052757940 ps
CPU time 18.65 seconds
Started Apr 21 04:20:37 PM PDT 24
Finished Apr 21 04:20:56 PM PDT 24
Peak memory 249072 kb
Host smart-2983b532-9bfa-4620-a9b6-60f9b1818831
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20135
42888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.2013542888
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.3203274531
Short name T327
Test name
Test status
Simulation time 9839747540 ps
CPU time 898.45 seconds
Started Apr 21 04:20:43 PM PDT 24
Finished Apr 21 04:35:42 PM PDT 24
Peak memory 265600 kb
Host smart-187c181a-6460-4162-bca3-5fe1d544fb66
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203274531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.3203274531
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.1890823422
Short name T6
Test name
Test status
Simulation time 33890559340 ps
CPU time 2459.96 seconds
Started Apr 21 04:20:45 PM PDT 24
Finished Apr 21 05:01:46 PM PDT 24
Peak memory 281960 kb
Host smart-6891cc59-217e-46bc-bd88-24f3ae80cf4f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890823422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.1890823422
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.954995608
Short name T471
Test name
Test status
Simulation time 3071585195 ps
CPU time 135.05 seconds
Started Apr 21 04:20:39 PM PDT 24
Finished Apr 21 04:22:55 PM PDT 24
Peak memory 254632 kb
Host smart-d9ad5c6d-e097-42a0-823b-83656bdf8d79
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954995608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.954995608
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.3048119138
Short name T386
Test name
Test status
Simulation time 739375584 ps
CPU time 22.91 seconds
Started Apr 21 04:20:36 PM PDT 24
Finished Apr 21 04:20:59 PM PDT 24
Peak memory 249112 kb
Host smart-0c7c1176-7a2a-480c-a956-b61a83de2d15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30481
19138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.3048119138
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.1008311199
Short name T422
Test name
Test status
Simulation time 23607901 ps
CPU time 4.73 seconds
Started Apr 21 04:20:36 PM PDT 24
Finished Apr 21 04:20:41 PM PDT 24
Peak memory 239436 kb
Host smart-f2a30159-acef-4633-8d40-c610412bfc98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10083
11199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.1008311199
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.3606957836
Short name T642
Test name
Test status
Simulation time 1726147463 ps
CPU time 33.93 seconds
Started Apr 21 04:20:36 PM PDT 24
Finished Apr 21 04:21:11 PM PDT 24
Peak memory 247400 kb
Host smart-81bf2e57-dd60-4870-bec0-7979c4001429
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36069
57836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.3606957836
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.222030162
Short name T502
Test name
Test status
Simulation time 115064986 ps
CPU time 10.12 seconds
Started Apr 21 04:20:33 PM PDT 24
Finished Apr 21 04:20:43 PM PDT 24
Peak memory 255124 kb
Host smart-b09b042c-6c8c-4368-a8b4-3e1f9a0d31c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22203
0162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.222030162
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.1297425073
Short name T628
Test name
Test status
Simulation time 378247039957 ps
CPU time 1231.72 seconds
Started Apr 21 04:20:45 PM PDT 24
Finished Apr 21 04:41:18 PM PDT 24
Peak memory 272924 kb
Host smart-b7f9a3d5-6c86-4e3d-9cfb-6b1aafe5f818
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297425073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.1297425073
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.2841827973
Short name T442
Test name
Test status
Simulation time 17889866669 ps
CPU time 1219.01 seconds
Started Apr 21 04:20:53 PM PDT 24
Finished Apr 21 04:41:13 PM PDT 24
Peak memory 273696 kb
Host smart-88d56e8d-2e04-4a65-81c3-c732512b75da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841827973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.2841827973
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.681486471
Short name T537
Test name
Test status
Simulation time 18766300723 ps
CPU time 129.24 seconds
Started Apr 21 04:20:50 PM PDT 24
Finished Apr 21 04:23:00 PM PDT 24
Peak memory 250212 kb
Host smart-c3ed33b6-4b65-45a8-a30d-fddd821d9fe3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68148
6471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.681486471
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.2007079678
Short name T510
Test name
Test status
Simulation time 4222356098 ps
CPU time 34.27 seconds
Started Apr 21 04:20:50 PM PDT 24
Finished Apr 21 04:21:24 PM PDT 24
Peak memory 255944 kb
Host smart-8d05c0c2-2465-4dca-889a-1344be372b4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20070
79678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.2007079678
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.2274398734
Short name T325
Test name
Test status
Simulation time 22615518325 ps
CPU time 1249.16 seconds
Started Apr 21 04:20:55 PM PDT 24
Finished Apr 21 04:41:44 PM PDT 24
Peak memory 267624 kb
Host smart-598c6d23-7b81-463d-a188-d7dd857ef7f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274398734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.2274398734
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.2485982150
Short name T664
Test name
Test status
Simulation time 399678062991 ps
CPU time 3239.21 seconds
Started Apr 21 04:21:00 PM PDT 24
Finished Apr 21 05:14:59 PM PDT 24
Peak memory 290104 kb
Host smart-ef0ba8de-ec19-46b2-979b-eee387e2c579
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485982150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.2485982150
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.4241131330
Short name T685
Test name
Test status
Simulation time 13958481656 ps
CPU time 631.15 seconds
Started Apr 21 04:20:53 PM PDT 24
Finished Apr 21 04:31:25 PM PDT 24
Peak memory 248284 kb
Host smart-d480cc2c-dc96-4795-9a5d-1b50f266986e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241131330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.4241131330
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.1896873302
Short name T63
Test name
Test status
Simulation time 714956555 ps
CPU time 44.34 seconds
Started Apr 21 04:20:51 PM PDT 24
Finished Apr 21 04:21:36 PM PDT 24
Peak memory 257228 kb
Host smart-a1244279-0753-4213-8fe2-6cebd5b35c63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18968
73302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.1896873302
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.172498796
Short name T112
Test name
Test status
Simulation time 143262547 ps
CPU time 9.01 seconds
Started Apr 21 04:20:51 PM PDT 24
Finished Apr 21 04:21:00 PM PDT 24
Peak memory 251836 kb
Host smart-75c4bc16-88b4-4a14-823c-dad76a9597ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17249
8796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.172498796
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.4126172351
Short name T638
Test name
Test status
Simulation time 519865425 ps
CPU time 21.44 seconds
Started Apr 21 04:20:54 PM PDT 24
Finished Apr 21 04:21:15 PM PDT 24
Peak memory 254436 kb
Host smart-0309a404-fc2d-4fa3-bda8-d9b36c0ac7fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41261
72351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.4126172351
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.4033527256
Short name T406
Test name
Test status
Simulation time 3406711376 ps
CPU time 62.86 seconds
Started Apr 21 04:20:51 PM PDT 24
Finished Apr 21 04:21:54 PM PDT 24
Peak memory 249180 kb
Host smart-e5cfd4de-d992-4fe7-9851-000a2d022a9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40335
27256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.4033527256
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.887293902
Short name T604
Test name
Test status
Simulation time 79009497642 ps
CPU time 2585.07 seconds
Started Apr 21 04:20:58 PM PDT 24
Finished Apr 21 05:04:04 PM PDT 24
Peak memory 289804 kb
Host smart-459036f4-7adf-4b14-9991-b6d66ff5933a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887293902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_han
dler_stress_all.887293902
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.4083152256
Short name T475
Test name
Test status
Simulation time 60486265489 ps
CPU time 5172.09 seconds
Started Apr 21 04:21:00 PM PDT 24
Finished Apr 21 05:47:13 PM PDT 24
Peak memory 305908 kb
Host smart-2f448049-2bc0-438c-98ae-1511cbe37676
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083152256 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.4083152256
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.899695537
Short name T527
Test name
Test status
Simulation time 132325011817 ps
CPU time 2189.2 seconds
Started Apr 21 04:21:08 PM PDT 24
Finished Apr 21 04:57:38 PM PDT 24
Peak memory 273028 kb
Host smart-d371dce4-89cc-4bce-a7c4-d3068b692096
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899695537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.899695537
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.451018793
Short name T603
Test name
Test status
Simulation time 44211578738 ps
CPU time 230.75 seconds
Started Apr 21 04:21:03 PM PDT 24
Finished Apr 21 04:24:54 PM PDT 24
Peak memory 250868 kb
Host smart-ac5af206-1a8e-4dc4-ac59-e331013d9185
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45101
8793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.451018793
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.671389091
Short name T644
Test name
Test status
Simulation time 4440978057 ps
CPU time 62.44 seconds
Started Apr 21 04:21:05 PM PDT 24
Finished Apr 21 04:22:08 PM PDT 24
Peak memory 255932 kb
Host smart-2d2888e2-dc19-4776-8c3d-25883a5e8088
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67138
9091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.671389091
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.4133414237
Short name T340
Test name
Test status
Simulation time 133059326411 ps
CPU time 2175.5 seconds
Started Apr 21 04:21:08 PM PDT 24
Finished Apr 21 04:57:24 PM PDT 24
Peak memory 273796 kb
Host smart-2a7b39b6-ba00-41a7-9a38-c0121621f83b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133414237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.4133414237
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.3961126182
Short name T286
Test name
Test status
Simulation time 109689725299 ps
CPU time 2808.2 seconds
Started Apr 21 04:21:11 PM PDT 24
Finished Apr 21 05:08:00 PM PDT 24
Peak memory 289688 kb
Host smart-4ded4d69-f56c-465c-9153-ba0e98577f82
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961126182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.3961126182
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.566395755
Short name T395
Test name
Test status
Simulation time 5090143927 ps
CPU time 77.13 seconds
Started Apr 21 04:21:00 PM PDT 24
Finished Apr 21 04:22:17 PM PDT 24
Peak memory 249196 kb
Host smart-464c10d6-2a06-4e61-b796-d45e24067559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56639
5755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.566395755
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.2635713662
Short name T529
Test name
Test status
Simulation time 269503803 ps
CPU time 4.57 seconds
Started Apr 21 04:21:00 PM PDT 24
Finished Apr 21 04:21:04 PM PDT 24
Peak memory 239252 kb
Host smart-b819a536-fd68-44df-8178-96d2b566d99f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26357
13662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.2635713662
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.4054597050
Short name T614
Test name
Test status
Simulation time 57378311 ps
CPU time 5.76 seconds
Started Apr 21 04:21:06 PM PDT 24
Finished Apr 21 04:21:12 PM PDT 24
Peak memory 239424 kb
Host smart-3bc2b829-4874-4f0a-8d63-1c04b5e07c01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40545
97050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.4054597050
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.2877546488
Short name T221
Test name
Test status
Simulation time 258179023 ps
CPU time 16.56 seconds
Started Apr 21 04:20:58 PM PDT 24
Finished Apr 21 04:21:15 PM PDT 24
Peak memory 254860 kb
Host smart-d5bc03f8-e673-4e2e-929b-699ae20d09c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28775
46488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.2877546488
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.1529569373
Short name T662
Test name
Test status
Simulation time 41542373386 ps
CPU time 1528.89 seconds
Started Apr 21 04:21:14 PM PDT 24
Finished Apr 21 04:46:43 PM PDT 24
Peak memory 289596 kb
Host smart-2e6f2ce9-f6f9-402e-9ee4-c29243da162e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529569373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.1529569373
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.2898753316
Short name T444
Test name
Test status
Simulation time 4361516912 ps
CPU time 249.11 seconds
Started Apr 21 04:21:15 PM PDT 24
Finished Apr 21 04:25:24 PM PDT 24
Peak memory 257320 kb
Host smart-03fb2c5a-770d-45a4-ac83-120c1fd65255
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28987
53316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.2898753316
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.1874159606
Short name T410
Test name
Test status
Simulation time 4526122201 ps
CPU time 69.95 seconds
Started Apr 21 04:21:12 PM PDT 24
Finished Apr 21 04:22:23 PM PDT 24
Peak memory 249108 kb
Host smart-23b342c7-054c-4d7a-9909-cbd65b1d8419
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18741
59606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.1874159606
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.2218789247
Short name T328
Test name
Test status
Simulation time 19246824852 ps
CPU time 1147.32 seconds
Started Apr 21 04:21:13 PM PDT 24
Finished Apr 21 04:40:21 PM PDT 24
Peak memory 273140 kb
Host smart-658a7e8b-799d-4428-b7f0-acb8afcaa610
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218789247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.2218789247
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.1991125985
Short name T375
Test name
Test status
Simulation time 166578465299 ps
CPU time 1795.98 seconds
Started Apr 21 04:21:15 PM PDT 24
Finished Apr 21 04:51:11 PM PDT 24
Peak memory 289744 kb
Host smart-569d5c5e-2c00-44a0-8c50-7ef85690e838
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991125985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.1991125985
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.577936146
Short name T647
Test name
Test status
Simulation time 411328630 ps
CPU time 16.99 seconds
Started Apr 21 04:21:10 PM PDT 24
Finished Apr 21 04:21:28 PM PDT 24
Peak memory 249032 kb
Host smart-947c520d-8a3a-47ee-b308-ce96e88236e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57793
6146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.577936146
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.118200210
Short name T114
Test name
Test status
Simulation time 747997778 ps
CPU time 23.86 seconds
Started Apr 21 04:21:12 PM PDT 24
Finished Apr 21 04:21:36 PM PDT 24
Peak memory 255480 kb
Host smart-a81253ac-49be-4564-94fb-9f59fcd9299c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11820
0210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.118200210
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.3182065978
Short name T243
Test name
Test status
Simulation time 111722058 ps
CPU time 17.15 seconds
Started Apr 21 04:21:13 PM PDT 24
Finished Apr 21 04:21:31 PM PDT 24
Peak memory 247620 kb
Host smart-4e7edda7-8eaf-4eb4-8166-0f71cd1644ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31820
65978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.3182065978
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.437737921
Short name T383
Test name
Test status
Simulation time 1303843124 ps
CPU time 25.96 seconds
Started Apr 21 04:21:13 PM PDT 24
Finished Apr 21 04:21:39 PM PDT 24
Peak memory 249252 kb
Host smart-a420eddc-ea98-4afa-a5bb-a08b433aa89b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43773
7921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.437737921
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.3892148332
Short name T19
Test name
Test status
Simulation time 132363964142 ps
CPU time 1620.99 seconds
Started Apr 21 04:21:20 PM PDT 24
Finished Apr 21 04:48:22 PM PDT 24
Peak memory 283500 kb
Host smart-3ca3ef1c-4851-4fd7-9c7a-aeb97a6e4d30
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892148332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.3892148332
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.138348876
Short name T593
Test name
Test status
Simulation time 204738524405 ps
CPU time 2699.8 seconds
Started Apr 21 04:21:27 PM PDT 24
Finished Apr 21 05:06:28 PM PDT 24
Peak memory 281968 kb
Host smart-52e9899e-2a5b-499a-b71c-7fb4d74e2902
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138348876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.138348876
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.2053748647
Short name T412
Test name
Test status
Simulation time 365182195 ps
CPU time 19.97 seconds
Started Apr 21 04:21:27 PM PDT 24
Finished Apr 21 04:21:47 PM PDT 24
Peak memory 248740 kb
Host smart-55dd5cc8-30e0-417a-94f3-5b2bf5afb96c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20537
48647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.2053748647
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.1799991429
Short name T113
Test name
Test status
Simulation time 367740604 ps
CPU time 22.62 seconds
Started Apr 21 04:21:25 PM PDT 24
Finished Apr 21 04:21:48 PM PDT 24
Peak memory 248960 kb
Host smart-e1fa9572-0da4-4fe5-9683-4b928afe4ec4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17999
91429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.1799991429
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.3407496835
Short name T549
Test name
Test status
Simulation time 66021383780 ps
CPU time 1282.33 seconds
Started Apr 21 04:21:32 PM PDT 24
Finished Apr 21 04:42:55 PM PDT 24
Peak memory 289500 kb
Host smart-ef6cde20-7ccb-4c8d-968b-315e76c83469
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407496835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.3407496835
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.862347102
Short name T281
Test name
Test status
Simulation time 39676304387 ps
CPU time 1646.31 seconds
Started Apr 21 04:21:32 PM PDT 24
Finished Apr 21 04:48:59 PM PDT 24
Peak memory 290144 kb
Host smart-ef9a69dd-26c5-4110-988b-22a6f217b15f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862347102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.862347102
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.3844749470
Short name T309
Test name
Test status
Simulation time 6097041625 ps
CPU time 261.93 seconds
Started Apr 21 04:21:28 PM PDT 24
Finished Apr 21 04:25:50 PM PDT 24
Peak memory 248472 kb
Host smart-1c71ec7b-53fc-40d3-9dd6-fb4bac12bd80
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844749470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.3844749470
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.1814748859
Short name T541
Test name
Test status
Simulation time 70553563 ps
CPU time 9.45 seconds
Started Apr 21 04:21:25 PM PDT 24
Finished Apr 21 04:21:34 PM PDT 24
Peak memory 257232 kb
Host smart-f17eb7c8-c6f2-4937-a055-27e4bb916959
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18147
48859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.1814748859
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.4024399766
Short name T571
Test name
Test status
Simulation time 522644428 ps
CPU time 12.68 seconds
Started Apr 21 04:21:24 PM PDT 24
Finished Apr 21 04:21:37 PM PDT 24
Peak memory 254016 kb
Host smart-1b89851a-2986-4745-858a-7fd797e572e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40243
99766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.4024399766
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.570051233
Short name T649
Test name
Test status
Simulation time 62928105 ps
CPU time 9.01 seconds
Started Apr 21 04:21:27 PM PDT 24
Finished Apr 21 04:21:36 PM PDT 24
Peak memory 247552 kb
Host smart-5f5eeaa8-e1cd-4730-a1b4-27cf6e1ac20b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57005
1233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.570051233
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.2397495600
Short name T598
Test name
Test status
Simulation time 1862163111 ps
CPU time 53.56 seconds
Started Apr 21 04:21:25 PM PDT 24
Finished Apr 21 04:22:19 PM PDT 24
Peak memory 249072 kb
Host smart-041db97f-4787-48bd-8a79-d7c72e4f8664
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23974
95600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.2397495600
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.3900352234
Short name T288
Test name
Test status
Simulation time 69103090374 ps
CPU time 4036.61 seconds
Started Apr 21 04:21:33 PM PDT 24
Finished Apr 21 05:28:50 PM PDT 24
Peak memory 299732 kb
Host smart-6d512281-99b0-4d42-a5fb-fbeeb3a9b91b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900352234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.3900352234
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.2055382925
Short name T490
Test name
Test status
Simulation time 8570796663 ps
CPU time 1059.77 seconds
Started Apr 21 04:21:39 PM PDT 24
Finished Apr 21 04:39:19 PM PDT 24
Peak memory 273932 kb
Host smart-9bc3af2b-50b9-44ff-9a1c-7c44facbffdd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055382925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.2055382925
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.3866975954
Short name T115
Test name
Test status
Simulation time 1655963308 ps
CPU time 94.23 seconds
Started Apr 21 04:21:34 PM PDT 24
Finished Apr 21 04:23:08 PM PDT 24
Peak memory 249112 kb
Host smart-55f972e5-5139-48d2-bdee-1cec0fadb8b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38669
75954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.3866975954
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.697704553
Short name T389
Test name
Test status
Simulation time 592085775 ps
CPU time 41.98 seconds
Started Apr 21 04:21:33 PM PDT 24
Finished Apr 21 04:22:15 PM PDT 24
Peak memory 255108 kb
Host smart-46fc3e39-8b8e-4ff3-a30b-768f85d7e457
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69770
4553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.697704553
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.3915931110
Short name T655
Test name
Test status
Simulation time 25150146322 ps
CPU time 1536.1 seconds
Started Apr 21 04:21:35 PM PDT 24
Finished Apr 21 04:47:12 PM PDT 24
Peak memory 271744 kb
Host smart-4dbfb243-7dd6-49b5-b14e-8539b781a4dd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915931110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.3915931110
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.3893664214
Short name T17
Test name
Test status
Simulation time 49567682099 ps
CPU time 1574.67 seconds
Started Apr 21 04:21:37 PM PDT 24
Finished Apr 21 04:47:52 PM PDT 24
Peak memory 265580 kb
Host smart-46c51c92-1c9a-4e5b-b730-11cd28b50ee8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893664214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.3893664214
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.337083962
Short name T316
Test name
Test status
Simulation time 13620152477 ps
CPU time 205.37 seconds
Started Apr 21 04:21:35 PM PDT 24
Finished Apr 21 04:25:00 PM PDT 24
Peak memory 248076 kb
Host smart-cd379b47-ee7b-41a9-a250-10179485ec68
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337083962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.337083962
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.824414513
Short name T694
Test name
Test status
Simulation time 917150215 ps
CPU time 20.42 seconds
Started Apr 21 04:21:33 PM PDT 24
Finished Apr 21 04:21:54 PM PDT 24
Peak memory 249088 kb
Host smart-42be4ef4-de0e-46af-acb0-b7b1434aa41e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82441
4513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.824414513
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.4236707870
Short name T520
Test name
Test status
Simulation time 585925551 ps
CPU time 42.69 seconds
Started Apr 21 04:21:32 PM PDT 24
Finished Apr 21 04:22:15 PM PDT 24
Peak memory 247596 kb
Host smart-49c73b5c-a04b-472b-afcc-007e324de7ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42367
07870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.4236707870
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.210570113
Short name T262
Test name
Test status
Simulation time 57910699 ps
CPU time 5.42 seconds
Started Apr 21 04:21:39 PM PDT 24
Finished Apr 21 04:21:44 PM PDT 24
Peak memory 251740 kb
Host smart-afc29d88-340e-4b5b-989d-6a443b2bc9a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21057
0113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.210570113
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.2258531788
Short name T504
Test name
Test status
Simulation time 1092976847 ps
CPU time 68.43 seconds
Started Apr 21 04:21:34 PM PDT 24
Finished Apr 21 04:22:42 PM PDT 24
Peak memory 256216 kb
Host smart-d0630dc6-ecdf-4b7f-9dea-ae4b898a4dc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22585
31788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.2258531788
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.548577711
Short name T76
Test name
Test status
Simulation time 5561951732 ps
CPU time 274.37 seconds
Started Apr 21 04:21:40 PM PDT 24
Finished Apr 21 04:26:14 PM PDT 24
Peak memory 257388 kb
Host smart-75ed5521-cea2-4ca2-820c-26fef06a977e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548577711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_han
dler_stress_all.548577711
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.3756544536
Short name T226
Test name
Test status
Simulation time 104586471239 ps
CPU time 1907.69 seconds
Started Apr 21 04:21:54 PM PDT 24
Finished Apr 21 04:53:42 PM PDT 24
Peak memory 273304 kb
Host smart-898027c4-fea4-4bf2-b393-0fa6b02b8d2a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756544536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.3756544536
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.1600583867
Short name T474
Test name
Test status
Simulation time 519019294 ps
CPU time 32.5 seconds
Started Apr 21 04:21:49 PM PDT 24
Finished Apr 21 04:22:21 PM PDT 24
Peak memory 249500 kb
Host smart-a5604e89-394d-4c5e-b50b-5ae59f0296b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16005
83867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.1600583867
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.2646985353
Short name T473
Test name
Test status
Simulation time 1242217952 ps
CPU time 37.48 seconds
Started Apr 21 04:21:46 PM PDT 24
Finished Apr 21 04:22:23 PM PDT 24
Peak memory 249124 kb
Host smart-b722563f-a295-4a70-9367-4c213cba0f82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26469
85353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.2646985353
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.1816276905
Short name T648
Test name
Test status
Simulation time 72800589375 ps
CPU time 1729.98 seconds
Started Apr 21 04:22:00 PM PDT 24
Finished Apr 21 04:50:50 PM PDT 24
Peak memory 289236 kb
Host smart-db671deb-9803-4d70-91a7-c8a2cb14f7f9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816276905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.1816276905
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.1507710976
Short name T512
Test name
Test status
Simulation time 150629004181 ps
CPU time 2390.96 seconds
Started Apr 21 04:22:00 PM PDT 24
Finished Apr 21 05:01:51 PM PDT 24
Peak memory 289960 kb
Host smart-147013e2-ba68-4d41-80d7-470f5a1cd5ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507710976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.1507710976
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.1076226124
Short name T704
Test name
Test status
Simulation time 60019278656 ps
CPU time 684.54 seconds
Started Apr 21 04:21:56 PM PDT 24
Finished Apr 21 04:33:21 PM PDT 24
Peak memory 248504 kb
Host smart-fbb487bf-2287-4f39-a861-33a11dd33e81
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076226124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.1076226124
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.3948421996
Short name T692
Test name
Test status
Simulation time 3414345645 ps
CPU time 47 seconds
Started Apr 21 04:21:46 PM PDT 24
Finished Apr 21 04:22:33 PM PDT 24
Peak memory 249208 kb
Host smart-bf561c44-38e7-41c6-aca0-7658a05c33c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39484
21996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.3948421996
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.3338331654
Short name T599
Test name
Test status
Simulation time 358571553 ps
CPU time 23.89 seconds
Started Apr 21 04:21:47 PM PDT 24
Finished Apr 21 04:22:11 PM PDT 24
Peak memory 249092 kb
Host smart-e8aa7c60-06c6-4c5b-824d-c92999640482
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33383
31654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.3338331654
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.3282008505
Short name T81
Test name
Test status
Simulation time 347067845 ps
CPU time 15.47 seconds
Started Apr 21 04:21:52 PM PDT 24
Finished Apr 21 04:22:08 PM PDT 24
Peak memory 252668 kb
Host smart-f9ea8150-0ca0-4a3e-860d-77e298b6ee72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32820
08505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.3282008505
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.1242204446
Short name T363
Test name
Test status
Simulation time 776941130 ps
CPU time 44.23 seconds
Started Apr 21 04:21:44 PM PDT 24
Finished Apr 21 04:22:28 PM PDT 24
Peak memory 249276 kb
Host smart-73ff24eb-9646-47af-828b-9a777678a8d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12422
04446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.1242204446
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.2055671506
Short name T666
Test name
Test status
Simulation time 39463242369 ps
CPU time 385.1 seconds
Started Apr 21 04:22:00 PM PDT 24
Finished Apr 21 04:28:25 PM PDT 24
Peak memory 257388 kb
Host smart-092ea2df-d639-4bee-b850-9da31187bcae
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055671506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.2055671506
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.788097601
Short name T515
Test name
Test status
Simulation time 33478682548 ps
CPU time 2983.82 seconds
Started Apr 21 04:22:03 PM PDT 24
Finished Apr 21 05:11:47 PM PDT 24
Peak memory 322472 kb
Host smart-4cf7a108-d8d1-4665-af9d-92f167f409c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788097601 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.788097601
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.2654991672
Short name T564
Test name
Test status
Simulation time 67749389326 ps
CPU time 2561.1 seconds
Started Apr 21 04:22:07 PM PDT 24
Finished Apr 21 05:04:49 PM PDT 24
Peak memory 289432 kb
Host smart-f3036f07-daae-494f-a157-2b1bf8bb2104
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654991672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.2654991672
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.2331937105
Short name T465
Test name
Test status
Simulation time 652494432 ps
CPU time 23.5 seconds
Started Apr 21 04:22:05 PM PDT 24
Finished Apr 21 04:22:29 PM PDT 24
Peak memory 249104 kb
Host smart-f76dd4a0-b5cf-4b61-acd6-4204bfbd618d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23319
37105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.2331937105
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.320178988
Short name T322
Test name
Test status
Simulation time 32551066863 ps
CPU time 793.62 seconds
Started Apr 21 04:22:09 PM PDT 24
Finished Apr 21 04:35:23 PM PDT 24
Peak memory 265760 kb
Host smart-8495b11d-ff2f-441b-8782-775ce9e05942
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320178988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.320178988
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.383534614
Short name T547
Test name
Test status
Simulation time 115628314598 ps
CPU time 1852.49 seconds
Started Apr 21 04:22:08 PM PDT 24
Finished Apr 21 04:53:01 PM PDT 24
Peak memory 273208 kb
Host smart-612ef807-88a9-4053-a20a-d9c7a3623519
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383534614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.383534614
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.1434381664
Short name T643
Test name
Test status
Simulation time 1985322007 ps
CPU time 85.45 seconds
Started Apr 21 04:22:08 PM PDT 24
Finished Apr 21 04:23:34 PM PDT 24
Peak memory 248092 kb
Host smart-e8e71db6-2ddf-4674-84fb-a1758509abe8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434381664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.1434381664
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.2548742767
Short name T399
Test name
Test status
Simulation time 193924146 ps
CPU time 18.54 seconds
Started Apr 21 04:22:03 PM PDT 24
Finished Apr 21 04:22:22 PM PDT 24
Peak memory 249088 kb
Host smart-6c17efd6-40a1-4fea-b25e-bf60d374f9ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25487
42767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.2548742767
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.3786372045
Short name T620
Test name
Test status
Simulation time 619382277 ps
CPU time 40.67 seconds
Started Apr 21 04:22:02 PM PDT 24
Finished Apr 21 04:22:43 PM PDT 24
Peak memory 255652 kb
Host smart-c47fa9e7-288f-4b04-9a23-49f6a9f5512c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37863
72045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.3786372045
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.1207066549
Short name T595
Test name
Test status
Simulation time 4384382399 ps
CPU time 40.38 seconds
Started Apr 21 04:22:08 PM PDT 24
Finished Apr 21 04:22:49 PM PDT 24
Peak memory 249236 kb
Host smart-bb520a1e-e2ae-40fc-9773-4d1d24c835bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12070
66549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.1207066549
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.3961892920
Short name T78
Test name
Test status
Simulation time 231233112 ps
CPU time 19.9 seconds
Started Apr 21 04:22:04 PM PDT 24
Finished Apr 21 04:22:24 PM PDT 24
Peak memory 249268 kb
Host smart-422ec9cc-87c8-403f-a206-bf709e9ceca1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39618
92920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.3961892920
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.3858873006
Short name T253
Test name
Test status
Simulation time 715913340 ps
CPU time 30.83 seconds
Started Apr 21 04:22:07 PM PDT 24
Finished Apr 21 04:22:38 PM PDT 24
Peak memory 249052 kb
Host smart-d8433036-542c-42a7-9c1f-7ba213007753
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858873006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.3858873006
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.2346090038
Short name T561
Test name
Test status
Simulation time 62815396073 ps
CPU time 856.24 seconds
Started Apr 21 04:22:20 PM PDT 24
Finished Apr 21 04:36:37 PM PDT 24
Peak memory 272268 kb
Host smart-7df77e84-0928-4bd6-a3fb-ea5f4ab93cc5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346090038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.2346090038
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.2227068453
Short name T427
Test name
Test status
Simulation time 1456259543 ps
CPU time 138.03 seconds
Started Apr 21 04:22:18 PM PDT 24
Finished Apr 21 04:24:37 PM PDT 24
Peak memory 250760 kb
Host smart-8f1a2042-8488-40cb-b7bb-db0bb6f3447f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22270
68453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.2227068453
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.418460831
Short name T433
Test name
Test status
Simulation time 537395976 ps
CPU time 40.23 seconds
Started Apr 21 04:22:17 PM PDT 24
Finished Apr 21 04:22:57 PM PDT 24
Peak memory 255392 kb
Host smart-693817ad-59f3-4089-820a-452055ea58f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41846
0831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.418460831
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.677637808
Short name T663
Test name
Test status
Simulation time 99378948839 ps
CPU time 2794.49 seconds
Started Apr 21 04:22:24 PM PDT 24
Finished Apr 21 05:08:59 PM PDT 24
Peak memory 289988 kb
Host smart-5f3ecde6-4109-4bb3-a12f-955263ac4bb1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677637808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.677637808
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.924586727
Short name T677
Test name
Test status
Simulation time 8704871689 ps
CPU time 896.18 seconds
Started Apr 21 04:22:29 PM PDT 24
Finished Apr 21 04:37:26 PM PDT 24
Peak memory 273760 kb
Host smart-4942ecc8-fad5-43d0-8cdc-239edbc2c6b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924586727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.924586727
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.1926143595
Short name T517
Test name
Test status
Simulation time 10884714590 ps
CPU time 111.99 seconds
Started Apr 21 04:22:26 PM PDT 24
Finished Apr 21 04:24:18 PM PDT 24
Peak memory 252664 kb
Host smart-8a2aa5b6-4609-4905-91fc-792f64032a40
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926143595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.1926143595
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.3507864987
Short name T665
Test name
Test status
Simulation time 784568954 ps
CPU time 24.75 seconds
Started Apr 21 04:22:16 PM PDT 24
Finished Apr 21 04:22:41 PM PDT 24
Peak memory 249032 kb
Host smart-9605b403-44d1-4440-aaef-330842bb54b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35078
64987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.3507864987
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.1521209551
Short name T508
Test name
Test status
Simulation time 44940846 ps
CPU time 6.64 seconds
Started Apr 21 04:22:16 PM PDT 24
Finished Apr 21 04:22:23 PM PDT 24
Peak memory 247576 kb
Host smart-12513102-b14f-4974-9bb7-b6330d81b6e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15212
09551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.1521209551
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.102423422
Short name T255
Test name
Test status
Simulation time 65339185 ps
CPU time 8.91 seconds
Started Apr 21 04:22:20 PM PDT 24
Finished Apr 21 04:22:29 PM PDT 24
Peak memory 252040 kb
Host smart-826adc35-deba-41bb-a058-669629c3f3ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10242
3422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.102423422
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.4002482858
Short name T411
Test name
Test status
Simulation time 371381559 ps
CPU time 33.81 seconds
Started Apr 21 04:22:10 PM PDT 24
Finished Apr 21 04:22:44 PM PDT 24
Peak memory 249092 kb
Host smart-7187c94c-db60-49be-8f51-469b8ae4b81f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40024
82858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.4002482858
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.637787478
Short name T206
Test name
Test status
Simulation time 14610169 ps
CPU time 2.43 seconds
Started Apr 21 04:17:12 PM PDT 24
Finished Apr 21 04:17:14 PM PDT 24
Peak memory 249368 kb
Host smart-27148cf3-f55f-46f1-ac4d-0f62e7eb986a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=637787478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.637787478
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.2319103451
Short name T670
Test name
Test status
Simulation time 10811029132 ps
CPU time 627.28 seconds
Started Apr 21 04:17:11 PM PDT 24
Finished Apr 21 04:27:39 PM PDT 24
Peak memory 265616 kb
Host smart-6669c84d-0de4-47a0-a75d-efb1d7b6df4c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319103451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.2319103451
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.1562333572
Short name T435
Test name
Test status
Simulation time 3761527601 ps
CPU time 22.9 seconds
Started Apr 21 04:17:12 PM PDT 24
Finished Apr 21 04:17:35 PM PDT 24
Peak memory 241012 kb
Host smart-eb4f2145-e295-41be-b354-39956a7de270
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1562333572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.1562333572
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.1363120241
Short name T446
Test name
Test status
Simulation time 5217016340 ps
CPU time 109.53 seconds
Started Apr 21 04:17:11 PM PDT 24
Finished Apr 21 04:19:01 PM PDT 24
Peak memory 250172 kb
Host smart-67a0d05a-0dbe-4bc9-af86-701ddcb79a3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13631
20241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.1363120241
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.1491938230
Short name T696
Test name
Test status
Simulation time 3856824606 ps
CPU time 54.47 seconds
Started Apr 21 04:17:11 PM PDT 24
Finished Apr 21 04:18:06 PM PDT 24
Peak memory 249180 kb
Host smart-5ac8a85d-a014-4fb8-aa42-454e1132623f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14919
38230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.1491938230
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.1366358286
Short name T338
Test name
Test status
Simulation time 217978706527 ps
CPU time 2823.81 seconds
Started Apr 21 04:17:11 PM PDT 24
Finished Apr 21 05:04:15 PM PDT 24
Peak memory 289232 kb
Host smart-74973749-d27e-41e9-9e0f-2689b59533c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366358286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.1366358286
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.2065699799
Short name T630
Test name
Test status
Simulation time 77825908712 ps
CPU time 2430.66 seconds
Started Apr 21 04:17:12 PM PDT 24
Finished Apr 21 04:57:43 PM PDT 24
Peak memory 282640 kb
Host smart-7c88ded0-6aa1-4aee-88f2-91e1a80710cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065699799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.2065699799
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.513980015
Short name T295
Test name
Test status
Simulation time 10184524995 ps
CPU time 405.38 seconds
Started Apr 21 04:17:12 PM PDT 24
Finished Apr 21 04:23:58 PM PDT 24
Peak memory 248264 kb
Host smart-d54ffbb8-1137-4d74-ba18-9dd457e41398
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513980015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.513980015
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.3485498958
Short name T417
Test name
Test status
Simulation time 1321607870 ps
CPU time 13.53 seconds
Started Apr 21 04:17:12 PM PDT 24
Finished Apr 21 04:17:26 PM PDT 24
Peak memory 253332 kb
Host smart-7f71d24a-ae8e-4d01-936c-d3376f95ec88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34854
98958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.3485498958
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.3193207104
Short name T652
Test name
Test status
Simulation time 98089616 ps
CPU time 7.57 seconds
Started Apr 21 04:17:13 PM PDT 24
Finished Apr 21 04:17:21 PM PDT 24
Peak memory 249072 kb
Host smart-0ce37c91-5dbb-457d-8bff-4a21fb86a7cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31932
07104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.3193207104
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.1676945396
Short name T483
Test name
Test status
Simulation time 81973345 ps
CPU time 3.54 seconds
Started Apr 21 04:17:11 PM PDT 24
Finished Apr 21 04:17:15 PM PDT 24
Peak memory 239236 kb
Host smart-5658f34d-297f-453f-bf3e-c67074d44371
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16769
45396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.1676945396
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.3617721194
Short name T385
Test name
Test status
Simulation time 656415757 ps
CPU time 45.69 seconds
Started Apr 21 04:17:13 PM PDT 24
Finished Apr 21 04:17:59 PM PDT 24
Peak memory 256044 kb
Host smart-5fe0ef29-36f1-42a9-9041-85db00b270f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36177
21194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.3617721194
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.1554388784
Short name T57
Test name
Test status
Simulation time 11377356690 ps
CPU time 1124.6 seconds
Started Apr 21 04:17:15 PM PDT 24
Finished Apr 21 04:36:00 PM PDT 24
Peak memory 288472 kb
Host smart-f57ed5cb-f16a-4c2b-a6a3-54ab5971ceb8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554388784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.1554388784
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.124912012
Short name T61
Test name
Test status
Simulation time 255971694290 ps
CPU time 4715.64 seconds
Started Apr 21 04:17:16 PM PDT 24
Finished Apr 21 05:35:52 PM PDT 24
Peak memory 314848 kb
Host smart-c64c3459-0059-46b7-a94b-a1ab4b79f176
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124912012 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.124912012
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.1112580220
Short name T259
Test name
Test status
Simulation time 32652819865 ps
CPU time 1908.95 seconds
Started Apr 21 04:22:47 PM PDT 24
Finished Apr 21 04:54:36 PM PDT 24
Peak memory 269648 kb
Host smart-e75c3690-96c9-4d8e-b56c-7be4d7a3b388
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112580220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.1112580220
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.2654044289
Short name T101
Test name
Test status
Simulation time 3480542157 ps
CPU time 172.98 seconds
Started Apr 21 04:22:43 PM PDT 24
Finished Apr 21 04:25:36 PM PDT 24
Peak memory 257152 kb
Host smart-a4524b33-9024-4c32-8b36-df117dc94275
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26540
44289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.2654044289
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.12932280
Short name T370
Test name
Test status
Simulation time 358349251 ps
CPU time 15.57 seconds
Started Apr 21 04:22:41 PM PDT 24
Finished Apr 21 04:22:57 PM PDT 24
Peak memory 252132 kb
Host smart-9ce01c97-6571-4eaf-b18a-af577cce1784
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12932
280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.12932280
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.3188272832
Short name T463
Test name
Test status
Simulation time 9661258709 ps
CPU time 1051.41 seconds
Started Apr 21 04:22:46 PM PDT 24
Finished Apr 21 04:40:18 PM PDT 24
Peak memory 290120 kb
Host smart-681c32a2-0dbb-479c-8741-2bd07d04a407
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188272832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.3188272832
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.2897520935
Short name T686
Test name
Test status
Simulation time 21855129938 ps
CPU time 241.56 seconds
Started Apr 21 04:22:47 PM PDT 24
Finished Apr 21 04:26:49 PM PDT 24
Peak memory 249132 kb
Host smart-34bc43d1-d3ff-419f-9920-02284e9bb78a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897520935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.2897520935
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.1487817940
Short name T65
Test name
Test status
Simulation time 96662271 ps
CPU time 8.69 seconds
Started Apr 21 04:22:40 PM PDT 24
Finished Apr 21 04:22:49 PM PDT 24
Peak memory 249088 kb
Host smart-6e9eb1d0-b7f9-4065-910f-5ab053ee34cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14878
17940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.1487817940
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.3723263265
Short name T679
Test name
Test status
Simulation time 914502431 ps
CPU time 17.73 seconds
Started Apr 21 04:22:42 PM PDT 24
Finished Apr 21 04:22:59 PM PDT 24
Peak memory 249032 kb
Host smart-b23c8850-7293-4822-914f-25fa2fa6995d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37232
63265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.3723263265
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.352787723
Short name T700
Test name
Test status
Simulation time 512043989 ps
CPU time 33.04 seconds
Started Apr 21 04:22:45 PM PDT 24
Finished Apr 21 04:23:19 PM PDT 24
Peak memory 247572 kb
Host smart-c6024b45-45ae-4bbc-9659-fc1e522b4c27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35278
7723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.352787723
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.2718013028
Short name T506
Test name
Test status
Simulation time 741101291 ps
CPU time 44.12 seconds
Started Apr 21 04:22:41 PM PDT 24
Finished Apr 21 04:23:25 PM PDT 24
Peak memory 249280 kb
Host smart-0731a6a5-d473-4dd2-9950-bc2ec664af61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27180
13028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.2718013028
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.580717044
Short name T619
Test name
Test status
Simulation time 12537532223 ps
CPU time 516.79 seconds
Started Apr 21 04:22:51 PM PDT 24
Finished Apr 21 04:31:28 PM PDT 24
Peak memory 254256 kb
Host smart-946f2ff2-51cd-46d6-92ab-bef25df72254
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580717044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_han
dler_stress_all.580717044
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.327985025
Short name T701
Test name
Test status
Simulation time 44330552819 ps
CPU time 1892.21 seconds
Started Apr 21 04:22:56 PM PDT 24
Finished Apr 21 04:54:28 PM PDT 24
Peak memory 268684 kb
Host smart-7e02c901-ccb5-4ecc-8cd1-6d8066159170
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327985025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.327985025
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.4009633796
Short name T633
Test name
Test status
Simulation time 5574065399 ps
CPU time 49.46 seconds
Started Apr 21 04:22:52 PM PDT 24
Finished Apr 21 04:23:42 PM PDT 24
Peak memory 249268 kb
Host smart-566c67be-481c-4184-ae91-e56d45db9a52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40096
33796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.4009633796
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.2522392370
Short name T592
Test name
Test status
Simulation time 640720855 ps
CPU time 33.36 seconds
Started Apr 21 04:22:53 PM PDT 24
Finished Apr 21 04:23:26 PM PDT 24
Peak memory 255636 kb
Host smart-00b9ca28-799c-45ab-a3b4-e3c889f90755
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25223
92370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.2522392370
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.2780873527
Short name T290
Test name
Test status
Simulation time 63501195737 ps
CPU time 1173.57 seconds
Started Apr 21 04:22:55 PM PDT 24
Finished Apr 21 04:42:28 PM PDT 24
Peak memory 272920 kb
Host smart-8142e7cd-ed8a-4170-80f2-5ccb4d9f9dbf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780873527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.2780873527
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.553966657
Short name T380
Test name
Test status
Simulation time 177380082229 ps
CPU time 2625.75 seconds
Started Apr 21 04:22:54 PM PDT 24
Finished Apr 21 05:06:40 PM PDT 24
Peak memory 290124 kb
Host smart-823536d4-6ebe-4884-b13b-4e55ca93bb30
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553966657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.553966657
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.3489292642
Short name T306
Test name
Test status
Simulation time 47774505522 ps
CPU time 373.86 seconds
Started Apr 21 04:22:55 PM PDT 24
Finished Apr 21 04:29:09 PM PDT 24
Peak memory 248608 kb
Host smart-a11c2d69-8203-489a-99ce-db711a919b02
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489292642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.3489292642
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.2025823752
Short name T456
Test name
Test status
Simulation time 820012507 ps
CPU time 7.04 seconds
Started Apr 21 04:22:49 PM PDT 24
Finished Apr 21 04:22:56 PM PDT 24
Peak memory 249088 kb
Host smart-d0988708-62fb-4099-95a1-d7ca24bc8ca3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20258
23752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.2025823752
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.1274352143
Short name T672
Test name
Test status
Simulation time 76241681 ps
CPU time 9.71 seconds
Started Apr 21 04:22:51 PM PDT 24
Finished Apr 21 04:23:00 PM PDT 24
Peak memory 252376 kb
Host smart-1cca4207-4cb4-4eef-93f2-2ec0bde3ff77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12743
52143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.1274352143
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.3954341235
Short name T634
Test name
Test status
Simulation time 907361945 ps
CPU time 61.89 seconds
Started Apr 21 04:22:51 PM PDT 24
Finished Apr 21 04:23:53 PM PDT 24
Peak memory 255768 kb
Host smart-fd75af54-840a-495d-825a-72e432094633
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39543
41235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.3954341235
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.1415792890
Short name T358
Test name
Test status
Simulation time 264415520 ps
CPU time 28.39 seconds
Started Apr 21 04:22:48 PM PDT 24
Finished Apr 21 04:23:17 PM PDT 24
Peak memory 256272 kb
Host smart-f2840f49-9917-4ad7-be14-dbac2aa4dd32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14157
92890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.1415792890
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.3060938308
Short name T414
Test name
Test status
Simulation time 84263433054 ps
CPU time 1495.63 seconds
Started Apr 21 04:23:03 PM PDT 24
Finished Apr 21 04:47:59 PM PDT 24
Peak memory 273388 kb
Host smart-3df8c458-571f-4344-a392-f94ae6b22ce5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060938308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.3060938308
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.3392799032
Short name T239
Test name
Test status
Simulation time 7360093008 ps
CPU time 46.74 seconds
Started Apr 21 04:23:00 PM PDT 24
Finished Apr 21 04:23:47 PM PDT 24
Peak memory 256584 kb
Host smart-b987a5cd-b988-44d0-9805-b4fa2951fa38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33927
99032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.3392799032
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.1575057530
Short name T699
Test name
Test status
Simulation time 2002465400 ps
CPU time 32.95 seconds
Started Apr 21 04:23:00 PM PDT 24
Finished Apr 21 04:23:33 PM PDT 24
Peak memory 255624 kb
Host smart-1c889fcb-c4c4-414c-940f-3fc9eb98a41a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15750
57530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.1575057530
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.755476277
Short name T402
Test name
Test status
Simulation time 69232593767 ps
CPU time 1210.04 seconds
Started Apr 21 04:23:07 PM PDT 24
Finished Apr 21 04:43:18 PM PDT 24
Peak memory 282804 kb
Host smart-e5434062-6a42-43be-9fe2-76de8bb2fe50
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755476277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.755476277
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.3822163761
Short name T378
Test name
Test status
Simulation time 2329495056 ps
CPU time 33.05 seconds
Started Apr 21 04:23:00 PM PDT 24
Finished Apr 21 04:23:33 PM PDT 24
Peak memory 249140 kb
Host smart-9187786b-82eb-467a-8d69-3f8c106c448a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38221
63761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.3822163761
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.2948546293
Short name T56
Test name
Test status
Simulation time 874160885 ps
CPU time 49.43 seconds
Started Apr 21 04:22:58 PM PDT 24
Finished Apr 21 04:23:47 PM PDT 24
Peak memory 249064 kb
Host smart-ccbbbe03-9342-4aa1-8d67-577e5049427b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29485
46293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.2948546293
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.2219564228
Short name T605
Test name
Test status
Simulation time 1246217140 ps
CPU time 27.31 seconds
Started Apr 21 04:22:59 PM PDT 24
Finished Apr 21 04:23:27 PM PDT 24
Peak memory 256312 kb
Host smart-088d2a70-d10f-4a2e-9b46-f0e64a8f472a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22195
64228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.2219564228
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.1925698757
Short name T462
Test name
Test status
Simulation time 2407864825 ps
CPU time 41.09 seconds
Started Apr 21 04:22:56 PM PDT 24
Finished Apr 21 04:23:38 PM PDT 24
Peak memory 256872 kb
Host smart-e04bc000-a308-4c59-b86f-5483d22762ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19256
98757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.1925698757
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.3053742263
Short name T514
Test name
Test status
Simulation time 162815495586 ps
CPU time 6110.42 seconds
Started Apr 21 04:23:10 PM PDT 24
Finished Apr 21 06:05:01 PM PDT 24
Peak memory 370800 kb
Host smart-c9170c4b-193c-44b3-80f4-e4ee74d9c8c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053742263 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.3053742263
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.376789404
Short name T659
Test name
Test status
Simulation time 42866668252 ps
CPU time 2484.14 seconds
Started Apr 21 04:23:16 PM PDT 24
Finished Apr 21 05:04:40 PM PDT 24
Peak memory 281976 kb
Host smart-8115aa90-2bcb-4a05-8ffd-c1851ba87c9a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376789404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.376789404
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.3729420334
Short name T668
Test name
Test status
Simulation time 18894791464 ps
CPU time 271.04 seconds
Started Apr 21 04:23:13 PM PDT 24
Finished Apr 21 04:27:45 PM PDT 24
Peak memory 250676 kb
Host smart-160b5748-ca1c-4467-9fcf-31c0a80d6fa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37294
20334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.3729420334
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.1399656109
Short name T423
Test name
Test status
Simulation time 1330505697 ps
CPU time 13.52 seconds
Started Apr 21 04:23:13 PM PDT 24
Finished Apr 21 04:23:27 PM PDT 24
Peak memory 251836 kb
Host smart-00f22b6c-307e-4eef-a0b5-7d983134e664
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13996
56109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.1399656109
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.590277315
Short name T591
Test name
Test status
Simulation time 35578711828 ps
CPU time 2068.29 seconds
Started Apr 21 04:23:21 PM PDT 24
Finished Apr 21 04:57:49 PM PDT 24
Peak memory 273236 kb
Host smart-ce23ecb2-92a0-46d7-af38-1a7d06138079
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590277315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.590277315
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.3620303515
Short name T319
Test name
Test status
Simulation time 45087842338 ps
CPU time 489.07 seconds
Started Apr 21 04:23:16 PM PDT 24
Finished Apr 21 04:31:25 PM PDT 24
Peak memory 248068 kb
Host smart-73e92159-a71b-414a-9e90-12bd3398a008
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620303515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.3620303515
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.3013104543
Short name T379
Test name
Test status
Simulation time 262143745 ps
CPU time 22.94 seconds
Started Apr 21 04:23:12 PM PDT 24
Finished Apr 21 04:23:35 PM PDT 24
Peak memory 249088 kb
Host smart-6949ae1b-fb28-41af-9e4b-41378fd23204
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30131
04543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.3013104543
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.1398447125
Short name T388
Test name
Test status
Simulation time 1826553320 ps
CPU time 38.2 seconds
Started Apr 21 04:23:14 PM PDT 24
Finished Apr 21 04:23:52 PM PDT 24
Peak memory 249072 kb
Host smart-d0274c8f-512e-4510-9626-8c1496f2b348
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13984
47125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.1398447125
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.1007888362
Short name T248
Test name
Test status
Simulation time 2251443756 ps
CPU time 39.07 seconds
Started Apr 21 04:23:16 PM PDT 24
Finished Apr 21 04:23:56 PM PDT 24
Peak memory 248144 kb
Host smart-f2de2c7c-a2ac-4544-9394-fad8bbeaf474
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10078
88362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.1007888362
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.1627428580
Short name T87
Test name
Test status
Simulation time 168453944 ps
CPU time 19.6 seconds
Started Apr 21 04:23:10 PM PDT 24
Finished Apr 21 04:23:30 PM PDT 24
Peak memory 249180 kb
Host smart-003a459a-bd97-4cfa-b579-b63b490b8cd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16274
28580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.1627428580
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.2883230751
Short name T85
Test name
Test status
Simulation time 312064022 ps
CPU time 30.58 seconds
Started Apr 21 04:23:18 PM PDT 24
Finished Apr 21 04:23:49 PM PDT 24
Peak memory 255656 kb
Host smart-b54fc3f1-1ce9-41cb-8caa-f124c82fd7b0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883230751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.2883230751
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.4073825753
Short name T194
Test name
Test status
Simulation time 208398821522 ps
CPU time 3568.43 seconds
Started Apr 21 04:23:23 PM PDT 24
Finished Apr 21 05:22:52 PM PDT 24
Peak memory 305468 kb
Host smart-035e666c-286c-4bc1-97d3-648c4118cca8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073825753 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.4073825753
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.2059977014
Short name T651
Test name
Test status
Simulation time 55546132226 ps
CPU time 2568.93 seconds
Started Apr 21 04:23:29 PM PDT 24
Finished Apr 21 05:06:18 PM PDT 24
Peak memory 289076 kb
Host smart-aea0c994-3404-4f02-90d9-f56cc2c9df00
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059977014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.2059977014
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.2772165625
Short name T635
Test name
Test status
Simulation time 2561962497 ps
CPU time 162.45 seconds
Started Apr 21 04:23:28 PM PDT 24
Finished Apr 21 04:26:11 PM PDT 24
Peak memory 257112 kb
Host smart-61787c8e-f433-44c8-a7a7-e9d9436b03a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27721
65625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.2772165625
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.1536345673
Short name T426
Test name
Test status
Simulation time 957668803 ps
CPU time 13.31 seconds
Started Apr 21 04:23:30 PM PDT 24
Finished Apr 21 04:23:43 PM PDT 24
Peak memory 253196 kb
Host smart-cc3eff57-7773-4ef7-b118-f3ab6c6c634f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15363
45673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.1536345673
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.605201520
Short name T586
Test name
Test status
Simulation time 69064255639 ps
CPU time 1983.86 seconds
Started Apr 21 04:23:35 PM PDT 24
Finished Apr 21 04:56:39 PM PDT 24
Peak memory 273724 kb
Host smart-23e2f975-9dda-4062-832b-3cfc0dc32d18
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605201520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.605201520
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.1159528794
Short name T303
Test name
Test status
Simulation time 3682833876 ps
CPU time 157.62 seconds
Started Apr 21 04:23:31 PM PDT 24
Finished Apr 21 04:26:09 PM PDT 24
Peak memory 248240 kb
Host smart-523ed284-dced-4600-bbeb-589e705d0d49
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159528794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.1159528794
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.1501125956
Short name T584
Test name
Test status
Simulation time 732903736 ps
CPU time 57.55 seconds
Started Apr 21 04:23:30 PM PDT 24
Finished Apr 21 04:24:28 PM PDT 24
Peak memory 256196 kb
Host smart-02473102-29b6-464a-80d0-2a6e568f1f88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15011
25956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.1501125956
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.340741201
Short name T367
Test name
Test status
Simulation time 163679510 ps
CPU time 4.63 seconds
Started Apr 21 04:23:26 PM PDT 24
Finished Apr 21 04:23:31 PM PDT 24
Peak memory 251156 kb
Host smart-fc541029-9c5c-4ba7-8b55-a05db29c18eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34074
1201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.340741201
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.183337253
Short name T94
Test name
Test status
Simulation time 3112650202 ps
CPU time 51.34 seconds
Started Apr 21 04:23:30 PM PDT 24
Finished Apr 21 04:24:22 PM PDT 24
Peak memory 255172 kb
Host smart-06a9e46f-4dad-4762-8a3d-1f230457e5f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18333
7253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.183337253
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.3947502076
Short name T558
Test name
Test status
Simulation time 1443142760 ps
CPU time 32.56 seconds
Started Apr 21 04:23:21 PM PDT 24
Finished Apr 21 04:23:54 PM PDT 24
Peak memory 249100 kb
Host smart-6f0ea08c-a9d4-4249-b231-8c530e71aa23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39475
02076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.3947502076
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.226669493
Short name T238
Test name
Test status
Simulation time 50946930778 ps
CPU time 3375.41 seconds
Started Apr 21 04:23:32 PM PDT 24
Finished Apr 21 05:19:48 PM PDT 24
Peak memory 298376 kb
Host smart-79ab8b23-fd4c-433d-961e-39543792ec22
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226669493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_han
dler_stress_all.226669493
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.3041807525
Short name T54
Test name
Test status
Simulation time 172024963467 ps
CPU time 3170.41 seconds
Started Apr 21 04:23:36 PM PDT 24
Finished Apr 21 05:16:26 PM PDT 24
Peak memory 298456 kb
Host smart-d94620f8-859b-438e-97f1-b97b6c8b8493
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041807525 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.3041807525
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.2784990938
Short name T454
Test name
Test status
Simulation time 106057000020 ps
CPU time 3073.88 seconds
Started Apr 21 04:23:45 PM PDT 24
Finished Apr 21 05:15:00 PM PDT 24
Peak memory 289144 kb
Host smart-210dca89-47a0-42b7-acb1-7bd2a6158a33
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784990938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.2784990938
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.3743853648
Short name T581
Test name
Test status
Simulation time 2759603531 ps
CPU time 86.52 seconds
Started Apr 21 04:23:41 PM PDT 24
Finished Apr 21 04:25:08 PM PDT 24
Peak memory 249628 kb
Host smart-f57443f3-5e68-4267-9aa5-0f1c2eeee7f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37438
53648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.3743853648
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.2704770111
Short name T578
Test name
Test status
Simulation time 1313783122 ps
CPU time 28.63 seconds
Started Apr 21 04:23:41 PM PDT 24
Finished Apr 21 04:24:10 PM PDT 24
Peak memory 255828 kb
Host smart-6dc7d6b3-ad2c-4930-88d1-8616818944a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27047
70111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.2704770111
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.2325640715
Short name T525
Test name
Test status
Simulation time 8801929934 ps
CPU time 860.48 seconds
Started Apr 21 04:23:49 PM PDT 24
Finished Apr 21 04:38:09 PM PDT 24
Peak memory 266604 kb
Host smart-f5fb63f4-c8e8-409d-9154-ca1b1e3532e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325640715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.2325640715
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.3440219701
Short name T69
Test name
Test status
Simulation time 222391346921 ps
CPU time 2165.53 seconds
Started Apr 21 04:23:49 PM PDT 24
Finished Apr 21 04:59:55 PM PDT 24
Peak memory 284964 kb
Host smart-44d342db-3844-4431-836e-0bb5da02be54
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440219701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.3440219701
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.1232246071
Short name T513
Test name
Test status
Simulation time 1545720823 ps
CPU time 56.95 seconds
Started Apr 21 04:23:38 PM PDT 24
Finished Apr 21 04:24:35 PM PDT 24
Peak memory 249032 kb
Host smart-60f11af2-c1be-415b-b1a5-3cdc3089ae7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12322
46071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.1232246071
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.4155435042
Short name T394
Test name
Test status
Simulation time 663730276 ps
CPU time 21.99 seconds
Started Apr 21 04:23:40 PM PDT 24
Finished Apr 21 04:24:02 PM PDT 24
Peak memory 247580 kb
Host smart-f045ee64-3dd3-4419-849d-ea3bbc902980
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41554
35042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.4155435042
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.2299554404
Short name T702
Test name
Test status
Simulation time 90108221 ps
CPU time 12.46 seconds
Started Apr 21 04:23:41 PM PDT 24
Finished Apr 21 04:23:53 PM PDT 24
Peak memory 249068 kb
Host smart-cc9da492-cb86-4c05-83a8-e71ebf1497f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22995
54404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.2299554404
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.3215104177
Short name T708
Test name
Test status
Simulation time 1264033460 ps
CPU time 69.94 seconds
Started Apr 21 04:23:35 PM PDT 24
Finished Apr 21 04:24:45 PM PDT 24
Peak memory 256948 kb
Host smart-c8131e91-e01d-4cc3-9de1-f2d523b4a7c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32151
04177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.3215104177
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.3462985200
Short name T516
Test name
Test status
Simulation time 1964474576 ps
CPU time 174.63 seconds
Started Apr 21 04:23:54 PM PDT 24
Finished Apr 21 04:26:49 PM PDT 24
Peak memory 257260 kb
Host smart-8bf1e05b-3a0d-473a-8920-7510d1a0b4dd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462985200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.3462985200
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.1254098207
Short name T230
Test name
Test status
Simulation time 22204310781 ps
CPU time 921.8 seconds
Started Apr 21 04:23:57 PM PDT 24
Finished Apr 21 04:39:19 PM PDT 24
Peak memory 273128 kb
Host smart-d90cf4ea-6431-417b-aa12-6617234d88a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254098207 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.1254098207
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.3145129960
Short name T398
Test name
Test status
Simulation time 168086235824 ps
CPU time 2683.14 seconds
Started Apr 21 04:24:06 PM PDT 24
Finished Apr 21 05:08:50 PM PDT 24
Peak memory 290152 kb
Host smart-26450762-cafd-4f6a-b30f-47545f647613
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145129960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.3145129960
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.777921601
Short name T384
Test name
Test status
Simulation time 3914201879 ps
CPU time 80.57 seconds
Started Apr 21 04:24:02 PM PDT 24
Finished Apr 21 04:25:23 PM PDT 24
Peak memory 249352 kb
Host smart-2f5405bf-43b8-4e4a-96a1-825cd23f01f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77792
1601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.777921601
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.3562338391
Short name T660
Test name
Test status
Simulation time 647389044 ps
CPU time 47.71 seconds
Started Apr 21 04:24:03 PM PDT 24
Finished Apr 21 04:24:51 PM PDT 24
Peak memory 255748 kb
Host smart-d8fdf5d0-ee1f-42e2-a05f-0e5cc269fae7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35623
38391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.3562338391
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.2831357227
Short name T297
Test name
Test status
Simulation time 33866502595 ps
CPU time 2228.71 seconds
Started Apr 21 04:24:06 PM PDT 24
Finished Apr 21 05:01:15 PM PDT 24
Peak memory 285104 kb
Host smart-b5b6fa05-1ba5-44e7-b83c-0a1bed1b9d62
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831357227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.2831357227
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.1083552935
Short name T707
Test name
Test status
Simulation time 42244194896 ps
CPU time 2635.6 seconds
Started Apr 21 04:24:06 PM PDT 24
Finished Apr 21 05:08:02 PM PDT 24
Peak memory 286256 kb
Host smart-b5f98e68-7aeb-4e58-b673-5b448baf0fc1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083552935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.1083552935
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.4043210964
Short name T181
Test name
Test status
Simulation time 14051614178 ps
CPU time 300 seconds
Started Apr 21 04:24:06 PM PDT 24
Finished Apr 21 04:29:07 PM PDT 24
Peak memory 248076 kb
Host smart-ea0611e8-343c-4d35-80f3-fff92277d8d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043210964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.4043210964
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.366958906
Short name T40
Test name
Test status
Simulation time 404859765 ps
CPU time 25.81 seconds
Started Apr 21 04:23:56 PM PDT 24
Finished Apr 21 04:24:22 PM PDT 24
Peak memory 256260 kb
Host smart-c4ac2f10-2902-4177-9854-84960ce80424
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36695
8906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.366958906
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.1198311435
Short name T278
Test name
Test status
Simulation time 225948472 ps
CPU time 13.85 seconds
Started Apr 21 04:23:57 PM PDT 24
Finished Apr 21 04:24:11 PM PDT 24
Peak memory 247620 kb
Host smart-3c6eebc3-5321-414b-a5a9-328969fae996
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11983
11435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.1198311435
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.1686063957
Short name T460
Test name
Test status
Simulation time 698815379 ps
CPU time 35.6 seconds
Started Apr 21 04:24:03 PM PDT 24
Finished Apr 21 04:24:39 PM PDT 24
Peak memory 249096 kb
Host smart-89261d26-cd23-489b-a6e0-68f2847c30a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16860
63957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.1686063957
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.4265438232
Short name T373
Test name
Test status
Simulation time 1230612918 ps
CPU time 29.93 seconds
Started Apr 21 04:23:57 PM PDT 24
Finished Apr 21 04:24:27 PM PDT 24
Peak memory 256748 kb
Host smart-63f1ca8c-f5ec-4375-a876-f75a4cca74bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42654
38232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.4265438232
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.2918428469
Short name T175
Test name
Test status
Simulation time 175640818535 ps
CPU time 2184.14 seconds
Started Apr 21 04:24:14 PM PDT 24
Finished Apr 21 05:00:38 PM PDT 24
Peak memory 289692 kb
Host smart-2bd6a0f0-3aa7-4ad8-94c2-8e292fa35d8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918428469 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.2918428469
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.1659083288
Short name T421
Test name
Test status
Simulation time 14388798761 ps
CPU time 587.19 seconds
Started Apr 21 04:24:21 PM PDT 24
Finished Apr 21 04:34:09 PM PDT 24
Peak memory 265560 kb
Host smart-d4268354-a935-441a-8b08-4c9b9d0f8cd6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659083288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.1659083288
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.4060389710
Short name T425
Test name
Test status
Simulation time 2744655637 ps
CPU time 195.52 seconds
Started Apr 21 04:24:19 PM PDT 24
Finished Apr 21 04:27:34 PM PDT 24
Peak memory 250256 kb
Host smart-c393d59f-e4d2-429a-8bb8-da550e3eebba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40603
89710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.4060389710
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.1357287513
Short name T511
Test name
Test status
Simulation time 1425788291 ps
CPU time 28.68 seconds
Started Apr 21 04:24:18 PM PDT 24
Finished Apr 21 04:24:47 PM PDT 24
Peak memory 255748 kb
Host smart-c9ffb6f8-f1ed-4fa9-bca4-dd04454f1670
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13572
87513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.1357287513
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.3249287476
Short name T335
Test name
Test status
Simulation time 11867346492 ps
CPU time 1048.78 seconds
Started Apr 21 04:24:24 PM PDT 24
Finished Apr 21 04:41:53 PM PDT 24
Peak memory 270720 kb
Host smart-abf8a805-07c6-43d1-8e3f-b722b6c409ef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249287476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.3249287476
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.476976896
Short name T271
Test name
Test status
Simulation time 92751676654 ps
CPU time 2245.94 seconds
Started Apr 21 04:24:23 PM PDT 24
Finished Apr 21 05:01:49 PM PDT 24
Peak memory 289640 kb
Host smart-b952ae84-b4b5-4255-8509-3cc008b7772c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476976896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.476976896
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.3113999386
Short name T312
Test name
Test status
Simulation time 3837743563 ps
CPU time 79.98 seconds
Started Apr 21 04:24:24 PM PDT 24
Finished Apr 21 04:25:44 PM PDT 24
Peak memory 247320 kb
Host smart-3aac8393-a0e0-454f-84f3-e637e8f5f046
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113999386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.3113999386
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.3152166648
Short name T53
Test name
Test status
Simulation time 839837953 ps
CPU time 28.38 seconds
Started Apr 21 04:24:16 PM PDT 24
Finished Apr 21 04:24:45 PM PDT 24
Peak memory 257272 kb
Host smart-ea060240-6b15-457e-990a-3b1ed1413854
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31521
66648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.3152166648
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.583297529
Short name T457
Test name
Test status
Simulation time 579701937 ps
CPU time 20.95 seconds
Started Apr 21 04:24:19 PM PDT 24
Finished Apr 21 04:24:40 PM PDT 24
Peak memory 255728 kb
Host smart-e23d53f9-22b9-4a4d-acdc-ac17c8b6e0d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58329
7529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.583297529
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.1225088891
Short name T597
Test name
Test status
Simulation time 862608532 ps
CPU time 10.32 seconds
Started Apr 21 04:24:17 PM PDT 24
Finished Apr 21 04:24:28 PM PDT 24
Peak memory 249092 kb
Host smart-6e84eb04-0007-4758-8956-f594a88e31b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12250
88891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.1225088891
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.507973716
Short name T361
Test name
Test status
Simulation time 468238408 ps
CPU time 9.82 seconds
Started Apr 21 04:24:14 PM PDT 24
Finished Apr 21 04:24:24 PM PDT 24
Peak memory 254264 kb
Host smart-4d8a800d-ed1d-4313-891c-c8780ff0c10f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50797
3716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.507973716
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.1104605421
Short name T84
Test name
Test status
Simulation time 24430418199 ps
CPU time 2266.35 seconds
Started Apr 21 04:24:26 PM PDT 24
Finished Apr 21 05:02:13 PM PDT 24
Peak memory 282072 kb
Host smart-0a7632e8-912b-4534-b372-ef3a0eb75889
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104605421 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.1104605421
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.3328675646
Short name T488
Test name
Test status
Simulation time 27665724451 ps
CPU time 1400.55 seconds
Started Apr 21 04:24:40 PM PDT 24
Finished Apr 21 04:48:01 PM PDT 24
Peak memory 290176 kb
Host smart-28f87d93-69b4-4007-95de-55e7e16ec664
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328675646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.3328675646
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.1892819464
Short name T5
Test name
Test status
Simulation time 64464438669 ps
CPU time 251.21 seconds
Started Apr 21 04:24:30 PM PDT 24
Finished Apr 21 04:28:42 PM PDT 24
Peak memory 256784 kb
Host smart-cfad0a64-6994-4566-bc71-4cf357225283
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18928
19464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.1892819464
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.1554964392
Short name T556
Test name
Test status
Simulation time 2684452692 ps
CPU time 48.36 seconds
Started Apr 21 04:24:31 PM PDT 24
Finished Apr 21 04:25:19 PM PDT 24
Peak memory 255800 kb
Host smart-6a16f284-6188-4d86-bd93-02fc5a927c9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15549
64392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.1554964392
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.2738190754
Short name T283
Test name
Test status
Simulation time 119083777644 ps
CPU time 1868.55 seconds
Started Apr 21 04:24:46 PM PDT 24
Finished Apr 21 04:55:55 PM PDT 24
Peak memory 289156 kb
Host smart-88a632a9-0987-4cd3-b5f1-562a926b81bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738190754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.2738190754
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.2160295226
Short name T343
Test name
Test status
Simulation time 29910603591 ps
CPU time 1735.05 seconds
Started Apr 21 04:24:43 PM PDT 24
Finished Apr 21 04:53:39 PM PDT 24
Peak memory 281920 kb
Host smart-26e988a1-f87f-43e8-845d-4d330deaa825
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160295226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.2160295226
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.2578126188
Short name T292
Test name
Test status
Simulation time 10466567412 ps
CPU time 450.01 seconds
Started Apr 21 04:24:43 PM PDT 24
Finished Apr 21 04:32:13 PM PDT 24
Peak memory 247324 kb
Host smart-cd02125a-ef2d-4e19-91b6-5ea0a8eec9f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578126188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.2578126188
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.4182759212
Short name T62
Test name
Test status
Simulation time 364233711 ps
CPU time 11.57 seconds
Started Apr 21 04:24:29 PM PDT 24
Finished Apr 21 04:24:41 PM PDT 24
Peak memory 249300 kb
Host smart-23c716f8-3079-48f1-a0ca-abd60a667cf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41827
59212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.4182759212
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.2059552317
Short name T396
Test name
Test status
Simulation time 1097268377 ps
CPU time 18.96 seconds
Started Apr 21 04:24:30 PM PDT 24
Finished Apr 21 04:24:50 PM PDT 24
Peak memory 249064 kb
Host smart-6bf2cfef-b397-4a54-a91f-27fe4a28dba6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20595
52317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.2059552317
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.756076051
Short name T59
Test name
Test status
Simulation time 361564218 ps
CPU time 21.26 seconds
Started Apr 21 04:24:34 PM PDT 24
Finished Apr 21 04:24:56 PM PDT 24
Peak memory 249084 kb
Host smart-bb1b2849-1979-47b2-be4e-b8dd5ca9d2d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75607
6051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.756076051
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.3829070742
Short name T176
Test name
Test status
Simulation time 1294967765 ps
CPU time 38.43 seconds
Started Apr 21 04:24:28 PM PDT 24
Finished Apr 21 04:25:07 PM PDT 24
Peak memory 255944 kb
Host smart-89e1954a-55ad-42b5-9e63-2b2441da64e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38290
70742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.3829070742
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.30742396
Short name T486
Test name
Test status
Simulation time 4344168407 ps
CPU time 340.09 seconds
Started Apr 21 04:24:46 PM PDT 24
Finished Apr 21 04:30:27 PM PDT 24
Peak memory 272732 kb
Host smart-f150c08f-2ef4-49cd-8e20-f8b0a8dce00c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30742396 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.30742396
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.2514166371
Short name T413
Test name
Test status
Simulation time 38611157385 ps
CPU time 1761.41 seconds
Started Apr 21 04:24:53 PM PDT 24
Finished Apr 21 04:54:15 PM PDT 24
Peak memory 289648 kb
Host smart-a31a3c52-51eb-46e9-a4fb-8d6653f03fb6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514166371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.2514166371
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.2611667734
Short name T689
Test name
Test status
Simulation time 6927060080 ps
CPU time 261.19 seconds
Started Apr 21 04:24:47 PM PDT 24
Finished Apr 21 04:29:09 PM PDT 24
Peak memory 256920 kb
Host smart-4d365b05-a8dc-4ba6-aa7e-fdc2db3f4992
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26116
67734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.2611667734
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.2939884738
Short name T535
Test name
Test status
Simulation time 2728625474 ps
CPU time 52.54 seconds
Started Apr 21 04:24:45 PM PDT 24
Finished Apr 21 04:25:38 PM PDT 24
Peak memory 249352 kb
Host smart-25a2ba39-96f5-4556-a96b-26f691ba7511
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29398
84738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.2939884738
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.4024639222
Short name T336
Test name
Test status
Simulation time 24596660033 ps
CPU time 1445.04 seconds
Started Apr 21 04:24:55 PM PDT 24
Finished Apr 21 04:49:00 PM PDT 24
Peak memory 265584 kb
Host smart-739f129f-207b-497a-b35a-1cf9731e2fa3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024639222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.4024639222
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.3013593982
Short name T284
Test name
Test status
Simulation time 138914148676 ps
CPU time 2128.79 seconds
Started Apr 21 04:24:56 PM PDT 24
Finished Apr 21 05:00:25 PM PDT 24
Peak memory 273664 kb
Host smart-ed856b9e-c638-4b6d-97d0-2b863d0da497
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013593982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.3013593982
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.1285057623
Short name T404
Test name
Test status
Simulation time 1191564591 ps
CPU time 59.87 seconds
Started Apr 21 04:24:46 PM PDT 24
Finished Apr 21 04:25:46 PM PDT 24
Peak memory 249040 kb
Host smart-63118977-3a99-421b-9b65-ead002d80f20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12850
57623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.1285057623
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.1416718811
Short name T222
Test name
Test status
Simulation time 351617479 ps
CPU time 23.43 seconds
Started Apr 21 04:24:47 PM PDT 24
Finished Apr 21 04:25:11 PM PDT 24
Peak memory 248984 kb
Host smart-c462f86d-6438-49ee-b866-387c66d2158f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14167
18811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.1416718811
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.3560902238
Short name T612
Test name
Test status
Simulation time 195528257 ps
CPU time 14.98 seconds
Started Apr 21 04:24:49 PM PDT 24
Finished Apr 21 04:25:04 PM PDT 24
Peak memory 253156 kb
Host smart-8da43331-5bf1-41e2-835a-df8565aaddb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35609
02238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.3560902238
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.3466771512
Short name T691
Test name
Test status
Simulation time 351054447 ps
CPU time 7.18 seconds
Started Apr 21 04:24:48 PM PDT 24
Finished Apr 21 04:24:55 PM PDT 24
Peak memory 240896 kb
Host smart-ad5cda20-5118-41ab-baa2-629ca2a26494
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34667
71512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.3466771512
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.2696873395
Short name T393
Test name
Test status
Simulation time 44537428337 ps
CPU time 1511.18 seconds
Started Apr 21 04:24:55 PM PDT 24
Finished Apr 21 04:50:07 PM PDT 24
Peak memory 289208 kb
Host smart-fa6180d5-3a8d-4488-91ab-cbc8842dc438
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696873395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.2696873395
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.153657386
Short name T200
Test name
Test status
Simulation time 129513661 ps
CPU time 3.33 seconds
Started Apr 21 04:17:19 PM PDT 24
Finished Apr 21 04:17:22 PM PDT 24
Peak memory 249392 kb
Host smart-33952fa9-230e-4416-99e5-97f2ce6a8e34
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=153657386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.153657386
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.951555192
Short name T72
Test name
Test status
Simulation time 50661469929 ps
CPU time 1121.99 seconds
Started Apr 21 04:17:15 PM PDT 24
Finished Apr 21 04:35:57 PM PDT 24
Peak memory 273756 kb
Host smart-2b005e7c-6072-4f3f-bee8-faad85d8ca5d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951555192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.951555192
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.2076722056
Short name T86
Test name
Test status
Simulation time 363037678 ps
CPU time 10.51 seconds
Started Apr 21 04:17:21 PM PDT 24
Finished Apr 21 04:17:32 PM PDT 24
Peak memory 240840 kb
Host smart-2de4ffe3-ff37-4bc6-a176-2442b2dc0c3f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2076722056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.2076722056
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.2465124981
Short name T272
Test name
Test status
Simulation time 1845015808 ps
CPU time 166.51 seconds
Started Apr 21 04:17:17 PM PDT 24
Finished Apr 21 04:20:04 PM PDT 24
Peak memory 251104 kb
Host smart-cd9af485-4873-4670-ac0b-c76ebd3ba4fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24651
24981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.2465124981
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.962262602
Short name T538
Test name
Test status
Simulation time 82404220 ps
CPU time 4.29 seconds
Started Apr 21 04:17:15 PM PDT 24
Finished Apr 21 04:17:19 PM PDT 24
Peak memory 240868 kb
Host smart-cbe2ba19-542a-48ba-80fd-deda00192923
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96226
2602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.962262602
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.1823635728
Short name T636
Test name
Test status
Simulation time 54046061955 ps
CPU time 1066.96 seconds
Started Apr 21 04:17:18 PM PDT 24
Finished Apr 21 04:35:05 PM PDT 24
Peak memory 289772 kb
Host smart-4ac0ead9-e3b6-4574-bb5a-23975ec64ce0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823635728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.1823635728
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.3189837943
Short name T703
Test name
Test status
Simulation time 9752576836 ps
CPU time 863.7 seconds
Started Apr 21 04:17:20 PM PDT 24
Finished Apr 21 04:31:44 PM PDT 24
Peak memory 286056 kb
Host smart-abfa8d65-7339-481b-9de5-ec291d8e31cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189837943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.3189837943
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.691989638
Short name T627
Test name
Test status
Simulation time 19153226079 ps
CPU time 213.13 seconds
Started Apr 21 04:17:16 PM PDT 24
Finished Apr 21 04:20:49 PM PDT 24
Peak memory 248096 kb
Host smart-7600a59d-072d-411f-b0dd-de0e4ab0a203
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691989638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.691989638
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.1989700810
Short name T524
Test name
Test status
Simulation time 450214652 ps
CPU time 8.33 seconds
Started Apr 21 04:17:13 PM PDT 24
Finished Apr 21 04:17:22 PM PDT 24
Peak memory 251124 kb
Host smart-db4eb939-37fe-407f-948a-28d5a8769aab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19897
00810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.1989700810
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.2936634429
Short name T68
Test name
Test status
Simulation time 1321912928 ps
CPU time 29.67 seconds
Started Apr 21 04:17:14 PM PDT 24
Finished Apr 21 04:17:43 PM PDT 24
Peak memory 247812 kb
Host smart-f14ad9c6-e2c2-4d4d-aa98-c4e985b93977
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29366
34429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.2936634429
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.3181750478
Short name T254
Test name
Test status
Simulation time 1355807149 ps
CPU time 26.5 seconds
Started Apr 21 04:17:18 PM PDT 24
Finished Apr 21 04:17:44 PM PDT 24
Peak memory 247808 kb
Host smart-50770f7d-ebb4-4515-9db6-9f125583634c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31817
50478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.3181750478
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.605621699
Short name T280
Test name
Test status
Simulation time 2483071361 ps
CPU time 17.88 seconds
Started Apr 21 04:17:15 PM PDT 24
Finished Apr 21 04:17:33 PM PDT 24
Peak memory 249184 kb
Host smart-d420679b-7bb8-4236-b4c3-9a6d86bda191
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60562
1699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.605621699
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.2585048860
Short name T277
Test name
Test status
Simulation time 47523900438 ps
CPU time 1336.93 seconds
Started Apr 21 04:17:18 PM PDT 24
Finished Apr 21 04:39:35 PM PDT 24
Peak memory 289020 kb
Host smart-e10ffd1b-d078-43d3-b9b0-e9708613ab2f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585048860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.2585048860
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.4275485075
Short name T180
Test name
Test status
Simulation time 13410071 ps
CPU time 2.48 seconds
Started Apr 21 04:17:29 PM PDT 24
Finished Apr 21 04:17:32 PM PDT 24
Peak memory 249564 kb
Host smart-d7353c8c-4498-4f25-ba46-b25d7e4d6413
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4275485075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.4275485075
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.1721500538
Short name T576
Test name
Test status
Simulation time 136737851059 ps
CPU time 2201.73 seconds
Started Apr 21 04:17:25 PM PDT 24
Finished Apr 21 04:54:07 PM PDT 24
Peak memory 285340 kb
Host smart-5b30fe16-eea4-4109-ba0f-fabcde4bd6fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721500538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.1721500538
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.2189080429
Short name T391
Test name
Test status
Simulation time 372321941 ps
CPU time 19.88 seconds
Started Apr 21 04:17:29 PM PDT 24
Finished Apr 21 04:17:49 PM PDT 24
Peak memory 249084 kb
Host smart-b8bdbb17-64cf-4e58-acbf-16613387705c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2189080429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.2189080429
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.2527391272
Short name T585
Test name
Test status
Simulation time 5231728047 ps
CPU time 58.33 seconds
Started Apr 21 04:17:25 PM PDT 24
Finished Apr 21 04:18:24 PM PDT 24
Peak memory 256436 kb
Host smart-172b0863-56cf-47a3-9638-668565b466b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25273
91272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.2527391272
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.2216363389
Short name T498
Test name
Test status
Simulation time 160806545 ps
CPU time 22.17 seconds
Started Apr 21 04:17:22 PM PDT 24
Finished Apr 21 04:17:44 PM PDT 24
Peak memory 248092 kb
Host smart-a1b5c5c6-c1e5-46db-907e-51ee45cb4478
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22163
63389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.2216363389
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.736539128
Short name T526
Test name
Test status
Simulation time 376564712806 ps
CPU time 2511.55 seconds
Started Apr 21 04:17:29 PM PDT 24
Finished Apr 21 04:59:21 PM PDT 24
Peak memory 289804 kb
Host smart-8b7f8738-17d4-46dc-a797-4d77c61fea8f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736539128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.736539128
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.1489350354
Short name T300
Test name
Test status
Simulation time 15331868348 ps
CPU time 512.44 seconds
Started Apr 21 04:17:25 PM PDT 24
Finished Apr 21 04:25:58 PM PDT 24
Peak memory 248092 kb
Host smart-a9e5fa38-a2bc-4f7d-b4a5-a3eabb7b4d54
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489350354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.1489350354
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.1312451759
Short name T49
Test name
Test status
Simulation time 494337850 ps
CPU time 33.01 seconds
Started Apr 21 04:17:22 PM PDT 24
Finished Apr 21 04:17:55 PM PDT 24
Peak memory 257244 kb
Host smart-b26df4c1-187c-4bb0-a7d7-316360480e8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13124
51759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.1312451759
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.1419835175
Short name T629
Test name
Test status
Simulation time 2254253692 ps
CPU time 67.36 seconds
Started Apr 21 04:17:22 PM PDT 24
Finished Apr 21 04:18:30 PM PDT 24
Peak memory 256204 kb
Host smart-2d770edc-45f2-438d-b74f-a4f2c28f067c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14198
35175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.1419835175
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.661075923
Short name T431
Test name
Test status
Simulation time 3888659668 ps
CPU time 27.55 seconds
Started Apr 21 04:17:25 PM PDT 24
Finished Apr 21 04:17:53 PM PDT 24
Peak memory 255468 kb
Host smart-2ef98d92-7d5c-426c-843e-4ba77b775dbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66107
5923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.661075923
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.1901539451
Short name T223
Test name
Test status
Simulation time 155178869 ps
CPU time 14.4 seconds
Started Apr 21 04:17:21 PM PDT 24
Finished Apr 21 04:17:36 PM PDT 24
Peak memory 257224 kb
Host smart-d0775746-9ca9-4cdf-8761-9179a1290b6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19015
39451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.1901539451
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.592062072
Short name T260
Test name
Test status
Simulation time 173459462209 ps
CPU time 3010.12 seconds
Started Apr 21 04:17:29 PM PDT 24
Finished Apr 21 05:07:40 PM PDT 24
Peak memory 289476 kb
Host smart-7a6b1eab-aac1-483a-afed-055ff576f31f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592062072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_hand
ler_stress_all.592062072
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.3318481773
Short name T215
Test name
Test status
Simulation time 140813607 ps
CPU time 3.65 seconds
Started Apr 21 04:17:34 PM PDT 24
Finished Apr 21 04:17:38 PM PDT 24
Peak memory 249412 kb
Host smart-d68d0c04-381b-4cd3-b1f2-515a8118ba1d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3318481773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.3318481773
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.1292337043
Short name T270
Test name
Test status
Simulation time 74172564386 ps
CPU time 2322.82 seconds
Started Apr 21 04:17:34 PM PDT 24
Finished Apr 21 04:56:17 PM PDT 24
Peak memory 289428 kb
Host smart-49e56229-da1c-45c6-a94d-5c08b2e5000d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292337043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.1292337043
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.20112891
Short name T434
Test name
Test status
Simulation time 315476032 ps
CPU time 17.1 seconds
Started Apr 21 04:17:34 PM PDT 24
Finished Apr 21 04:17:51 PM PDT 24
Peak memory 249120 kb
Host smart-c5890d08-7bee-4b75-8080-0e053b766c98
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=20112891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.20112891
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.1943696876
Short name T625
Test name
Test status
Simulation time 2136712373 ps
CPU time 147.84 seconds
Started Apr 21 04:17:31 PM PDT 24
Finished Apr 21 04:20:00 PM PDT 24
Peak memory 256692 kb
Host smart-7a33ed3d-d561-47de-8063-9e656600461d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19436
96876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.1943696876
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.268600405
Short name T587
Test name
Test status
Simulation time 118170116 ps
CPU time 8.86 seconds
Started Apr 21 04:17:31 PM PDT 24
Finished Apr 21 04:17:40 PM PDT 24
Peak memory 251028 kb
Host smart-49d9863d-32aa-45b0-8006-81c95e9f3cd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26860
0405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.268600405
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.1742493839
Short name T330
Test name
Test status
Simulation time 56550578571 ps
CPU time 3292.08 seconds
Started Apr 21 04:17:34 PM PDT 24
Finished Apr 21 05:12:26 PM PDT 24
Peak memory 289272 kb
Host smart-b2e73488-1b7d-4689-b621-9850229ccfc2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742493839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.1742493839
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.3546810200
Short name T93
Test name
Test status
Simulation time 6964654082 ps
CPU time 802.58 seconds
Started Apr 21 04:17:33 PM PDT 24
Finished Apr 21 04:30:56 PM PDT 24
Peak memory 273760 kb
Host smart-2ec61f97-1d2c-4d19-a082-07e450226529
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546810200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.3546810200
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.3064956082
Short name T301
Test name
Test status
Simulation time 9278869836 ps
CPU time 198.77 seconds
Started Apr 21 04:17:32 PM PDT 24
Finished Apr 21 04:20:51 PM PDT 24
Peak memory 248416 kb
Host smart-73d1127f-2785-4256-a964-47bfd676d909
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064956082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.3064956082
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.3167237237
Short name T568
Test name
Test status
Simulation time 3009076003 ps
CPU time 44.39 seconds
Started Apr 21 04:17:30 PM PDT 24
Finished Apr 21 04:18:15 PM PDT 24
Peak memory 249348 kb
Host smart-71ba9eb4-c532-4bce-83ec-d5ea27e177c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31672
37237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.3167237237
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.3862812115
Short name T540
Test name
Test status
Simulation time 1296661468 ps
CPU time 23.4 seconds
Started Apr 21 04:17:39 PM PDT 24
Finished Apr 21 04:18:03 PM PDT 24
Peak memory 248984 kb
Host smart-06a0d3f3-a73e-4393-ac61-ca4c8f026a85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38628
12115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.3862812115
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.2489133651
Short name T658
Test name
Test status
Simulation time 949264942 ps
CPU time 28.81 seconds
Started Apr 21 04:17:32 PM PDT 24
Finished Apr 21 04:18:01 PM PDT 24
Peak memory 255724 kb
Host smart-bf9c25b6-09b1-47c3-8d0a-d1a63d8c7e19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24891
33651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.2489133651
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.3850477366
Short name T566
Test name
Test status
Simulation time 4763587001 ps
CPU time 76.53 seconds
Started Apr 21 04:17:34 PM PDT 24
Finished Apr 21 04:18:51 PM PDT 24
Peak memory 249304 kb
Host smart-c62770a5-1191-498c-86be-a3bbf45a72c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38504
77366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.3850477366
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.3465305810
Short name T29
Test name
Test status
Simulation time 252024263938 ps
CPU time 3637.1 seconds
Started Apr 21 04:17:34 PM PDT 24
Finished Apr 21 05:18:12 PM PDT 24
Peak memory 289484 kb
Host smart-46f53dab-104c-4daa-8ae9-f6084bb46659
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465305810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.3465305810
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.955140729
Short name T480
Test name
Test status
Simulation time 24749134318 ps
CPU time 2415.69 seconds
Started Apr 21 04:17:34 PM PDT 24
Finished Apr 21 04:57:51 PM PDT 24
Peak memory 306656 kb
Host smart-2b6f1b3d-f6e0-44b2-a92c-aeede8adfd3d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955140729 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.955140729
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.1707467752
Short name T201
Test name
Test status
Simulation time 18547445 ps
CPU time 2.92 seconds
Started Apr 21 04:17:42 PM PDT 24
Finished Apr 21 04:17:45 PM PDT 24
Peak memory 249360 kb
Host smart-caa1c10d-70da-4420-9932-e2854860340e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1707467752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.1707467752
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.3752152348
Short name T616
Test name
Test status
Simulation time 35350885538 ps
CPU time 2402.01 seconds
Started Apr 21 04:17:42 PM PDT 24
Finished Apr 21 04:57:45 PM PDT 24
Peak memory 289452 kb
Host smart-260c23a9-de4e-471d-848b-8746b8543313
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752152348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.3752152348
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.564757489
Short name T596
Test name
Test status
Simulation time 170582867 ps
CPU time 10.11 seconds
Started Apr 21 04:17:44 PM PDT 24
Finished Apr 21 04:17:54 PM PDT 24
Peak memory 249108 kb
Host smart-ef0ad74d-472e-4cc8-9b0f-125df87193ba
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=564757489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.564757489
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.3683139606
Short name T680
Test name
Test status
Simulation time 15128739504 ps
CPU time 182.38 seconds
Started Apr 21 04:17:37 PM PDT 24
Finished Apr 21 04:20:39 PM PDT 24
Peak memory 256920 kb
Host smart-7908fd03-2a21-4a09-bcdf-730d43b059e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36831
39606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.3683139606
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.15302574
Short name T626
Test name
Test status
Simulation time 1497468028 ps
CPU time 26.16 seconds
Started Apr 21 04:17:38 PM PDT 24
Finished Apr 21 04:18:04 PM PDT 24
Peak memory 254620 kb
Host smart-edc0f63b-d317-49a4-9403-2630030154ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15302
574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.15302574
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.3177102392
Short name T345
Test name
Test status
Simulation time 101092808222 ps
CPU time 1822.53 seconds
Started Apr 21 04:17:42 PM PDT 24
Finished Apr 21 04:48:05 PM PDT 24
Peak memory 273644 kb
Host smart-85d5f1f2-2985-4d3b-9e5c-9778cd349be3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177102392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.3177102392
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.3631476557
Short name T530
Test name
Test status
Simulation time 43511552100 ps
CPU time 1196.14 seconds
Started Apr 21 04:17:43 PM PDT 24
Finished Apr 21 04:37:40 PM PDT 24
Peak memory 273764 kb
Host smart-895cca90-f357-4c8b-9b4b-43e869104214
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631476557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.3631476557
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.2674630372
Short name T224
Test name
Test status
Simulation time 33327816793 ps
CPU time 674.07 seconds
Started Apr 21 04:17:40 PM PDT 24
Finished Apr 21 04:28:54 PM PDT 24
Peak memory 248316 kb
Host smart-e72ca01e-1f6b-4998-a2c3-e0a335b7d83a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674630372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.2674630372
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.1861147098
Short name T533
Test name
Test status
Simulation time 348120118 ps
CPU time 30.51 seconds
Started Apr 21 04:17:37 PM PDT 24
Finished Apr 21 04:18:07 PM PDT 24
Peak memory 249040 kb
Host smart-5dd022fc-a3fb-4f07-8dad-9611b62167b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18611
47098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.1861147098
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.1895943174
Short name T44
Test name
Test status
Simulation time 970639563 ps
CPU time 32.55 seconds
Started Apr 21 04:17:39 PM PDT 24
Finished Apr 21 04:18:12 PM PDT 24
Peak memory 249024 kb
Host smart-ecb9970c-eca5-4aa2-b1a3-84d77407ef92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18959
43174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.1895943174
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.3441762849
Short name T83
Test name
Test status
Simulation time 639549629 ps
CPU time 14.46 seconds
Started Apr 21 04:17:42 PM PDT 24
Finished Apr 21 04:17:57 PM PDT 24
Peak memory 254336 kb
Host smart-35520405-650b-4094-895d-d4286d02d9b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34417
62849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.3441762849
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.669491914
Short name T419
Test name
Test status
Simulation time 1524614895 ps
CPU time 60.23 seconds
Started Apr 21 04:17:39 PM PDT 24
Finished Apr 21 04:18:39 PM PDT 24
Peak memory 249032 kb
Host smart-a25a2cb7-9024-469a-a511-63a057df929f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66949
1914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.669491914
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.3892425347
Short name T179
Test name
Test status
Simulation time 17945206405 ps
CPU time 517.39 seconds
Started Apr 21 04:17:43 PM PDT 24
Finished Apr 21 04:26:21 PM PDT 24
Peak memory 255732 kb
Host smart-c7b78b63-aa28-4fca-878f-2ef214f796ab
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892425347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.3892425347
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.2540720249
Short name T116
Test name
Test status
Simulation time 188915793798 ps
CPU time 3549.64 seconds
Started Apr 21 04:17:48 PM PDT 24
Finished Apr 21 05:16:58 PM PDT 24
Peak memory 318844 kb
Host smart-b1223381-070a-473c-b986-71cd77ed5167
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540720249 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.2540720249
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.3398709057
Short name T199
Test name
Test status
Simulation time 140905380 ps
CPU time 3.47 seconds
Started Apr 21 04:17:49 PM PDT 24
Finished Apr 21 04:17:52 PM PDT 24
Peak memory 249344 kb
Host smart-4fb69be9-8495-44e0-8952-ea0af7683792
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3398709057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.3398709057
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.3789615824
Short name T177
Test name
Test status
Simulation time 53312536814 ps
CPU time 935.17 seconds
Started Apr 21 04:17:52 PM PDT 24
Finished Apr 21 04:33:27 PM PDT 24
Peak memory 273612 kb
Host smart-30e2a096-6035-4717-bf0e-dc7aaacd08e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789615824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.3789615824
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.1782395539
Short name T528
Test name
Test status
Simulation time 156250228 ps
CPU time 9.86 seconds
Started Apr 21 04:17:46 PM PDT 24
Finished Apr 21 04:17:56 PM PDT 24
Peak memory 240888 kb
Host smart-4273e4be-733e-447e-8648-7f7943793c7b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1782395539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.1782395539
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.4113320821
Short name T470
Test name
Test status
Simulation time 3136282038 ps
CPU time 21.81 seconds
Started Apr 21 04:17:45 PM PDT 24
Finished Apr 21 04:18:07 PM PDT 24
Peak memory 254324 kb
Host smart-8e6fc98b-040e-4f6c-b607-8ea1a2602f51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41133
20821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.4113320821
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.59351636
Short name T695
Test name
Test status
Simulation time 1102734284 ps
CPU time 66.35 seconds
Started Apr 21 04:17:46 PM PDT 24
Finished Apr 21 04:18:52 PM PDT 24
Peak memory 255900 kb
Host smart-28e9f8f3-c437-4fbf-88cd-ffdf76d6bed7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59351
636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.59351636
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.171165819
Short name T409
Test name
Test status
Simulation time 20688612719 ps
CPU time 1292.8 seconds
Started Apr 21 04:17:52 PM PDT 24
Finished Apr 21 04:39:25 PM PDT 24
Peak memory 286376 kb
Host smart-52f755cb-a2cf-45a7-924b-904878a51588
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171165819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.171165819
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.1710420448
Short name T550
Test name
Test status
Simulation time 10865286885 ps
CPU time 122.67 seconds
Started Apr 21 04:17:52 PM PDT 24
Finished Apr 21 04:19:55 PM PDT 24
Peak memory 248136 kb
Host smart-9ef5f1e2-5aca-4700-91b8-a94a9eae8c52
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710420448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.1710420448
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.2383024753
Short name T469
Test name
Test status
Simulation time 260092064 ps
CPU time 9.13 seconds
Started Apr 21 04:17:52 PM PDT 24
Finished Apr 21 04:18:01 PM PDT 24
Peak memory 248972 kb
Host smart-0e1e5920-6b53-405a-811c-116a136a6c80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23830
24753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.2383024753
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.641859558
Short name T273
Test name
Test status
Simulation time 1710051393 ps
CPU time 17.71 seconds
Started Apr 21 04:17:48 PM PDT 24
Finished Apr 21 04:18:06 PM PDT 24
Peak memory 247612 kb
Host smart-430ad1b5-5581-42be-adc6-b509c0dcdd9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64185
9558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.641859558
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.1922156953
Short name T257
Test name
Test status
Simulation time 613154778 ps
CPU time 43.35 seconds
Started Apr 21 04:17:50 PM PDT 24
Finished Apr 21 04:18:34 PM PDT 24
Peak memory 255316 kb
Host smart-ac40ab22-1f03-4f35-bf9b-b5ddb79987fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19221
56953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.1922156953
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.3466418015
Short name T687
Test name
Test status
Simulation time 1146962235 ps
CPU time 66.08 seconds
Started Apr 21 04:17:43 PM PDT 24
Finished Apr 21 04:18:49 PM PDT 24
Peak memory 256288 kb
Host smart-e62d2934-02a5-48a1-be7e-326b15e0b928
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34664
18015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.3466418015
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.2900659788
Short name T45
Test name
Test status
Simulation time 98813721908 ps
CPU time 2515.38 seconds
Started Apr 21 04:17:48 PM PDT 24
Finished Apr 21 04:59:44 PM PDT 24
Peak memory 290024 kb
Host smart-12c85159-2c1d-473b-a9e9-a9646b553fd8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900659788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.2900659788
Directory /workspace/9.alert_handler_stress_all/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%