Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	86155	1			T1	1		T3	5		T4	524
class_i[0x1]	50555	1			T3	2		T4	22		T6	4
class_i[0x2]	59606	1			T1	25		T4	12		T6	3
class_i[0x3]	63188	1			T1	10		T3	1		T4	7

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	65421	1			T1	1		T3	4		T4	146
alert[0x1]	67553	1			T1	10		T4	135		T6	2
alert[0x2]	62892	1			T1	12		T3	1		T4	185
alert[0x3]	63638	1			T1	13		T3	3		T4	99

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

259207

1

T1

36

T3

4

T4

565

esc_ping_fail

297

1

T3

4

T6

9

T54

8

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	65335	1			T1	1		T3	2		T4	146
esc_integrity_fail	alert[0x1]	67474	1			T1	10		T4	135		T16	582
esc_integrity_fail	alert[0x2]	62819	1			T1	12		T4	185		T6	2
esc_integrity_fail	alert[0x3]	63579	1			T1	13		T3	2		T4	99
esc_ping_fail	alert[0x0]	86	1			T3	2		T6	4		T54	3
esc_ping_fail	alert[0x1]	79	1			T6	2		T54	2		T59	1
esc_ping_fail	alert[0x2]	73	1			T3	1		T6	2		T54	2
esc_ping_fail	alert[0x3]	59	1			T3	1		T6	1		T54	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	86077	1			T1	1		T3	2		T4	524
esc_integrity_fail	class_i[0x1]	50476	1			T3	2		T4	22		T6	2
esc_integrity_fail	class_i[0x2]	59530	1			T1	25		T4	12		T6	3
esc_integrity_fail	class_i[0x3]	63124	1			T1	10		T4	7		T16	3
esc_ping_fail	class_i[0x0]	78	1			T3	3		T59	1		T61	3
esc_ping_fail	class_i[0x1]	79	1			T6	2		T54	7		T59	2
esc_ping_fail	class_i[0x2]	76	1			T54	1		T59	1		T234	8
esc_ping_fail	class_i[0x3]	64	1			T3	1		T6	7		T59	1