Unified Coverage Report

Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	611713173	0	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	611713173	0	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	611713173	0	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	611713173	0	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	611713173	0	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	611713173	0	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	611713173	0	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	611713173	0	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	611713173	0	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	611713173	0	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	611713173	0	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	611713173	0	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	611713173	0	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	611713173	0	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	611713173	0	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	611713173	0	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	611713173	0	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	611713173	0	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	611713173	0	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	611713173	0	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	611713173	0	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	611713173	0	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	611713173	0	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	611713173	0	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	611713173	0	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	611713173	0	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	611713173	0	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	611713173	0	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	611713173	0	0	0
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	611713173	0	0	610
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	611713173	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	611713173	611643977	0	0
tb.dut.CheckAccuCntDw	0	0	610	610	0	0
tb.dut.CheckEscCntDw	0	0	610	610	0	0
tb.dut.CheckNAlerts	0	0	610	610	0	0
tb.dut.CheckNClasses	0	0	610	610	0	0
tb.dut.CheckNEscSev	0	0	610	610	0	0
tb.dut.CrashdumpKnownO_A	0	0	611713173	611643977	0	0
tb.dut.EdnKnownO_A	0	0	611713173	611643977	0	0
tb.dut.EscPKnownO_A	0	0	611713173	611643977	0	0
tb.dut.IrqAKnownO_A	0	0	611713173	611643977	0	0
tb.dut.IrqBKnownO_A	0	0	611713173	611643977	0	0
tb.dut.IrqCKnownO_A	0	0	611713173	611643977	0	0
tb.dut.IrqDKnownO_A	0	0	611713173	611643977	0	0
tb.dut.TlAReadyKnownO_A	0	0	611713173	611643977	0	0
tb.dut.TlDValidKnownO_A	0	0	611713173	611643977	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	637219141	1999976	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	637219141	16169	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	637219141	15935	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	637219141	14771	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	637219141	15916	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	637219141	16186	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	637219141	14861	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	637219141	15920	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	637219141	15180	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	637219141	15114	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	637219141	14820	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	637219141	14599	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	637219141	14607	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	637219141	14829	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	637219141	14821	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	637219141	15038	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	637219141	14679	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	637219141	15915	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	637219141	14864	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	637219141	14780	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	637219141	14948	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	637219141	14912	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	637219141	15733	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	637219141	14413	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	637219141	14792	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	637219141	14673	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	637219141	15816	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	637219141	14820	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	637219141	15892	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	637219141	15926	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	637219141	14743	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	637219141	14483	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	637219141	14809	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	637219141	14676	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	637219141	15567	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	637219141	15670	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	637219141	14749	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	637219141	14712	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	637219141	14941	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	637219141	14632	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	637219141	15931	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	637219141	14863	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	637219141	14739	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	637219141	14660	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	637219141	15921	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	637219141	14600	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	637219141	14763	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	637219141	14600	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	637219141	16308	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	637219141	14626	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	637219141	14644	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	637219141	14715	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	637219141	14789	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	637219141	16149	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	637219141	14912	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	637219141	16023	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	637219141	14735	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	637219141	15716	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	637219141	14734	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	637219141	14834	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	637219141	14543	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	637219141	14548	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	637219141	14836	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	637219141	15988	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	637219141	14736	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	637219141	14690	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	637219141	15888	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	637219141	14888	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	637219141	14552	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	637219141	15854	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	637219141	26524	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	637219141	14962	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	637219141	14812	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	637219141	14897	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	637219141	16059	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	637219141	15768	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	637219141	15874	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	637219141	14495	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	637219141	15768	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	611713173	5030	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	611713173	247047	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	611713173	312636045	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	611713173	800	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	611713173	66	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	611713173	386	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	611713173	240067758	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	611713173	918	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	611713173	897	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	611713173	880	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	611713173	868	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	611713173	1234	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	611713173	118169	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	611713173	1105	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	611713173	61	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	611713173	611643977	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	610	610	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	611713173	611643977	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	611713173	3114	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	611713173	191985	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	611713173	337234634	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	611713173	509	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	611713173	25	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	611713173	257	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	611713173	266682475	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	611713173	580	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	611713173	569	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	611713173	556	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	611713173	544	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	611713173	1104	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	611713173	119305	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	611713173	1025	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	611713173	52	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	611713173	611643977	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	610	610	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	611713173	611643977	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	611713173	1568	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	611713173	235852	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	611713173	342594576	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	611713173	476	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	611713173	31	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	611713173	225	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	611713173	285686337	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	611713173	553	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	611713173	540	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	611713173	529	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	611713173	522	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	611713173	711	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	611713173	70949	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	611713173	618	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	611713173	59	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	611713173	611643977	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	610	610	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	611713173	611643977	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	611713173	5407	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	611713173	155146	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	611713173	355999960	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	611713173	481	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	611713173	18	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	611713173	220	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	611713173	278108389	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	611713173	550	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	611713173	539	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	611713173	529	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	611713173	521	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	611713173	1008	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	611713173	102530	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	611713173	926	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	611713173	63	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	611713173	611643977	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	610	610	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	611713173	611643977	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	637219141	109192974	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	637219141	636668271	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	637219141	636668271	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	637219141	161390590	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	637219141	636668271	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	637219141	636668271	0	0
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tb.dut.tlul_assert_device.gen_assert_final[160].noOutstandingReqsAtEndOfSim_A	0	0	815	815	0	0
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tb.dut.tlul_assert_device.gen_assert_final[189].noOutstandingReqsAtEndOfSim_A	0	0	815	815	0	0
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tb.dut.tlul_assert_device.gen_assert_final[193].noOutstandingReqsAtEndOfSim_A	0	0	815	815	0	0
tb.dut.tlul_assert_device.gen_assert_final[194].noOutstandingReqsAtEndOfSim_A	0	0	815	815	0	0
tb.dut.tlul_assert_device.gen_assert_final[195].noOutstandingReqsAtEndOfSim_A	0	0	815	815	0	0
tb.dut.tlul_assert_device.gen_assert_final[196].noOutstandingReqsAtEndOfSim_A	0	0	815	815	0	0
tb.dut.tlul_assert_device.gen_assert_final[197].noOutstandingReqsAtEndOfSim_A	0	0	815	815	0	0
tb.dut.tlul_assert_device.gen_assert_final[198].noOutstandingReqsAtEndOfSim_A	0	0	815	815	0	0
tb.dut.tlul_assert_device.gen_assert_final[199].noOutstandingReqsAtEndOfSim_A	0	0	815	815	0	0

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	ASSERT	PROPERTIES	SEQUENCES
Total	1279	0	10
Category 0	1279	0	10

	ASSERT	PROPERTIES	SEQUENCES
Total	1279	0	10
Severity 0	1279	0	10

	NUMBER	PERCENT
Total Number	1279	100.00
Uncovered	31	2.42
Success	1248	97.58
Failure	0	0.00
Incomplete	49	3.83
Without Attempts	0	0.00

	NUMBER	PERCENT
Total Number	10	100.00
Uncovered	6	60.00
All Matches	4	40.00
First Matches	4	40.00