Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.31	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	1	43	97.73

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	1	43	97.73	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	206	1			T1	1		T16	1		T30	1
index[0x1]	172	1			T1	1		T66	1		T15	3
index[0x2]	183	1			T1	1		T4	1		T8	1
index[0x3]	202	1			T1	3		T4	18		T5	1

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	271	1			T1	1		T4	6		T16	5
lens_less_than_1000[1]	137	1			T1	2		T4	1		T5	1
lens_less_than_1000[2]	89	1			T1	1		T4	2		T30	1
lens_less_than_1000[3]	65	1			T4	1		T8	1		T21	1
lens_less_than_1000[4]	55	1			T1	1		T4	8		T21	1
lens_less_than_1000[5]	42	1			T4	1		T15	4		T64	1
lens_less_than_1000[6]	29	1			T27	2		T83	1		T10	1
lens_less_than_1000[7]	38	1			T1	1		T17	1		T22	2
lens_less_than_1000[8]	24	1			T67	1		T79	1		T260	1
lens_less_than_1000[9]	3	1			T96	1		T261	1		T105	1
len_2	10	1			T10	1		T262	1		T263	2

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	1	43	97.73	1

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x1]]	[lens_less_than_1000[9]]	0	1	1

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	62	1			T16	1		T22	1		T122	1
index[0x0]	lens_less_than_1000[1]	33	1			T1	1		T64	1		T19	2
index[0x0]	lens_less_than_1000[2]	27	1			T30	1		T27	1		T230	1
index[0x0]	lens_less_than_1000[3]	19	1			T264	1		T97	1		T108	2
index[0x0]	lens_less_than_1000[4]	13	1			T119	1		T124	1		T187	1
index[0x0]	lens_less_than_1000[5]	18	1			T10	4		T72	1		T265	1
index[0x0]	lens_less_than_1000[6]	10	1			T27	2		T113	1		T75	1
index[0x0]	lens_less_than_1000[7]	7	1			T22	1		T51	1		T108	2
index[0x0]	lens_less_than_1000[8]	11	1			T79	1		T107	8		T266	1
index[0x0]	lens_less_than_1000[9]	1	1			T105	1		-	-		-	-
index[0x0]	len_2	5	1			T262	1		T263	1		T267	1
index[0x1]	lens_less_than_1000[0]	43	1			T15	1		T22	2		T122	2
index[0x1]	lens_less_than_1000[1]	36	1			T61	1		T27	1		T268	1
index[0x1]	lens_less_than_1000[2]	23	1			T1	1		T66	1		T269	1
index[0x1]	lens_less_than_1000[3]	15	1			T21	1		T232	1		T265	1
index[0x1]	lens_less_than_1000[4]	15	1			T45	1		T19	1		T119	1
index[0x1]	lens_less_than_1000[5]	8	1			T15	2		T43	1		T113	1
index[0x1]	lens_less_than_1000[6]	7	1			T113	1		T270	1		T271	1
index[0x1]	lens_less_than_1000[7]	15	1			T22	1		T45	1		T33	11
index[0x1]	lens_less_than_1000[8]	8	1			T107	8		-	-		-	-
index[0x1]	len_2	2	1			T263	1		T272	1		-	-
index[0x2]	lens_less_than_1000[0]	76	1			T16	4		T56	1		T22	2
index[0x2]	lens_less_than_1000[1]	29	1			T83	1		T45	2		T94	1
index[0x2]	lens_less_than_1000[2]	26	1			T15	3		T237	1		T19	1
index[0x2]	lens_less_than_1000[3]	17	1			T8	1		T122	2		T67	1
index[0x2]	lens_less_than_1000[4]	5	1			T64	1		T266	1		T41	1
index[0x2]	lens_less_than_1000[5]	10	1			T4	1		T64	1		T74	1
index[0x2]	lens_less_than_1000[6]	9	1			T72	2		T35	7		-	-
index[0x2]	lens_less_than_1000[7]	6	1			T1	1		T108	1		T273	1
index[0x2]	lens_less_than_1000[8]	2	1			T67	1		T274	1		-	-
index[0x2]	lens_less_than_1000[9]	1	1			T96	1		-	-		-	-
index[0x2]	len_2	2	1			T10	1		T275	1		-	-
index[0x3]	lens_less_than_1000[0]	90	1			T1	1		T4	6		T22	5
index[0x3]	lens_less_than_1000[1]	39	1			T1	1		T4	1		T5	1
index[0x3]	lens_less_than_1000[2]	13	1			T4	2		T276	1		T108	2
index[0x3]	lens_less_than_1000[3]	14	1			T4	1		T277	1		T45	1
index[0x3]	lens_less_than_1000[4]	22	1			T1	1		T4	8		T21	1
index[0x3]	lens_less_than_1000[5]	6	1			T15	2		T90	1		T110	1
index[0x3]	lens_less_than_1000[6]	3	1			T83	1		T10	1		T271	1
index[0x3]	lens_less_than_1000[7]	10	1			T17	1		T49	2		T27	3
index[0x3]	lens_less_than_1000[8]	3	1			T260	1		T267	1		T278	1
index[0x3]	lens_less_than_1000[9]	1	1			T261	1		-	-		-	-
index[0x3]	len_2	1	1			T279	1		-	-		-	-