Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.15	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	1	39	97.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	1	39	97.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	61	1			T1	1		T65	1		T45	2
class_index[0x1]	52	1			T30	1		T87	1		T43	2
class_index[0x2]	59	1			T1	1		T16	1		T20	1
class_index[0x3]	63	1			T16	1		T89	2		T28	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	98	1			T1	1		T65	1		T16	1
intr_timeout_cnt[1]	53	1			T30	1		T91	1		T43	1
intr_timeout_cnt[2]	19	1			T28	1		T83	1		T19	1
intr_timeout_cnt[3]	18	1			T16	1		T43	1		T97	1
intr_timeout_cnt[4]	12	1			T120	1		T34	2		T107	3
intr_timeout_cnt[5]	10	1			T43	1		T45	1		T51	1
intr_timeout_cnt[6]	7	1			T1	1		T94	1		T51	1
intr_timeout_cnt[7]	6	1			T99	1		T241	1		T110	2
intr_timeout_cnt[8]	5	1			T19	1		T99	1		T101	1
intr_timeout_cnt[9]	7	1			T242	1		T243	1		T108	2

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	1	39	97.50	1

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x1]]	[intr_timeout_cnt[6]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	27	1			T1	1		T65	1		T98	1
class_index[0x0]	intr_timeout_cnt[1]	14	1			T45	1		T107	1		T244	2
class_index[0x0]	intr_timeout_cnt[2]	2	1			T99	1		T244	1		-	-
class_index[0x0]	intr_timeout_cnt[3]	4	1			T34	1		T245	1		T41	1
class_index[0x0]	intr_timeout_cnt[4]	2	1			T246	1		T247	1		-	-
class_index[0x0]	intr_timeout_cnt[5]	4	1			T45	1		T100	1		T243	1
class_index[0x0]	intr_timeout_cnt[6]	3	1			T94	1		T51	1		T34	1
class_index[0x0]	intr_timeout_cnt[7]	1	1			T241	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[8]	2	1			T101	1		T110	1		-	-
class_index[0x0]	intr_timeout_cnt[9]	2	1			T108	2		-	-		-	-
class_index[0x1]	intr_timeout_cnt[0]	24	1			T87	1		T43	1		T31	1
class_index[0x1]	intr_timeout_cnt[1]	14	1			T30	1		T43	1		T84	1
class_index[0x1]	intr_timeout_cnt[2]	3	1			T95	1		T248	1		T249	1
class_index[0x1]	intr_timeout_cnt[3]	3	1			T97	1		T35	1		T250	1
class_index[0x1]	intr_timeout_cnt[4]	2	1			T34	2		-	-		-	-
class_index[0x1]	intr_timeout_cnt[5]	2	1			T51	1		T251	1		-	-
class_index[0x1]	intr_timeout_cnt[7]	1	1			T99	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[8]	1	1			T19	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[9]	2	1			T107	2		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	20	1			T20	1		T91	1		T45	1
class_index[0x2]	intr_timeout_cnt[1]	12	1			T91	1		T98	1		T79	1
class_index[0x2]	intr_timeout_cnt[2]	8	1			T83	1		T19	1		T119	1
class_index[0x2]	intr_timeout_cnt[3]	6	1			T16	1		T43	1		T98	1
class_index[0x2]	intr_timeout_cnt[4]	6	1			T120	1		T107	3		T201	2
class_index[0x2]	intr_timeout_cnt[5]	1	1			T52	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[6]	1	1			T1	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[7]	3	1			T110	2		T252	1		-	-
class_index[0x2]	intr_timeout_cnt[8]	1	1			T108	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[9]	1	1			T242	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	27	1			T16	1		T89	2		T91	1
class_index[0x3]	intr_timeout_cnt[1]	13	1			T45	2		T9	1		T96	1
class_index[0x3]	intr_timeout_cnt[2]	6	1			T28	1		T95	2		T110	1
class_index[0x3]	intr_timeout_cnt[3]	5	1			T253	1		T254	1		T201	1
class_index[0x3]	intr_timeout_cnt[4]	2	1			T255	1		T256	1		-	-
class_index[0x3]	intr_timeout_cnt[5]	3	1			T43	1		T257	1		T255	1
class_index[0x3]	intr_timeout_cnt[6]	3	1			T108	2		T258	1		-	-
class_index[0x3]	intr_timeout_cnt[7]	1	1			T259	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[8]	1	1			T99	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[9]	2	1			T243	1		T248	1		-	-