Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	318727	1			T1	1817		T3	19		T4	455
all_values[1]	318727	1			T1	1817		T3	19		T4	455
all_values[2]	318727	1			T1	1817		T3	19		T4	455
all_values[3]	318727	1			T1	1817		T3	19		T4	455

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

633249

1

T1

3557

T4

937

T5

89

auto[1]

641659

1

T1

3711

T3

76

T4

883

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

765983

1

T1

4596

T3

66

T4

1514

auto[1]

508925

1

T1

2672

T3

10

T4

306

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	91000	1			T1	490		T4	124		T5	8
all_values[0]	auto[0]	auto[1]	67303	1			T1	378		T4	120		T5	8
all_values[0]	auto[1]	auto[0]	92535	1			T1	529		T3	16		T4	106
all_values[0]	auto[1]	auto[1]	67889	1			T1	420		T3	3		T4	105
all_values[1]	auto[0]	auto[0]	96038	1			T1	605		T4	201		T5	25
all_values[1]	auto[0]	auto[1]	61924	1			T1	307		T4	11		T8	8
all_values[1]	auto[1]	auto[0]	98193	1			T1	584		T3	18		T4	227
all_values[1]	auto[1]	auto[1]	62572	1			T1	321		T3	1		T4	16
all_values[2]	auto[0]	auto[0]	96507	1			T1	535		T4	216		T5	17
all_values[2]	auto[0]	auto[1]	61865	1			T1	324		T4	11		T8	10
all_values[2]	auto[1]	auto[0]	98154	1			T1	583		T3	14		T4	212
all_values[2]	auto[1]	auto[1]	62201	1			T1	375		T3	5		T4	16
all_values[3]	auto[0]	auto[0]	96046	1			T1	641		T4	242		T5	31
all_values[3]	auto[0]	auto[1]	62566	1			T1	277		T4	12		T8	10
all_values[3]	auto[1]	auto[0]	97510	1			T1	629		T3	18		T4	186
all_values[3]	auto[1]	auto[1]	62605	1			T1	270		T3	1		T4	15