Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	318727	1			T1	1817		T3	19		T4	455
all_pins[1]	318727	1			T1	1817		T3	19		T4	455
all_pins[2]	318727	1			T1	1817		T3	19		T4	455
all_pins[3]	318727	1			T1	1817		T3	19		T4	455

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1019641	1			T1	5882		T3	66		T4	1668
values[0x1]	255267	1			T1	1386		T3	10		T4	152
transitions[0x0=>0x1]	170405	1			T1	928		T3	9		T4	125
transitions[0x1=>0x0]	170663	1			T1	929		T3	9		T4	125

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	250838	1			T1	1397		T3	16		T4	350
all_pins[0]	values[0x1]	67889	1			T1	420		T3	3		T4	105
all_pins[0]	transitions[0x0=>0x1]	67247	1			T1	416		T3	3		T4	105
all_pins[0]	transitions[0x1=>0x0]	62221	1			T1	267		T3	1		T4	15
all_pins[1]	values[0x0]	256155	1			T1	1496		T3	18		T4	439
all_pins[1]	values[0x1]	62572	1			T1	321		T3	1		T4	16
all_pins[1]	transitions[0x0=>0x1]	33965	1			T1	178		T4	8		T8	8
all_pins[1]	transitions[0x1=>0x0]	39282	1			T1	277		T3	2		T4	97
all_pins[2]	values[0x0]	256526	1			T1	1442		T3	14		T4	439
all_pins[2]	values[0x1]	62201	1			T1	375		T3	5		T4	16
all_pins[2]	transitions[0x0=>0x1]	34012	1			T1	204		T3	5		T4	5
all_pins[2]	transitions[0x1=>0x0]	34383	1			T1	150		T3	1		T4	5
all_pins[3]	values[0x0]	256122	1			T1	1547		T3	18		T4	440
all_pins[3]	values[0x1]	62605	1			T1	270		T3	1		T4	15
all_pins[3]	transitions[0x0=>0x1]	35181	1			T1	130		T3	1		T4	7
all_pins[3]	transitions[0x1=>0x0]	34777	1			T1	235		T3	5		T4	8