Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	269	1			T165	7		T167	4		T235	7
all_values[1]	269	1			T165	7		T167	4		T235	7
all_values[2]	269	1			T165	7		T167	4		T235	7
all_values[3]	269	1			T165	7		T167	4		T235	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

578

1

T165

16

T167

8

T235

15

auto[1]

498

1

T165

12

T167

8

T235

13

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

431

1

T165

9

T167

9

T235

7

auto[1]

645

1

T165

19

T167

7

T235

21

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

639

1

T165

16

T167

11

T235

14

auto[1]

437

1

T165

12

T167

5

T235

14

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

63

1

T165

1

T167

4

T328

2

all_values[0]

auto[0]

auto[0]

auto[1]

25

1

T165

3

T235

3

T328

1

all_values[0]

auto[0]

auto[1]

auto[0]

38

1

T329

1

T330

1

T331

2

all_values[0]

auto[0]

auto[1]

auto[1]

31

1

T236

2

T332

1

T333

1

all_values[0]

auto[1]

auto[0]

auto[1]

74

1

T165

3

T235

3

T236

1

all_values[0]

auto[1]

auto[1]

auto[1]

38

1

T235

1

T236

1

T328

1

all_values[1]

auto[0]

auto[0]

auto[0]

63

1

T165

1

T235

1

T236

1

all_values[1]

auto[0]

auto[0]

auto[1]

24

1

T235

1

T333

1

T334

3

all_values[1]

auto[0]

auto[1]

auto[0]

62

1

T165

2

T167

2

T235

3

all_values[1]

auto[0]

auto[1]

auto[1]

21

1

T165

1

T236

1

T328

1

all_values[1]

auto[1]

auto[0]

auto[1]

53

1

T167

1

T236

1

T328

2

all_values[1]

auto[1]

auto[1]

auto[1]

46

1

T165

3

T167

1

T235

2

all_values[2]

auto[0]

auto[0]

auto[0]

54

1

T165

2

T235

1

T236

2

all_values[2]

auto[0]

auto[0]

auto[1]

24

1

T335

1

T330

2

T336

2

all_values[2]

auto[0]

auto[1]

auto[0]

51

1

T165

1

T235

1

T328

1

all_values[2]

auto[0]

auto[1]

auto[1]

27

1

T165

1

T167

2

T235

1

all_values[2]

auto[1]

auto[0]

auto[1]

63

1

T165

2

T167

1

T235

2

all_values[2]

auto[1]

auto[1]

auto[1]

50

1

T165

1

T167

1

T235

2

all_values[3]

auto[0]

auto[0]

auto[0]

51

1

T165

2

T167

1

T236

1

all_values[3]

auto[0]

auto[0]

auto[1]

28

1

T165

1

T235

1

T236

1

all_values[3]

auto[0]

auto[1]

auto[0]

49

1

T167

2

T235

1

T328

1

all_values[3]

auto[0]

auto[1]

auto[1]

28

1

T165

1

T235

1

T332

2

all_values[3]

auto[1]

auto[0]

auto[1]

56

1

T165

1

T167

1

T235

3

all_values[3]

auto[1]

auto[1]

auto[1]

57

1

T165

2

T235

1

T236

1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal