Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	83603	1			T16	509		T56	472		T15	73
accum_cnt_1000	205563	1			T1	106		T4	237		T7	1195
accum_cnt_100	24807	1			T1	67		T4	42		T7	66
accum_cnt_50	51877	1			T1	138		T4	45		T8	25
accum_cnt_10	165607	1			T1	296		T3	4		T4	62
accum_cnt_0	364755	1			T1	4505		T3	48		T4	1010

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	235752	1			T1	1278		T3	13		T4	349
class_index[0x1]	235752	1			T1	1278		T3	13		T4	349
class_index[0x2]	235752	1			T1	1278		T3	13		T4	349
class_index[0x3]	235752	1			T1	1278		T3	13		T4	349

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	23512	1			T22	139		T49	631		T90	487
class_index[0x0]	accum_cnt_1000	52493	1			T1	82		T4	237		T16	36
class_index[0x0]	accum_cnt_100	6099	1			T1	11		T4	42		T16	43
class_index[0x0]	accum_cnt_50	13930	1			T1	17		T4	32		T55	3
class_index[0x0]	accum_cnt_10	46727	1			T1	170		T4	20		T5	23
class_index[0x0]	accum_cnt_0	76749	1			T1	998		T3	13		T4	18
class_index[0x1]	accum_cnt_2000	20824	1			T16	210		T15	73		T60	405
class_index[0x1]	accum_cnt_1000	54151	1			T1	17		T7	1195		T25	1004
class_index[0x1]	accum_cnt_100	5451	1			T1	31		T7	66		T25	70
class_index[0x1]	accum_cnt_50	13773	1			T1	32		T7	62		T25	57
class_index[0x1]	accum_cnt_10	41702	1			T1	76		T3	4		T4	7
class_index[0x1]	accum_cnt_0	90757	1			T1	1122		T3	9		T4	342
class_index[0x2]	accum_cnt_2000	20231	1			T16	251		T56	222		T60	636
class_index[0x2]	accum_cnt_1000	46164	1			T16	266		T30	12		T56	478
class_index[0x2]	accum_cnt_100	6048	1			T16	28		T30	18		T56	22
class_index[0x2]	accum_cnt_50	13648	1			T4	13		T7	1329		T16	56
class_index[0x2]	accum_cnt_10	35409	1			T1	22		T4	13		T8	28
class_index[0x2]	accum_cnt_0	99313	1			T1	1256		T3	13		T4	323
class_index[0x3]	accum_cnt_2000	19036	1			T16	48		T56	250		T63	239
class_index[0x3]	accum_cnt_1000	52755	1			T1	7		T16	519		T48	2
class_index[0x3]	accum_cnt_100	7209	1			T1	25		T16	48		T48	30
class_index[0x3]	accum_cnt_50	10526	1			T1	89		T8	25		T16	95
class_index[0x3]	accum_cnt_10	41769	1			T1	28		T4	22		T8	3
class_index[0x3]	accum_cnt_0	97936	1			T1	1129		T3	13		T4	327