Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	2317	1			T4	225		T16	25		T54	1
alert[0x1]	2105	1			T15	2		T59	1		T90	45
alert[0x2]	5333	1			T4	1		T6	1		T15	32
alert[0x3]	10244	1			T16	22		T63	129		T90	38
alert[0x4]	9512	1			T15	6		T61	1		T22	19
alert[0x5]	4101	1			T4	7		T6	1		T90	389
alert[0x6]	3029	1			T4	24		T63	381		T62	1
alert[0x7]	8925	1			T7	1		T16	198		T54	3
alert[0x8]	9320	1			T16	2		T15	1		T63	16
alert[0x9]	9752	1			T54	1		T22	429		T283	2
alert[0xa]	4775	1			T6	1		T63	26		T62	2
alert[0xb]	6380	1			T1	4		T4	1		T16	87
alert[0xc]	1659	1			T16	11		T83	3		T90	12
alert[0xd]	4247	1			T1	77		T22	10		T63	100
alert[0xe]	4134	1			T1	1		T16	6		T15	8
alert[0xf]	7321	1			T3	1		T4	1		T6	1
alert[0x10]	5312	1			T16	775		T22	522		T90	22
alert[0x11]	11729	1			T4	31		T16	15		T54	1
alert[0x12]	4289	1			T16	5		T15	19		T59	1
alert[0x13]	1995	1			T4	4		T63	21		T90	52
alert[0x14]	7282	1			T7	1		T54	1		T15	504
alert[0x15]	8863	1			T59	1		T80	1		T62	1
alert[0x16]	5344	1			T4	1		T90	17		T283	1
alert[0x17]	2310	1			T3	1		T4	4		T16	6
alert[0x18]	5389	1			T4	1		T6	1		T16	8
alert[0x19]	8043	1			T62	1		T283	1		T128	8
alert[0x1a]	3956	1			T15	69		T63	17		T90	18
alert[0x1b]	7760	1			T61	1		T22	3		T70	1
alert[0x1c]	10529	1			T59	1		T90	11		T283	1
alert[0x1d]	8316	1			T119	2		T284	3		T10	458
alert[0x1e]	5722	1			T4	2		T15	29		T90	211
alert[0x1f]	3945	1			T16	269		T54	1		T90	26
alert[0x20]	5125	1			T54	1		T15	2		T90	66
alert[0x21]	9476	1			T4	11		T6	1		T83	2
alert[0x22]	3720	1			T1	73		T16	1		T54	1
alert[0x23]	8672	1			T15	12		T22	63		T29	1
alert[0x24]	2977	1			T54	1		T15	17		T61	1
alert[0x25]	4225	1			T15	2		T62	1		T29	1
alert[0x26]	4873	1			T1	1		T4	1		T16	737
alert[0x27]	2506	1			T54	1		T61	1		T22	18
alert[0x28]	6608	1			T4	2		T16	102		T80	1
alert[0x29]	3604	1			T4	21		T16	80		T63	16
alert[0x2a]	8725	1			T6	2		T15	149		T63	408
alert[0x2b]	8417	1			T4	14		T16	89		T15	10
alert[0x2c]	7184	1			T6	1		T7	1		T15	13
alert[0x2d]	4436	1			T7	1		T54	1		T43	1
alert[0x2e]	3761	1			T1	1		T4	5		T16	89
alert[0x2f]	5661	1			T6	2		T59	1		T22	175
alert[0x30]	5340	1			T1	6		T19	2		T9	197
alert[0x31]	7956	1			T61	2		T62	1		T90	271
alert[0x32]	2943	1			T16	14		T54	1		T15	2
alert[0x33]	5088	1			T4	3		T16	50		T59	1
alert[0x34]	3898	1			T16	121		T59	1		T63	10
alert[0x35]	6946	1			T1	218		T3	1		T16	13
alert[0x36]	10627	1			T3	1		T15	187		T128	15
alert[0x37]	7777	1			T3	1		T15	12		T59	1
alert[0x38]	8118	1			T4	1		T15	16		T63	236
alert[0x39]	9019	1			T4	6		T22	115		T90	91
alert[0x3a]	5891	1			T16	70		T15	8		T22	40
alert[0x3b]	5329	1			T16	9		T15	9		T63	31
alert[0x3c]	6714	1			T1	5		T63	271		T90	660
alert[0x3d]	6449	1			T6	1		T15	152		T63	14
alert[0x3e]	9452	1			T16	8		T63	259		T83	1
alert[0x3f]	4818	1			T1	5		T6	1		T16	68
alert[0x40]	10175	1			T16	578		T62	1		T29	1

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	93798	1			T1	178		T4	343		T6	9
class_i[0x1]	90964	1			T1	193		T4	20		T6	1
class_i[0x2]	152971	1			T1	20		T3	5		T4	3
class_i[0x3]	62715	1			T6	2		T16	17		T54	1

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

399719

1

T1

391

T4

366

T16

3465

alert_ping_fail

729

1

T3

5

T6

13

T7

4

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	2309	1			T4	225		T16	25		T15	34
alert_integrity_fail	alert[0x1]	2094	1			T15	2		T90	45		T67	66
alert_integrity_fail	alert[0x2]	5326	1			T4	1		T15	32		T90	144
alert_integrity_fail	alert[0x3]	10238	1			T16	22		T63	129		T90	38
alert_integrity_fail	alert[0x4]	9504	1			T15	6		T22	19		T63	67
alert_integrity_fail	alert[0x5]	4089	1			T4	7		T90	389		T45	85
alert_integrity_fail	alert[0x6]	3021	1			T4	24		T63	381		T90	43
alert_integrity_fail	alert[0x7]	8904	1			T16	198		T15	173		T128	86
alert_integrity_fail	alert[0x8]	9301	1			T16	2		T15	1		T63	16
alert_integrity_fail	alert[0x9]	9740	1			T22	429		T128	114		T43	1
alert_integrity_fail	alert[0xa]	4763	1			T63	26		T128	100		T45	66
alert_integrity_fail	alert[0xb]	6371	1			T1	4		T4	1		T16	87
alert_integrity_fail	alert[0xc]	1652	1			T16	11		T83	3		T90	12
alert_integrity_fail	alert[0xd]	4234	1			T1	77		T22	10		T63	100
alert_integrity_fail	alert[0xe]	4124	1			T1	1		T16	6		T15	8
alert_integrity_fail	alert[0xf]	7313	1			T4	1		T16	7		T15	160
alert_integrity_fail	alert[0x10]	5296	1			T16	775		T22	522		T90	22
alert_integrity_fail	alert[0x11]	11719	1			T4	31		T16	15		T15	3
alert_integrity_fail	alert[0x12]	4279	1			T16	5		T15	19		T128	38
alert_integrity_fail	alert[0x13]	1983	1			T4	4		T63	21		T90	52
alert_integrity_fail	alert[0x14]	7266	1			T15	504		T63	1717		T90	51
alert_integrity_fail	alert[0x15]	8852	1			T45	266		T98	10		T285	63
alert_integrity_fail	alert[0x16]	5333	1			T4	1		T90	17		T67	9
alert_integrity_fail	alert[0x17]	2294	1			T4	4		T16	6		T15	13
alert_integrity_fail	alert[0x18]	5378	1			T4	1		T16	8		T63	21
alert_integrity_fail	alert[0x19]	8036	1			T128	8		T67	14		T45	47
alert_integrity_fail	alert[0x1a]	3944	1			T15	69		T63	17		T90	18
alert_integrity_fail	alert[0x1b]	7752	1			T22	3		T70	1		T9	67
alert_integrity_fail	alert[0x1c]	10510	1			T90	11		T67	61		T9	35
alert_integrity_fail	alert[0x1d]	8306	1			T119	2		T10	458		T72	6
alert_integrity_fail	alert[0x1e]	5715	1			T4	2		T15	29		T90	211
alert_integrity_fail	alert[0x1f]	3928	1			T16	269		T90	26		T285	5
alert_integrity_fail	alert[0x20]	5117	1			T15	2		T90	66		T128	37
alert_integrity_fail	alert[0x21]	9465	1			T4	11		T83	2		T90	1169
alert_integrity_fail	alert[0x22]	3711	1			T1	73		T16	1		T15	16
alert_integrity_fail	alert[0x23]	8664	1			T15	12		T22	63		T128	23
alert_integrity_fail	alert[0x24]	2965	1			T15	17		T90	37		T9	34
alert_integrity_fail	alert[0x25]	4211	1			T15	2		T128	4		T67	33
alert_integrity_fail	alert[0x26]	4864	1			T1	1		T4	1		T16	737
alert_integrity_fail	alert[0x27]	2498	1			T22	18		T63	114		T45	62
alert_integrity_fail	alert[0x28]	6596	1			T4	2		T16	102		T83	6
alert_integrity_fail	alert[0x29]	3595	1			T4	21		T16	80		T63	16
alert_integrity_fail	alert[0x2a]	8710	1			T15	149		T63	408		T128	155
alert_integrity_fail	alert[0x2b]	8401	1			T4	14		T16	89		T15	10
alert_integrity_fail	alert[0x2c]	7169	1			T15	13		T22	64		T90	3
alert_integrity_fail	alert[0x2d]	4424	1			T43	1		T67	3		T45	44
alert_integrity_fail	alert[0x2e]	3744	1			T1	1		T4	5		T16	89
alert_integrity_fail	alert[0x2f]	5644	1			T22	175		T128	100		T43	1
alert_integrity_fail	alert[0x30]	5327	1			T1	6		T19	2		T9	197
alert_integrity_fail	alert[0x31]	7943	1			T90	271		T128	2872		T43	112
alert_integrity_fail	alert[0x32]	2935	1			T16	14		T15	2		T45	26
alert_integrity_fail	alert[0x33]	5075	1			T4	3		T16	50		T63	151
alert_integrity_fail	alert[0x34]	3887	1			T16	121		T63	10		T90	58
alert_integrity_fail	alert[0x35]	6937	1			T1	218		T16	13		T15	21
alert_integrity_fail	alert[0x36]	10616	1			T15	187		T128	15		T67	854
alert_integrity_fail	alert[0x37]	7764	1			T15	12		T63	252		T128	13
alert_integrity_fail	alert[0x38]	8112	1			T4	1		T15	16		T63	236
alert_integrity_fail	alert[0x39]	9005	1			T4	6		T22	115		T90	91
alert_integrity_fail	alert[0x3a]	5879	1			T16	70		T15	8		T22	40
alert_integrity_fail	alert[0x3b]	5323	1			T16	9		T15	9		T63	31
alert_integrity_fail	alert[0x3c]	6705	1			T1	5		T63	271		T90	660
alert_integrity_fail	alert[0x3d]	6439	1			T15	152		T63	14		T90	11
alert_integrity_fail	alert[0x3e]	9443	1			T16	8		T63	259		T83	1
alert_integrity_fail	alert[0x3f]	4810	1			T1	5		T16	68		T15	8
alert_integrity_fail	alert[0x40]	10167	1			T16	578		T67	525		T45	1005
alert_ping_fail	alert[0x0]	8	1			T54	1		T284	1		T286	1
alert_ping_fail	alert[0x1]	11	1			T59	1		T287	1		T288	1
alert_ping_fail	alert[0x2]	7	1			T6	1		T286	1		T261	1
alert_ping_fail	alert[0x3]	6	1			T122	1		T287	1		T289	1
alert_ping_fail	alert[0x4]	8	1			T61	1		T62	1		T290	1
alert_ping_fail	alert[0x5]	12	1			T6	1		T291	1		T292	1
alert_ping_fail	alert[0x6]	8	1			T62	1		T261	1		T293	1
alert_ping_fail	alert[0x7]	21	1			T7	1		T54	3		T59	1
alert_ping_fail	alert[0x8]	19	1			T62	1		T122	1		T288	1
alert_ping_fail	alert[0x9]	12	1			T54	1		T283	2		T234	1
alert_ping_fail	alert[0xa]	12	1			T6	1		T62	2		T234	1
alert_ping_fail	alert[0xb]	9	1			T294	1		T295	2		T296	1
alert_ping_fail	alert[0xc]	7	1			T283	1		T288	1		T294	1
alert_ping_fail	alert[0xd]	13	1			T283	2		T287	1		T284	1
alert_ping_fail	alert[0xe]	10	1			T288	2		T286	1		T109	1
alert_ping_fail	alert[0xf]	8	1			T3	1		T6	1		T62	1
alert_ping_fail	alert[0x10]	16	1			T283	1		T284	1		T288	2
alert_ping_fail	alert[0x11]	10	1			T54	1		T287	1		T286	2
alert_ping_fail	alert[0x12]	10	1			T59	1		T297	1		T290	1
alert_ping_fail	alert[0x13]	12	1			T283	1		T297	1		T288	1
alert_ping_fail	alert[0x14]	16	1			T7	1		T54	1		T297	1
alert_ping_fail	alert[0x15]	11	1			T59	1		T80	1		T62	1
alert_ping_fail	alert[0x16]	11	1			T283	1		T284	1		T298	1
alert_ping_fail	alert[0x17]	16	1			T3	1		T54	1		T297	1
alert_ping_fail	alert[0x18]	11	1			T6	1		T54	2		T29	1
alert_ping_fail	alert[0x19]	7	1			T62	1		T283	1		T299	2
alert_ping_fail	alert[0x1a]	12	1			T29	1		T286	1		T261	1
alert_ping_fail	alert[0x1b]	8	1			T61	1		T297	1		T292	1
alert_ping_fail	alert[0x1c]	19	1			T59	1		T283	1		T300	1
alert_ping_fail	alert[0x1d]	10	1			T284	3		T261	1		T189	1
alert_ping_fail	alert[0x1e]	7	1			T284	1		T301	1		T299	1
alert_ping_fail	alert[0x1f]	17	1			T54	1		T297	1		T284	1
alert_ping_fail	alert[0x20]	8	1			T54	1		T284	1		T288	1
alert_ping_fail	alert[0x21]	11	1			T6	1		T122	1		T286	1
alert_ping_fail	alert[0x22]	9	1			T54	1		T62	1		T234	2
alert_ping_fail	alert[0x23]	8	1			T29	1		T189	1		T302	2
alert_ping_fail	alert[0x24]	12	1			T54	1		T61	1		T301	1
alert_ping_fail	alert[0x25]	14	1			T62	1		T29	1		T234	1
alert_ping_fail	alert[0x26]	9	1			T29	1		T297	2		T299	1
alert_ping_fail	alert[0x27]	8	1			T54	1		T61	1		T303	2
alert_ping_fail	alert[0x28]	12	1			T80	1		T283	1		T301	1
alert_ping_fail	alert[0x29]	9	1			T62	1		T234	1		T288	1
alert_ping_fail	alert[0x2a]	15	1			T6	2		T300	1		T234	1
alert_ping_fail	alert[0x2b]	16	1			T29	1		T234	1		T287	1
alert_ping_fail	alert[0x2c]	15	1			T6	1		T7	1		T283	1
alert_ping_fail	alert[0x2d]	12	1			T7	1		T54	1		T234	1
alert_ping_fail	alert[0x2e]	17	1			T54	2		T62	1		T280	1
alert_ping_fail	alert[0x2f]	17	1			T6	2		T59	1		T234	1
alert_ping_fail	alert[0x30]	13	1			T298	1		T301	1		T109	1
alert_ping_fail	alert[0x31]	13	1			T61	2		T62	1		T297	1
alert_ping_fail	alert[0x32]	8	1			T54	1		T59	1		T234	1
alert_ping_fail	alert[0x33]	13	1			T59	1		T234	1		T284	2
alert_ping_fail	alert[0x34]	11	1			T59	1		T283	2		T288	1
alert_ping_fail	alert[0x35]	9	1			T3	1		T29	1		T288	1
alert_ping_fail	alert[0x36]	11	1			T3	1		T287	1		T288	1
alert_ping_fail	alert[0x37]	13	1			T3	1		T59	1		T234	1
alert_ping_fail	alert[0x38]	6	1			T283	1		T288	1		T286	1
alert_ping_fail	alert[0x39]	14	1			T288	1		T301	2		T299	1
alert_ping_fail	alert[0x3a]	12	1			T122	1		T283	1		T300	1
alert_ping_fail	alert[0x3b]	6	1			T283	1		T304	1		T305	1
alert_ping_fail	alert[0x3c]	9	1			T283	2		T292	1		T304	1
alert_ping_fail	alert[0x3d]	10	1			T6	1		T62	1		T283	1
alert_ping_fail	alert[0x3e]	9	1			T286	1		T109	1		T289	2
alert_ping_fail	alert[0x3f]	8	1			T6	1		T287	1		T284	1
alert_ping_fail	alert[0x40]	8	1			T62	1		T29	1		T234	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	93605	1			T1	178		T4	343		T16	35
alert_integrity_fail	class_i[0x1]	90761	1			T1	193		T4	20		T16	3413
alert_integrity_fail	class_i[0x2]	152812	1			T1	20		T4	3		T15	61
alert_integrity_fail	class_i[0x3]	62541	1			T16	17		T83	13		T43	178
alert_ping_fail	class_i[0x0]	193	1			T6	9		T59	1		T61	2
alert_ping_fail	class_i[0x1]	203	1			T6	1		T7	4		T59	8
alert_ping_fail	class_i[0x2]	159	1			T3	5		T6	1		T54	18
alert_ping_fail	class_i[0x3]	174	1			T6	2		T54	1		T59	1