Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.57 99.86 98.49 89.17 91.94 99.81 97.13 99.60


Total test records in report: 815
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T158 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3385658128 Apr 23 03:01:04 PM PDT 24 Apr 23 03:10:54 PM PDT 24 5004899080 ps
T764 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.2430115349 Apr 23 03:01:24 PM PDT 24 Apr 23 03:01:26 PM PDT 24 9409484 ps
T765 /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.602583188 Apr 23 03:00:31 PM PDT 24 Apr 23 03:05:16 PM PDT 24 8563051924 ps
T766 /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.1803708415 Apr 23 03:02:28 PM PDT 24 Apr 23 03:02:30 PM PDT 24 11065700 ps
T767 /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.3202658574 Apr 23 03:01:53 PM PDT 24 Apr 23 03:02:04 PM PDT 24 82632181 ps
T768 /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.4259584613 Apr 23 03:02:20 PM PDT 24 Apr 23 03:02:22 PM PDT 24 10089216 ps
T769 /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.1966550505 Apr 23 03:01:23 PM PDT 24 Apr 23 03:01:29 PM PDT 24 417894037 ps
T174 /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.4174952403 Apr 23 03:01:28 PM PDT 24 Apr 23 03:01:31 PM PDT 24 43118334 ps
T770 /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.2221475124 Apr 23 03:02:10 PM PDT 24 Apr 23 03:02:12 PM PDT 24 9737037 ps
T157 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.734484867 Apr 23 03:01:23 PM PDT 24 Apr 23 03:19:10 PM PDT 24 56491388354 ps
T342 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.3984679404 Apr 23 03:00:00 PM PDT 24 Apr 23 03:09:54 PM PDT 24 16096646907 ps
T771 /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.797928057 Apr 23 03:01:43 PM PDT 24 Apr 23 03:02:04 PM PDT 24 696281671 ps
T772 /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.2012885913 Apr 23 03:01:08 PM PDT 24 Apr 23 03:01:11 PM PDT 24 132064557 ps
T773 /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.2871405430 Apr 23 03:02:25 PM PDT 24 Apr 23 03:02:27 PM PDT 24 9530742 ps
T774 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.2848630910 Apr 23 03:01:35 PM PDT 24 Apr 23 03:07:08 PM PDT 24 8985389705 ps
T775 /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.1100220107 Apr 23 03:02:22 PM PDT 24 Apr 23 03:02:24 PM PDT 24 9806897 ps
T776 /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.1865752282 Apr 23 03:01:19 PM PDT 24 Apr 23 03:01:46 PM PDT 24 500912220 ps
T777 /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.1572930602 Apr 23 03:01:45 PM PDT 24 Apr 23 03:01:52 PM PDT 24 186813041 ps
T343 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.3114675892 Apr 23 03:00:20 PM PDT 24 Apr 23 03:09:44 PM PDT 24 6597088216 ps
T778 /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.1167040184 Apr 23 02:59:59 PM PDT 24 Apr 23 03:00:14 PM PDT 24 407819295 ps
T168 /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.1523077056 Apr 23 03:01:57 PM PDT 24 Apr 23 03:02:00 PM PDT 24 39571234 ps
T779 /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.3767316058 Apr 23 03:01:24 PM PDT 24 Apr 23 03:01:33 PM PDT 24 379957565 ps
T780 /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.928616810 Apr 23 03:01:12 PM PDT 24 Apr 23 03:01:26 PM PDT 24 100796555 ps
T781 /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.3562388903 Apr 23 03:02:11 PM PDT 24 Apr 23 03:02:18 PM PDT 24 120336742 ps
T169 /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.568347389 Apr 23 02:59:59 PM PDT 24 Apr 23 03:00:25 PM PDT 24 158449683 ps
T151 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.651513408 Apr 23 03:01:16 PM PDT 24 Apr 23 03:07:34 PM PDT 24 5922352106 ps
T782 /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.135712050 Apr 23 03:01:53 PM PDT 24 Apr 23 03:01:55 PM PDT 24 18453226 ps
T783 /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.4245890156 Apr 23 03:00:52 PM PDT 24 Apr 23 03:00:56 PM PDT 24 71812357 ps
T784 /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.237041482 Apr 23 03:02:18 PM PDT 24 Apr 23 03:02:20 PM PDT 24 8197506 ps
T153 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3364648119 Apr 23 03:01:49 PM PDT 24 Apr 23 03:05:09 PM PDT 24 2217577515 ps
T785 /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.1683955013 Apr 23 03:01:57 PM PDT 24 Apr 23 03:01:59 PM PDT 24 13523758 ps
T786 /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.2900990988 Apr 23 03:01:22 PM PDT 24 Apr 23 03:02:05 PM PDT 24 13474075852 ps
T787 /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.3627012608 Apr 23 03:01:45 PM PDT 24 Apr 23 03:01:58 PM PDT 24 156351794 ps
T788 /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.3105304763 Apr 23 03:02:30 PM PDT 24 Apr 23 03:02:32 PM PDT 24 7691890 ps
T789 /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.3908563767 Apr 23 03:00:32 PM PDT 24 Apr 23 03:00:37 PM PDT 24 190291236 ps
T790 /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.250749261 Apr 23 03:01:34 PM PDT 24 Apr 23 03:01:39 PM PDT 24 34276421 ps
T791 /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.1437480485 Apr 23 03:00:06 PM PDT 24 Apr 23 03:00:12 PM PDT 24 253926826 ps
T792 /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.3661636829 Apr 23 03:00:59 PM PDT 24 Apr 23 03:01:01 PM PDT 24 8535858 ps
T793 /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.311527558 Apr 23 03:02:07 PM PDT 24 Apr 23 03:02:13 PM PDT 24 177245190 ps
T161 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.373230686 Apr 23 03:01:34 PM PDT 24 Apr 23 03:04:40 PM PDT 24 8326952608 ps
T794 /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.122661727 Apr 23 03:01:06 PM PDT 24 Apr 23 03:02:00 PM PDT 24 2633546696 ps
T795 /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.4181643743 Apr 23 03:01:52 PM PDT 24 Apr 23 03:02:46 PM PDT 24 707869050 ps
T796 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.1171581937 Apr 23 03:00:52 PM PDT 24 Apr 23 03:07:13 PM PDT 24 5495433616 ps
T797 /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.1303051827 Apr 23 03:01:24 PM PDT 24 Apr 23 03:01:32 PM PDT 24 51806159 ps
T798 /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.3304142528 Apr 23 03:01:52 PM PDT 24 Apr 23 03:01:59 PM PDT 24 84773012 ps
T799 /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.21847103 Apr 23 03:00:11 PM PDT 24 Apr 23 03:00:18 PM PDT 24 116702280 ps
T159 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.64493468 Apr 23 03:02:14 PM PDT 24 Apr 23 03:07:39 PM PDT 24 35142094067 ps
T800 /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.2963229625 Apr 23 03:02:28 PM PDT 24 Apr 23 03:02:30 PM PDT 24 11206742 ps
T801 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3460881144 Apr 23 03:02:01 PM PDT 24 Apr 23 03:08:11 PM PDT 24 4567861178 ps
T802 /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.445170828 Apr 23 03:02:34 PM PDT 24 Apr 23 03:02:36 PM PDT 24 13856109 ps
T803 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.2898999761 Apr 23 03:00:07 PM PDT 24 Apr 23 03:07:42 PM PDT 24 11929006697 ps
T804 /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1059952662 Apr 23 03:00:14 PM PDT 24 Apr 23 03:01:08 PM PDT 24 2641814799 ps
T805 /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.3815227357 Apr 23 03:01:59 PM PDT 24 Apr 23 03:02:26 PM PDT 24 340978517 ps
T806 /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.432362657 Apr 23 03:00:49 PM PDT 24 Apr 23 03:03:24 PM PDT 24 8364490360 ps
T807 /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.2862855125 Apr 23 03:01:47 PM PDT 24 Apr 23 03:01:49 PM PDT 24 6486870 ps
T808 /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.2101680058 Apr 23 03:01:59 PM PDT 24 Apr 23 03:02:05 PM PDT 24 457020889 ps
T160 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.978869259 Apr 23 03:02:07 PM PDT 24 Apr 23 03:06:57 PM PDT 24 69915606985 ps
T809 /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.3241991407 Apr 23 03:01:35 PM PDT 24 Apr 23 03:01:44 PM PDT 24 233354657 ps
T810 /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.3162622826 Apr 23 03:02:28 PM PDT 24 Apr 23 03:02:30 PM PDT 24 7378724 ps
T177 /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.3267683796 Apr 23 03:00:26 PM PDT 24 Apr 23 03:00:29 PM PDT 24 170596109 ps
T811 /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.386074385 Apr 23 03:02:18 PM PDT 24 Apr 23 03:02:20 PM PDT 24 11717506 ps
T812 /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.1815610831 Apr 23 03:01:03 PM PDT 24 Apr 23 03:01:15 PM PDT 24 264461184 ps
T813 /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.2291948288 Apr 23 03:02:01 PM PDT 24 Apr 23 03:02:12 PM PDT 24 870267280 ps
T814 /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.1956368185 Apr 23 03:01:53 PM PDT 24 Apr 23 03:01:59 PM PDT 24 61689874 ps
T815 /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.4096925977 Apr 23 03:00:23 PM PDT 24 Apr 23 03:00:37 PM PDT 24 335515715 ps

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.596905866
Short name T1
Test name
Test status
Simulation time 67236972834 ps
CPU time 4337.12 seconds
Started Apr 23 03:11:36 PM PDT 24
Finished Apr 23 04:23:54 PM PDT 24
Peak memory 306100 kb
Host smart-96ae5457-e331-4f5d-9790-2c397d6d761a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596905866 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.596905866
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.1370769718
Short name T16
Test name
Test status
Simulation time 73307428414 ps
CPU time 2159.6 seconds
Started Apr 23 03:07:46 PM PDT 24
Finished Apr 23 03:43:46 PM PDT 24
Peak memory 280968 kb
Host smart-b15d8840-cf4b-499a-bc81-788cb72fc33d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370769718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.1370769718
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.2668275307
Short name T140
Test name
Test status
Simulation time 34253072555 ps
CPU time 1314.96 seconds
Started Apr 23 03:01:47 PM PDT 24
Finished Apr 23 03:23:43 PM PDT 24
Peak memory 265368 kb
Host smart-eb95fd3e-1fd0-4463-90f0-378457f5a7e2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668275307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.2668275307
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.3382219274
Short name T2
Test name
Test status
Simulation time 518208830 ps
CPU time 23.61 seconds
Started Apr 23 03:03:19 PM PDT 24
Finished Apr 23 03:03:43 PM PDT 24
Peak memory 248664 kb
Host smart-d5719f59-7020-40b5-87fc-f94bd900ceaf
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3382219274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.3382219274
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.3113584196
Short name T35
Test name
Test status
Simulation time 97345282649 ps
CPU time 2874.37 seconds
Started Apr 23 03:13:14 PM PDT 24
Finished Apr 23 04:01:09 PM PDT 24
Peak memory 289616 kb
Host smart-270934b7-16df-4fe1-b616-c879300a531a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113584196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.3113584196
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.2134108344
Short name T162
Test name
Test status
Simulation time 613737794 ps
CPU time 20.16 seconds
Started Apr 23 03:00:54 PM PDT 24
Finished Apr 23 03:01:15 PM PDT 24
Peak memory 244972 kb
Host smart-9a3ef6ae-2a74-4112-9b39-3d3ee9ebf6e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2134108344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.2134108344
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.792284902
Short name T27
Test name
Test status
Simulation time 60649467210 ps
CPU time 1277.39 seconds
Started Apr 23 03:08:20 PM PDT 24
Finished Apr 23 03:29:38 PM PDT 24
Peak memory 285036 kb
Host smart-a8c5b233-df95-4588-bcf4-2bb345f9fc63
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792284902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_han
dler_stress_all.792284902
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.4237001102
Short name T306
Test name
Test status
Simulation time 62736357454 ps
CPU time 2811.7 seconds
Started Apr 23 03:07:15 PM PDT 24
Finished Apr 23 03:54:07 PM PDT 24
Peak memory 289140 kb
Host smart-cd118c1f-7c18-42ce-984c-696ee77b4dc0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237001102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.4237001102
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3904843259
Short name T134
Test name
Test status
Simulation time 1621697916 ps
CPU time 194.94 seconds
Started Apr 23 03:02:14 PM PDT 24
Finished Apr 23 03:05:30 PM PDT 24
Peak memory 265476 kb
Host smart-25e2af9c-d3c5-4cc6-bb87-a3cb3155e5ff
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3904843259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.3904843259
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.2775126847
Short name T4
Test name
Test status
Simulation time 92366834333 ps
CPU time 1739.18 seconds
Started Apr 23 03:04:27 PM PDT 24
Finished Apr 23 03:33:27 PM PDT 24
Peak memory 282584 kb
Host smart-58ccb3a5-8007-4048-be84-7ebbcede9080
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775126847 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.2775126847
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.3411575521
Short name T130
Test name
Test status
Simulation time 12213867485 ps
CPU time 1093.82 seconds
Started Apr 23 03:01:57 PM PDT 24
Finished Apr 23 03:20:11 PM PDT 24
Peak memory 265376 kb
Host smart-d267d54c-ab47-40a8-aaed-08185ace5f7d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411575521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.3411575521
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.4171118624
Short name T45
Test name
Test status
Simulation time 47243955894 ps
CPU time 2861.81 seconds
Started Apr 23 03:12:54 PM PDT 24
Finished Apr 23 04:00:36 PM PDT 24
Peak memory 289160 kb
Host smart-095935f2-e7ee-45c4-b429-f1c0e5cfcafe
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171118624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.4171118624
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.4062057678
Short name T122
Test name
Test status
Simulation time 6975032288 ps
CPU time 86.35 seconds
Started Apr 23 03:10:32 PM PDT 24
Finished Apr 23 03:11:59 PM PDT 24
Peak memory 248672 kb
Host smart-12da742a-8596-4be5-88da-a9e29a38bcd2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062057678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.4062057678
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.212255765
Short name T145
Test name
Test status
Simulation time 4280049896 ps
CPU time 315.84 seconds
Started Apr 23 03:01:02 PM PDT 24
Finished Apr 23 03:06:18 PM PDT 24
Peak memory 265264 kb
Host smart-3b28638d-ed22-46c1-949b-379c9eec18f2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=212255765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_error
s.212255765
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.2414240592
Short name T42
Test name
Test status
Simulation time 88650970049 ps
CPU time 1949.74 seconds
Started Apr 23 03:03:02 PM PDT 24
Finished Apr 23 03:35:32 PM PDT 24
Peak memory 289184 kb
Host smart-1c3873e8-004e-4614-928f-404f47021057
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414240592 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.2414240592
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.412071562
Short name T17
Test name
Test status
Simulation time 291228267251 ps
CPU time 2922.87 seconds
Started Apr 23 03:03:01 PM PDT 24
Finished Apr 23 03:51:45 PM PDT 24
Peak memory 287196 kb
Host smart-469b377f-a301-4f42-9d1a-9d16b422235d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412071562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.412071562
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.101028840
Short name T141
Test name
Test status
Simulation time 82601221103 ps
CPU time 1080.13 seconds
Started Apr 23 03:01:53 PM PDT 24
Finished Apr 23 03:19:54 PM PDT 24
Peak memory 265432 kb
Host smart-7f8ddae3-b277-44dc-990a-717d6278c94f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101028840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.101028840
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.1327706082
Short name T165
Test name
Test status
Simulation time 11045538 ps
CPU time 1.32 seconds
Started Apr 23 03:02:17 PM PDT 24
Finished Apr 23 03:02:19 PM PDT 24
Peak memory 236656 kb
Host smart-8a513cd2-bc6b-4b34-8a8b-93cfbef2f75a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1327706082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.1327706082
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.3197111635
Short name T283
Test name
Test status
Simulation time 25332841975 ps
CPU time 522.76 seconds
Started Apr 23 03:05:25 PM PDT 24
Finished Apr 23 03:14:08 PM PDT 24
Peak memory 246744 kb
Host smart-1da88120-4355-46d1-8990-7e3f0e7f5afe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197111635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.3197111635
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.2215702942
Short name T10
Test name
Test status
Simulation time 342952457320 ps
CPU time 2825.98 seconds
Started Apr 23 03:13:26 PM PDT 24
Finished Apr 23 04:00:32 PM PDT 24
Peak memory 301404 kb
Host smart-3b47b079-b60f-44d0-abd2-3868102dc91b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215702942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.2215702942
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.889148736
Short name T54
Test name
Test status
Simulation time 50581185079 ps
CPU time 508.36 seconds
Started Apr 23 03:03:54 PM PDT 24
Finished Apr 23 03:12:23 PM PDT 24
Peak memory 247552 kb
Host smart-9b1b6be5-3c89-450c-ac7b-019380d9bc84
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889148736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.889148736
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.1941192532
Short name T147
Test name
Test status
Simulation time 9916293231 ps
CPU time 715.83 seconds
Started Apr 23 03:01:37 PM PDT 24
Finished Apr 23 03:13:33 PM PDT 24
Peak memory 265508 kb
Host smart-a22b13fa-963b-4a9a-a120-9c7063cb4b6a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941192532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.1941192532
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.1765404264
Short name T313
Test name
Test status
Simulation time 40827461850 ps
CPU time 2156.47 seconds
Started Apr 23 03:08:33 PM PDT 24
Finished Apr 23 03:44:30 PM PDT 24
Peak memory 289144 kb
Host smart-ca350c57-b67a-4eda-821e-07659609af3a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765404264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.1765404264
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.974951259
Short name T107
Test name
Test status
Simulation time 211299693403 ps
CPU time 7132.81 seconds
Started Apr 23 03:10:26 PM PDT 24
Finished Apr 23 05:09:20 PM PDT 24
Peak memory 386352 kb
Host smart-958a764e-058e-413d-8ed7-63b85d7230a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974951259 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.974951259
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.1501742225
Short name T261
Test name
Test status
Simulation time 14319735473 ps
CPU time 600.04 seconds
Started Apr 23 03:07:13 PM PDT 24
Finished Apr 23 03:17:13 PM PDT 24
Peak memory 247376 kb
Host smart-4ebad7b0-4185-4d48-9c4c-69b0c9598b8a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501742225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.1501742225
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.2149473778
Short name T309
Test name
Test status
Simulation time 164570466543 ps
CPU time 2398.87 seconds
Started Apr 23 03:08:05 PM PDT 24
Finished Apr 23 03:48:05 PM PDT 24
Peak memory 288816 kb
Host smart-2cc2ad05-da01-4d36-a9f8-27be5fd54094
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149473778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.2149473778
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.734484867
Short name T157
Test name
Test status
Simulation time 56491388354 ps
CPU time 1066.24 seconds
Started Apr 23 03:01:23 PM PDT 24
Finished Apr 23 03:19:10 PM PDT 24
Peak memory 265348 kb
Host smart-cd1fb0c4-8212-4d2b-a104-845e4399ef95
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734484867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.734484867
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.2701433395
Short name T99
Test name
Test status
Simulation time 60608261092 ps
CPU time 1514.45 seconds
Started Apr 23 03:05:28 PM PDT 24
Finished Apr 23 03:30:43 PM PDT 24
Peak memory 289132 kb
Host smart-1853bf6c-5460-40b9-bb1c-ccda7a18c559
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701433395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.2701433395
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3385658128
Short name T158
Test name
Test status
Simulation time 5004899080 ps
CPU time 589.75 seconds
Started Apr 23 03:01:04 PM PDT 24
Finished Apr 23 03:10:54 PM PDT 24
Peak memory 273252 kb
Host smart-a3255e74-ee99-4cc1-aa11-c894d2efcbfb
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385658128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.3385658128
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.1113523360
Short name T22
Test name
Test status
Simulation time 78034815666 ps
CPU time 4555.29 seconds
Started Apr 23 03:13:51 PM PDT 24
Finished Apr 23 04:29:47 PM PDT 24
Peak memory 306108 kb
Host smart-72f83524-6d66-4edf-86be-13fd22c2ae44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113523360 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.1113523360
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.1640789411
Short name T467
Test name
Test status
Simulation time 10555641380 ps
CPU time 401.34 seconds
Started Apr 23 03:04:43 PM PDT 24
Finished Apr 23 03:11:24 PM PDT 24
Peak memory 247352 kb
Host smart-4a6ce9b9-684f-439b-ba72-054b1b13cc3d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640789411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.1640789411
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.1624570350
Short name T312
Test name
Test status
Simulation time 76005689203 ps
CPU time 1808.39 seconds
Started Apr 23 03:03:50 PM PDT 24
Finished Apr 23 03:33:59 PM PDT 24
Peak memory 288860 kb
Host smart-6ba8cb4e-67f8-4723-9930-0cd41d242fc0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624570350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.1624570350
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.3296754224
Short name T34
Test name
Test status
Simulation time 308283285707 ps
CPU time 3748.18 seconds
Started Apr 23 03:06:59 PM PDT 24
Finished Apr 23 04:09:28 PM PDT 24
Peak memory 306188 kb
Host smart-396f8e3e-c9a7-4043-a266-ac22eaba1af3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296754224 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.3296754224
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.359569842
Short name T723
Test name
Test status
Simulation time 14248254 ps
CPU time 1.41 seconds
Started Apr 23 03:02:25 PM PDT 24
Finished Apr 23 03:02:27 PM PDT 24
Peak memory 236688 kb
Host smart-85d0c4ba-0fba-4430-9810-6b2e22d3c124
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=359569842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.359569842
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.1848825783
Short name T234
Test name
Test status
Simulation time 11777837387 ps
CPU time 490.28 seconds
Started Apr 23 03:05:45 PM PDT 24
Finished Apr 23 03:13:55 PM PDT 24
Peak memory 247360 kb
Host smart-f902f8be-c05c-4bed-83cf-d76a4bbe9075
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848825783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.1848825783
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.1990654897
Short name T108
Test name
Test status
Simulation time 154884685791 ps
CPU time 2243.9 seconds
Started Apr 23 03:13:39 PM PDT 24
Finished Apr 23 03:51:04 PM PDT 24
Peak memory 285024 kb
Host smart-fc9f00bb-4177-4e96-bb3b-6b028d781440
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990654897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.1990654897
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.2879576217
Short name T149
Test name
Test status
Simulation time 3399262569 ps
CPU time 121.63 seconds
Started Apr 23 03:00:23 PM PDT 24
Finished Apr 23 03:02:25 PM PDT 24
Peak memory 257116 kb
Host smart-41868b05-94d4-4a33-a24b-a48fdd4d6a73
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2879576217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.2879576217
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.1861224721
Short name T110
Test name
Test status
Simulation time 24159065240 ps
CPU time 410.99 seconds
Started Apr 23 03:12:33 PM PDT 24
Finished Apr 23 03:19:24 PM PDT 24
Peak memory 255888 kb
Host smart-b78c3331-22d9-42d4-804d-698d10c34f05
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861224721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.1861224721
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.2257802106
Short name T36
Test name
Test status
Simulation time 118845531464 ps
CPU time 1755.56 seconds
Started Apr 23 03:03:41 PM PDT 24
Finished Apr 23 03:32:57 PM PDT 24
Peak memory 288804 kb
Host smart-10c72c42-d95c-4ca9-8ab4-faa965c9a96b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257802106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.2257802106
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.2300851265
Short name T41
Test name
Test status
Simulation time 62448744907 ps
CPU time 1605 seconds
Started Apr 23 03:11:42 PM PDT 24
Finished Apr 23 03:38:27 PM PDT 24
Peak memory 289356 kb
Host smart-b57c3d04-80c4-494b-9b1a-e54850a8a9fa
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300851265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.2300851265
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.1222248438
Short name T137
Test name
Test status
Simulation time 18514535554 ps
CPU time 355.73 seconds
Started Apr 23 03:01:19 PM PDT 24
Finished Apr 23 03:07:15 PM PDT 24
Peak memory 266228 kb
Host smart-5e21a47c-c176-4e28-ac89-775ff8f62b2b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1222248438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.1222248438
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.862836439
Short name T296
Test name
Test status
Simulation time 29200162665 ps
CPU time 562.36 seconds
Started Apr 23 03:04:33 PM PDT 24
Finished Apr 23 03:13:56 PM PDT 24
Peak memory 248300 kb
Host smart-ca67d6cb-b321-4a9f-b8e0-c56bb38acdc5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862836439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.862836439
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.2116491106
Short name T321
Test name
Test status
Simulation time 13255271158 ps
CPU time 1266.26 seconds
Started Apr 23 03:05:01 PM PDT 24
Finished Apr 23 03:26:08 PM PDT 24
Peak memory 282452 kb
Host smart-46db75f6-c92c-4ee1-b022-33cc4bca2cef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116491106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.2116491106
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.2393609267
Short name T259
Test name
Test status
Simulation time 37783011270 ps
CPU time 2170.41 seconds
Started Apr 23 03:08:33 PM PDT 24
Finished Apr 23 03:44:44 PM PDT 24
Peak memory 273232 kb
Host smart-09e62d7f-5b6f-4829-a0cb-fa3c0ee2543e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393609267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.2393609267
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.2391031473
Short name T267
Test name
Test status
Simulation time 73432391958 ps
CPU time 2113.59 seconds
Started Apr 23 03:03:18 PM PDT 24
Finished Apr 23 03:38:32 PM PDT 24
Peak memory 281528 kb
Host smart-a957b981-2b60-447f-b2c8-3d097c50a813
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391031473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.2391031473
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.1216106140
Short name T317
Test name
Test status
Simulation time 151106016736 ps
CPU time 2537.65 seconds
Started Apr 23 03:12:29 PM PDT 24
Finished Apr 23 03:54:47 PM PDT 24
Peak memory 289244 kb
Host smart-9e78d28c-831a-4e60-96a0-30b6d4ad18c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216106140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.1216106140
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.2753627528
Short name T178
Test name
Test status
Simulation time 573745973 ps
CPU time 36.7 seconds
Started Apr 23 03:00:11 PM PDT 24
Finished Apr 23 03:00:48 PM PDT 24
Peak memory 236864 kb
Host smart-60272794-e65e-4d64-9a54-99eb8431a75c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2753627528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.2753627528
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.2988014949
Short name T208
Test name
Test status
Simulation time 35261592 ps
CPU time 3.3 seconds
Started Apr 23 03:02:39 PM PDT 24
Finished Apr 23 03:02:43 PM PDT 24
Peak memory 248816 kb
Host smart-dd58871d-1762-4705-98b5-7f459723155f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2988014949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.2988014949
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.3094792766
Short name T216
Test name
Test status
Simulation time 13619256 ps
CPU time 2.68 seconds
Started Apr 23 03:02:53 PM PDT 24
Finished Apr 23 03:02:56 PM PDT 24
Peak memory 248816 kb
Host smart-c99e9fee-8736-4516-961d-5f7445cf44cc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3094792766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.3094792766
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.2646044201
Short name T82
Test name
Test status
Simulation time 142634522 ps
CPU time 3.22 seconds
Started Apr 23 03:05:19 PM PDT 24
Finished Apr 23 03:05:22 PM PDT 24
Peak memory 248760 kb
Host smart-9064f30f-83b6-415f-a336-5ec83be9abcc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2646044201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.2646044201
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.1073942364
Short name T206
Test name
Test status
Simulation time 109253184 ps
CPU time 3.22 seconds
Started Apr 23 03:05:28 PM PDT 24
Finished Apr 23 03:05:31 PM PDT 24
Peak memory 248800 kb
Host smart-a8434496-4330-4a40-9306-c0c6a75fa6c2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1073942364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.1073942364
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.4251509929
Short name T341
Test name
Test status
Simulation time 2120531455 ps
CPU time 394.3 seconds
Started Apr 23 03:02:07 PM PDT 24
Finished Apr 23 03:08:42 PM PDT 24
Peak memory 268832 kb
Host smart-535bb314-9ddb-4db1-852d-9ff37d250d6a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251509929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.4251509929
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.3660530910
Short name T255
Test name
Test status
Simulation time 6720105952 ps
CPU time 30.38 seconds
Started Apr 23 03:04:41 PM PDT 24
Finished Apr 23 03:05:12 PM PDT 24
Peak memory 255096 kb
Host smart-d3b47284-a742-440a-aeff-4ee081c6292f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36605
30910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.3660530910
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.4235115942
Short name T64
Test name
Test status
Simulation time 52255846976 ps
CPU time 1108.32 seconds
Started Apr 23 03:05:45 PM PDT 24
Finished Apr 23 03:24:14 PM PDT 24
Peak memory 272180 kb
Host smart-d7e8fd71-0fca-4209-b78a-b5a4dec38070
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235115942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.4235115942
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.2051874851
Short name T248
Test name
Test status
Simulation time 80844097561 ps
CPU time 2720.92 seconds
Started Apr 23 03:02:57 PM PDT 24
Finished Apr 23 03:48:19 PM PDT 24
Peak memory 289060 kb
Host smart-6a7da8b6-0a34-4b50-958d-98d403187d0b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051874851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.2051874851
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.334397607
Short name T7
Test name
Test status
Simulation time 138942072133 ps
CPU time 2242.96 seconds
Started Apr 23 03:07:42 PM PDT 24
Finished Apr 23 03:45:05 PM PDT 24
Peak memory 288732 kb
Host smart-b9cd84eb-64f8-4e52-ac0d-d92a6b3cad11
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334397607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.334397607
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.1228098480
Short name T600
Test name
Test status
Simulation time 25468418379 ps
CPU time 253.38 seconds
Started Apr 23 03:09:54 PM PDT 24
Finished Apr 23 03:14:08 PM PDT 24
Peak memory 247640 kb
Host smart-1009a216-2b80-4042-92ef-21f9be7fbd8f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228098480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.1228098480
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.1523077056
Short name T168
Test name
Test status
Simulation time 39571234 ps
CPU time 3.35 seconds
Started Apr 23 03:01:57 PM PDT 24
Finished Apr 23 03:02:00 PM PDT 24
Peak memory 235676 kb
Host smart-4e70c93c-c5df-4c41-8251-ea0b5ca9d5f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1523077056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.1523077056
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3364648119
Short name T153
Test name
Test status
Simulation time 2217577515 ps
CPU time 199.76 seconds
Started Apr 23 03:01:49 PM PDT 24
Finished Apr 23 03:05:09 PM PDT 24
Peak memory 265316 kb
Host smart-837313cf-63c0-47a8-8288-637631412ed6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3364648119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.3364648119
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.1310762365
Short name T285
Test name
Test status
Simulation time 69087049377 ps
CPU time 1585.22 seconds
Started Apr 23 03:04:27 PM PDT 24
Finished Apr 23 03:30:52 PM PDT 24
Peak memory 288840 kb
Host smart-262f6f4f-2669-4a19-bcb0-a0fa105e153b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310762365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.1310762365
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.1404304131
Short name T136
Test name
Test status
Simulation time 5102522030 ps
CPU time 364.87 seconds
Started Apr 23 03:02:00 PM PDT 24
Finished Apr 23 03:08:05 PM PDT 24
Peak memory 265368 kb
Host smart-877c3420-34b4-4b7e-8479-8ce1b1d019b1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1404304131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.1404304131
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.2146050290
Short name T53
Test name
Test status
Simulation time 47007217504 ps
CPU time 2322.04 seconds
Started Apr 23 03:06:09 PM PDT 24
Finished Apr 23 03:44:52 PM PDT 24
Peak memory 304744 kb
Host smart-fa95d61a-7700-4874-ae8d-378022dec680
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146050290 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.2146050290
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.3950976262
Short name T331
Test name
Test status
Simulation time 7681530 ps
CPU time 1.38 seconds
Started Apr 23 03:01:53 PM PDT 24
Finished Apr 23 03:01:54 PM PDT 24
Peak memory 236664 kb
Host smart-ce5d88b1-4c16-4ca3-bb88-1ac539db3f23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3950976262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.3950976262
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.3692069303
Short name T274
Test name
Test status
Simulation time 80636018126 ps
CPU time 1587.87 seconds
Started Apr 23 03:05:06 PM PDT 24
Finished Apr 23 03:31:34 PM PDT 24
Peak memory 288916 kb
Host smart-3e598b4e-a405-4153-bbc0-7c4073a6be00
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692069303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.3692069303
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.3947943894
Short name T105
Test name
Test status
Simulation time 852120170 ps
CPU time 52.98 seconds
Started Apr 23 03:05:18 PM PDT 24
Finished Apr 23 03:06:11 PM PDT 24
Peak memory 255608 kb
Host smart-dd10b93c-e8ce-407a-98b1-ae560644c95c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39479
43894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.3947943894
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.1927097853
Short name T448
Test name
Test status
Simulation time 10836666301 ps
CPU time 452.57 seconds
Started Apr 23 03:06:24 PM PDT 24
Finished Apr 23 03:13:57 PM PDT 24
Peak memory 247556 kb
Host smart-fe285d2a-e8a8-4734-95b7-800af0d781b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927097853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.1927097853
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.733888727
Short name T52
Test name
Test status
Simulation time 81374190691 ps
CPU time 1970.91 seconds
Started Apr 23 03:07:32 PM PDT 24
Finished Apr 23 03:40:23 PM PDT 24
Peak memory 304908 kb
Host smart-9fb7d8dc-1923-4694-9751-f72c23ff843a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733888727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_han
dler_stress_all.733888727
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.674566512
Short name T246
Test name
Test status
Simulation time 348692627983 ps
CPU time 6706.91 seconds
Started Apr 23 03:07:48 PM PDT 24
Finished Apr 23 04:59:36 PM PDT 24
Peak memory 321096 kb
Host smart-65345a1d-acb4-4cde-82e3-33a1f72bfa5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674566512 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.674566512
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.1140780663
Short name T272
Test name
Test status
Simulation time 98703334919 ps
CPU time 2837.71 seconds
Started Apr 23 03:08:06 PM PDT 24
Finished Apr 23 03:55:24 PM PDT 24
Peak memory 286412 kb
Host smart-40a29011-b619-40c5-a0b4-50443fb58df1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140780663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.1140780663
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.1530496043
Short name T19
Test name
Test status
Simulation time 76338578662 ps
CPU time 2310.06 seconds
Started Apr 23 03:09:16 PM PDT 24
Finished Apr 23 03:47:46 PM PDT 24
Peak memory 288492 kb
Host smart-d0e92053-09ed-490d-847b-21504cc8c677
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530496043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.1530496043
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.2817667702
Short name T251
Test name
Test status
Simulation time 774390455 ps
CPU time 64.23 seconds
Started Apr 23 03:10:03 PM PDT 24
Finished Apr 23 03:11:07 PM PDT 24
Peak memory 247004 kb
Host smart-74904c00-e2cb-4f80-96d9-68db9131ce85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28176
67702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.2817667702
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.3098623284
Short name T242
Test name
Test status
Simulation time 531311193 ps
CPU time 40.96 seconds
Started Apr 23 03:10:45 PM PDT 24
Finished Apr 23 03:11:26 PM PDT 24
Peak memory 253624 kb
Host smart-97fe5e4a-a3ad-43af-a746-d941133ef1ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30986
23284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.3098623284
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.138661813
Short name T241
Test name
Test status
Simulation time 325334727 ps
CPU time 23.75 seconds
Started Apr 23 03:11:24 PM PDT 24
Finished Apr 23 03:11:48 PM PDT 24
Peak memory 248588 kb
Host smart-b8baa1c6-45a9-453a-a20c-5c1bfa0fb499
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13866
1813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.138661813
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.710818234
Short name T279
Test name
Test status
Simulation time 416071084384 ps
CPU time 3040.97 seconds
Started Apr 23 03:03:11 PM PDT 24
Finished Apr 23 03:53:53 PM PDT 24
Peak memory 288932 kb
Host smart-7c5569ca-6c41-4047-b4e0-e34649d82c21
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710818234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.710818234
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.2605852108
Short name T96
Test name
Test status
Simulation time 3951323096 ps
CPU time 35.39 seconds
Started Apr 23 03:13:33 PM PDT 24
Finished Apr 23 03:14:09 PM PDT 24
Peak memory 247612 kb
Host smart-85ed8e33-1d0c-442c-8554-9edc81daacb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26058
52108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.2605852108
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.4134224886
Short name T13
Test name
Test status
Simulation time 27153425663 ps
CPU time 1201.06 seconds
Started Apr 23 03:05:58 PM PDT 24
Finished Apr 23 03:25:59 PM PDT 24
Peak memory 287044 kb
Host smart-98859520-c2e7-4012-94f2-9d93ab29861e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134224886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.4134224886
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.4129959379
Short name T14
Test name
Test status
Simulation time 54355812790 ps
CPU time 1453.91 seconds
Started Apr 23 03:09:14 PM PDT 24
Finished Apr 23 03:33:28 PM PDT 24
Peak memory 288940 kb
Host smart-5d386b70-e24d-453f-a378-295277fe7692
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129959379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.4129959379
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.2339272356
Short name T39
Test name
Test status
Simulation time 46754258361 ps
CPU time 2331.48 seconds
Started Apr 23 03:04:03 PM PDT 24
Finished Apr 23 03:42:55 PM PDT 24
Peak memory 306140 kb
Host smart-6a5ab70d-3c9e-49c6-86c5-80130522cd77
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339272356 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.2339272356
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.3505844991
Short name T135
Test name
Test status
Simulation time 18196688371 ps
CPU time 331.64 seconds
Started Apr 23 03:01:43 PM PDT 24
Finished Apr 23 03:07:15 PM PDT 24
Peak memory 265300 kb
Host smart-5bd7dbd0-d16c-4a73-ad3f-900632fb427c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3505844991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.3505844991
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1785348877
Short name T171
Test name
Test status
Simulation time 594060317 ps
CPU time 62.32 seconds
Started Apr 23 03:01:33 PM PDT 24
Finished Apr 23 03:02:36 PM PDT 24
Peak memory 239456 kb
Host smart-19f12098-9e9a-43b5-a20b-4049dc47bb07
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1785348877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.1785348877
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.978869259
Short name T160
Test name
Test status
Simulation time 69915606985 ps
CPU time 289.47 seconds
Started Apr 23 03:02:07 PM PDT 24
Finished Apr 23 03:06:57 PM PDT 24
Peak memory 271408 kb
Host smart-c5717eb2-30b0-49a8-95a5-d6ae6c6dc399
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=978869259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_erro
rs.978869259
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.3550406743
Short name T173
Test name
Test status
Simulation time 2440835034 ps
CPU time 43.81 seconds
Started Apr 23 03:01:54 PM PDT 24
Finished Apr 23 03:02:38 PM PDT 24
Peak memory 239552 kb
Host smart-dac26624-c49e-4c25-91af-05213717c362
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3550406743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.3550406743
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.2862725558
Short name T175
Test name
Test status
Simulation time 63619605 ps
CPU time 3.68 seconds
Started Apr 23 03:02:05 PM PDT 24
Finished Apr 23 03:02:09 PM PDT 24
Peak memory 236572 kb
Host smart-003838c9-50e0-449a-8cc7-098c38537cba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2862725558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.2862725558
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.411838896
Short name T183
Test name
Test status
Simulation time 627442400 ps
CPU time 21.86 seconds
Started Apr 23 03:02:09 PM PDT 24
Finished Apr 23 03:02:32 PM PDT 24
Peak memory 239488 kb
Host smart-69254147-d4e0-423a-a43a-eabccc1b8417
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=411838896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.411838896
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.3031381419
Short name T144
Test name
Test status
Simulation time 3270018284 ps
CPU time 226.55 seconds
Started Apr 23 03:00:42 PM PDT 24
Finished Apr 23 03:04:29 PM PDT 24
Peak memory 270724 kb
Host smart-a4e2623a-0eb4-4914-848a-dc899c304386
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3031381419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.3031381419
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.3757704773
Short name T170
Test name
Test status
Simulation time 1774233125 ps
CPU time 32.87 seconds
Started Apr 23 03:01:23 PM PDT 24
Finished Apr 23 03:01:57 PM PDT 24
Peak memory 236928 kb
Host smart-2b1c77a8-4994-4a43-8e90-2c6b159a8860
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3757704773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.3757704773
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.4174952403
Short name T174
Test name
Test status
Simulation time 43118334 ps
CPU time 2.97 seconds
Started Apr 23 03:01:28 PM PDT 24
Finished Apr 23 03:01:31 PM PDT 24
Peak memory 236588 kb
Host smart-7f35fb95-dbb2-47a2-82bc-a89139ca8fd2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4174952403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.4174952403
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1657863430
Short name T163
Test name
Test status
Simulation time 93203799 ps
CPU time 5.96 seconds
Started Apr 23 03:01:52 PM PDT 24
Finished Apr 23 03:01:58 PM PDT 24
Peak memory 235720 kb
Host smart-b18048d0-b065-4b09-8b16-bc499a2475c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1657863430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.1657863430
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.553930804
Short name T182
Test name
Test status
Simulation time 65836432 ps
CPU time 3.14 seconds
Started Apr 23 03:02:19 PM PDT 24
Finished Apr 23 03:02:23 PM PDT 24
Peak memory 236644 kb
Host smart-9bd4a8bc-618e-4c4a-b191-92a329cdf789
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=553930804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.553930804
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.3267683796
Short name T177
Test name
Test status
Simulation time 170596109 ps
CPU time 2.21 seconds
Started Apr 23 03:00:26 PM PDT 24
Finished Apr 23 03:00:29 PM PDT 24
Peak memory 236452 kb
Host smart-03ca6676-ac12-4f8e-bace-93021b3d2337
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3267683796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.3267683796
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.2540392959
Short name T172
Test name
Test status
Simulation time 324029008 ps
CPU time 24.05 seconds
Started Apr 23 03:00:35 PM PDT 24
Finished Apr 23 03:00:59 PM PDT 24
Peak memory 240280 kb
Host smart-56f46e00-a5e3-49a4-bbb4-3ff190d09fe4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2540392959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.2540392959
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.903936537
Short name T164
Test name
Test status
Simulation time 54254585 ps
CPU time 2.07 seconds
Started Apr 23 03:00:42 PM PDT 24
Finished Apr 23 03:00:45 PM PDT 24
Peak memory 236740 kb
Host smart-b8e4804b-5969-40f7-b809-756ada5ddf87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=903936537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.903936537
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.4146517138
Short name T185
Test name
Test status
Simulation time 615886255 ps
CPU time 47.65 seconds
Started Apr 23 03:01:02 PM PDT 24
Finished Apr 23 03:01:50 PM PDT 24
Peak memory 245108 kb
Host smart-477c231d-930e-49e4-a110-8e6a8358123a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4146517138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.4146517138
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.1917251561
Short name T184
Test name
Test status
Simulation time 886276054 ps
CPU time 33.72 seconds
Started Apr 23 03:01:10 PM PDT 24
Finished Apr 23 03:01:44 PM PDT 24
Peak memory 239432 kb
Host smart-0eb9c2dd-f382-48cb-ba81-c8645663911f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1917251561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.1917251561
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.1525943289
Short name T176
Test name
Test status
Simulation time 39319566 ps
CPU time 3.53 seconds
Started Apr 23 03:01:11 PM PDT 24
Finished Apr 23 03:01:15 PM PDT 24
Peak memory 236740 kb
Host smart-b5dd2b9e-bd47-40b7-a11c-82ed49bd83e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1525943289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.1525943289
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.1569577717
Short name T738
Test name
Test status
Simulation time 6687532843 ps
CPU time 251.34 seconds
Started Apr 23 03:00:06 PM PDT 24
Finished Apr 23 03:04:18 PM PDT 24
Peak memory 238764 kb
Host smart-ca957a68-4f73-48b3-8664-e0c1b22822ed
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1569577717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.1569577717
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.2695556499
Short name T239
Test name
Test status
Simulation time 33708003486 ps
CPU time 215.82 seconds
Started Apr 23 03:00:07 PM PDT 24
Finished Apr 23 03:03:43 PM PDT 24
Peak memory 235864 kb
Host smart-0e09e964-0989-445f-b940-f05dcd0add59
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2695556499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.2695556499
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.1062998848
Short name T710
Test name
Test status
Simulation time 480728509 ps
CPU time 11.39 seconds
Started Apr 23 03:00:06 PM PDT 24
Finished Apr 23 03:00:18 PM PDT 24
Peak memory 240416 kb
Host smart-99814142-fff0-4a8a-b9a0-cddea95b592d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1062998848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.1062998848
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.127635474
Short name T744
Test name
Test status
Simulation time 384998216 ps
CPU time 8.37 seconds
Started Apr 23 03:00:07 PM PDT 24
Finished Apr 23 03:00:16 PM PDT 24
Peak memory 240448 kb
Host smart-220dc4eb-fcde-48b5-b104-b9df71dcd718
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127635474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.alert_handler_csr_mem_rw_with_rand_reset.127635474
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.1437480485
Short name T791
Test name
Test status
Simulation time 253926826 ps
CPU time 5.85 seconds
Started Apr 23 03:00:06 PM PDT 24
Finished Apr 23 03:00:12 PM PDT 24
Peak memory 236544 kb
Host smart-352c784b-7141-4775-8968-4b23f1d723f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1437480485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.1437480485
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.2807969486
Short name T705
Test name
Test status
Simulation time 53012896 ps
CPU time 1.38 seconds
Started Apr 23 02:59:59 PM PDT 24
Finished Apr 23 03:00:01 PM PDT 24
Peak memory 236536 kb
Host smart-ec036c37-c330-4f25-8a63-f8359fc16193
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2807969486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.2807969486
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.576958146
Short name T728
Test name
Test status
Simulation time 1133230163 ps
CPU time 19.23 seconds
Started Apr 23 03:00:07 PM PDT 24
Finished Apr 23 03:00:27 PM PDT 24
Peak memory 243888 kb
Host smart-21ce86ff-af6e-4a32-917c-a8f5992e22ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=576958146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_outs
tanding.576958146
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.2822331870
Short name T148
Test name
Test status
Simulation time 4056905709 ps
CPU time 175.95 seconds
Started Apr 23 02:59:59 PM PDT 24
Finished Apr 23 03:02:55 PM PDT 24
Peak memory 268452 kb
Host smart-cc79911b-df69-48c2-9476-54217cccf418
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2822331870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.2822331870
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.3984679404
Short name T342
Test name
Test status
Simulation time 16096646907 ps
CPU time 593.56 seconds
Started Apr 23 03:00:00 PM PDT 24
Finished Apr 23 03:09:54 PM PDT 24
Peak memory 265360 kb
Host smart-79ac6558-a5e5-4812-9edd-7a983bfdc4a0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984679404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.3984679404
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.1167040184
Short name T778
Test name
Test status
Simulation time 407819295 ps
CPU time 14.53 seconds
Started Apr 23 02:59:59 PM PDT 24
Finished Apr 23 03:00:14 PM PDT 24
Peak memory 248636 kb
Host smart-16d16c56-2c0a-4f5b-aeb5-6dd715234b95
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1167040184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.1167040184
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.568347389
Short name T169
Test name
Test status
Simulation time 158449683 ps
CPU time 25.5 seconds
Started Apr 23 02:59:59 PM PDT 24
Finished Apr 23 03:00:25 PM PDT 24
Peak memory 240356 kb
Host smart-72ee5374-0a33-419e-8908-3ae66b4bbe5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=568347389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.568347389
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.3418158061
Short name T199
Test name
Test status
Simulation time 7120157009 ps
CPU time 240.52 seconds
Started Apr 23 03:00:13 PM PDT 24
Finished Apr 23 03:04:14 PM PDT 24
Peak memory 240500 kb
Host smart-6ca15cac-6abe-41f5-9a66-c4d83cdf6d11
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3418158061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.3418158061
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.3542791113
Short name T721
Test name
Test status
Simulation time 27482369326 ps
CPU time 460.66 seconds
Started Apr 23 03:00:15 PM PDT 24
Finished Apr 23 03:07:56 PM PDT 24
Peak memory 235888 kb
Host smart-7e32e6c8-baf1-4f7c-8579-b96b7d088671
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3542791113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.3542791113
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.2830360477
Short name T719
Test name
Test status
Simulation time 22447151 ps
CPU time 4.21 seconds
Started Apr 23 03:00:12 PM PDT 24
Finished Apr 23 03:00:16 PM PDT 24
Peak memory 240308 kb
Host smart-1f947718-6d6c-4762-86bd-d4220dda8214
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2830360477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.2830360477
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.587887031
Short name T238
Test name
Test status
Simulation time 470533076 ps
CPU time 8.37 seconds
Started Apr 23 03:00:19 PM PDT 24
Finished Apr 23 03:00:28 PM PDT 24
Peak memory 238516 kb
Host smart-d28fb2af-01f5-424c-9534-4266fb68d650
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587887031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.alert_handler_csr_mem_rw_with_rand_reset.587887031
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.21847103
Short name T799
Test name
Test status
Simulation time 116702280 ps
CPU time 6.4 seconds
Started Apr 23 03:00:11 PM PDT 24
Finished Apr 23 03:00:18 PM PDT 24
Peak memory 236612 kb
Host smart-e77c486e-f544-450e-ad51-852b3016d6e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=21847103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.21847103
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.1820117635
Short name T737
Test name
Test status
Simulation time 8736835 ps
CPU time 1.6 seconds
Started Apr 23 03:00:10 PM PDT 24
Finished Apr 23 03:00:12 PM PDT 24
Peak memory 236664 kb
Host smart-210e0923-4e3b-4158-887c-dd97ff2e322b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1820117635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.1820117635
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1059952662
Short name T804
Test name
Test status
Simulation time 2641814799 ps
CPU time 53.91 seconds
Started Apr 23 03:00:14 PM PDT 24
Finished Apr 23 03:01:08 PM PDT 24
Peak memory 244896 kb
Host smart-a54c568b-8985-4aba-a17d-b2fadb9162d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1059952662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.1059952662
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.2116392179
Short name T150
Test name
Test status
Simulation time 2861487887 ps
CPU time 199.49 seconds
Started Apr 23 03:00:07 PM PDT 24
Finished Apr 23 03:03:27 PM PDT 24
Peak memory 265260 kb
Host smart-b18148bf-aebb-44ca-82a0-946a3f5729b5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2116392179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.2116392179
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.2898999761
Short name T803
Test name
Test status
Simulation time 11929006697 ps
CPU time 454.68 seconds
Started Apr 23 03:00:07 PM PDT 24
Finished Apr 23 03:07:42 PM PDT 24
Peak memory 265464 kb
Host smart-66576225-4cac-4155-bd54-4e952ba3e0ba
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898999761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.2898999761
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.1794093563
Short name T709
Test name
Test status
Simulation time 258852554 ps
CPU time 8.96 seconds
Started Apr 23 03:00:07 PM PDT 24
Finished Apr 23 03:00:16 PM PDT 24
Peak memory 248588 kb
Host smart-a42b0254-4cc8-446d-affa-3fee59775e3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1794093563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.1794093563
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.3241991407
Short name T809
Test name
Test status
Simulation time 233354657 ps
CPU time 8.73 seconds
Started Apr 23 03:01:35 PM PDT 24
Finished Apr 23 03:01:44 PM PDT 24
Peak memory 248648 kb
Host smart-e0da3491-bea1-4acd-bfc4-0aade2590a2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241991407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.3241991407
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.2062227901
Short name T722
Test name
Test status
Simulation time 179861019 ps
CPU time 8.06 seconds
Started Apr 23 03:01:31 PM PDT 24
Finished Apr 23 03:01:39 PM PDT 24
Peak memory 240360 kb
Host smart-fc243c8a-692f-45f9-a767-607bd2f27398
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2062227901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.2062227901
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.3192681139
Short name T727
Test name
Test status
Simulation time 17961937 ps
CPU time 1.26 seconds
Started Apr 23 03:01:30 PM PDT 24
Finished Apr 23 03:01:32 PM PDT 24
Peak memory 235736 kb
Host smart-c33ff876-c782-4be9-96e9-4bb025c1b49a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3192681139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.3192681139
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.3239207519
Short name T197
Test name
Test status
Simulation time 497661672 ps
CPU time 40.06 seconds
Started Apr 23 03:01:34 PM PDT 24
Finished Apr 23 03:02:15 PM PDT 24
Peak memory 243844 kb
Host smart-4d20b3a2-cf0b-4ac0-833d-9c9115e8199f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3239207519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.3239207519
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.1110540424
Short name T156
Test name
Test status
Simulation time 825471619 ps
CPU time 112.36 seconds
Started Apr 23 03:01:26 PM PDT 24
Finished Apr 23 03:03:19 PM PDT 24
Peak memory 265256 kb
Host smart-b34ed197-e0f5-49c0-b903-bf47879327f1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1110540424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.1110540424
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.3753968630
Short name T724
Test name
Test status
Simulation time 124876882 ps
CPU time 9.46 seconds
Started Apr 23 03:01:28 PM PDT 24
Finished Apr 23 03:01:38 PM PDT 24
Peak memory 252644 kb
Host smart-050ebc4e-8ce7-4052-a8f9-1d701b88e401
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3753968630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.3753968630
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.801253399
Short name T756
Test name
Test status
Simulation time 133747084 ps
CPU time 6.49 seconds
Started Apr 23 03:01:37 PM PDT 24
Finished Apr 23 03:01:44 PM PDT 24
Peak memory 256544 kb
Host smart-c886145c-036d-48f5-8f4c-11bc7ed74d45
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801253399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 11.alert_handler_csr_mem_rw_with_rand_reset.801253399
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.250749261
Short name T790
Test name
Test status
Simulation time 34276421 ps
CPU time 5.12 seconds
Started Apr 23 03:01:34 PM PDT 24
Finished Apr 23 03:01:39 PM PDT 24
Peak memory 236604 kb
Host smart-c3512e72-10ce-44f3-a006-19abd32ca9df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=250749261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.250749261
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.194621615
Short name T755
Test name
Test status
Simulation time 14774634 ps
CPU time 1.24 seconds
Started Apr 23 03:01:35 PM PDT 24
Finished Apr 23 03:01:36 PM PDT 24
Peak memory 234736 kb
Host smart-dd5ddeaf-2071-47e3-8cba-05f2d0cccdc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=194621615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.194621615
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.1040368132
Short name T701
Test name
Test status
Simulation time 234868752 ps
CPU time 12.07 seconds
Started Apr 23 03:01:35 PM PDT 24
Finished Apr 23 03:01:48 PM PDT 24
Peak memory 244812 kb
Host smart-8c91258b-9707-492e-9dfa-288f2221c8c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1040368132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.1040368132
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.373230686
Short name T161
Test name
Test status
Simulation time 8326952608 ps
CPU time 185.31 seconds
Started Apr 23 03:01:34 PM PDT 24
Finished Apr 23 03:04:40 PM PDT 24
Peak memory 265436 kb
Host smart-5277347c-a6ce-4509-9578-e54ac856cedd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=373230686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_erro
rs.373230686
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.2848630910
Short name T774
Test name
Test status
Simulation time 8985389705 ps
CPU time 332.78 seconds
Started Apr 23 03:01:35 PM PDT 24
Finished Apr 23 03:07:08 PM PDT 24
Peak memory 265456 kb
Host smart-0e7ba613-8ef3-4fb5-aa1c-c7ae87276a68
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848630910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.2848630910
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.1881487888
Short name T712
Test name
Test status
Simulation time 267249419 ps
CPU time 6.64 seconds
Started Apr 23 03:01:36 PM PDT 24
Finished Apr 23 03:01:43 PM PDT 24
Peak memory 248628 kb
Host smart-e1b2509a-1cb2-4a25-8a91-dcad6f4385c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1881487888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.1881487888
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.3627012608
Short name T787
Test name
Test status
Simulation time 156351794 ps
CPU time 12.05 seconds
Started Apr 23 03:01:45 PM PDT 24
Finished Apr 23 03:01:58 PM PDT 24
Peak memory 250824 kb
Host smart-3ed6a2d0-263a-490d-b163-9be1bdbfed58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627012608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.3627012608
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.3527246989
Short name T196
Test name
Test status
Simulation time 453796401 ps
CPU time 9.45 seconds
Started Apr 23 03:01:46 PM PDT 24
Finished Apr 23 03:01:55 PM PDT 24
Peak memory 236584 kb
Host smart-a7a88a42-8f9a-473e-9da7-8dd53031eb05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3527246989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.3527246989
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.3685317090
Short name T333
Test name
Test status
Simulation time 12869279 ps
CPU time 1.26 seconds
Started Apr 23 03:01:44 PM PDT 24
Finished Apr 23 03:01:45 PM PDT 24
Peak memory 236628 kb
Host smart-116585ed-7602-4021-a130-8fa34cbdef6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3685317090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.3685317090
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.797928057
Short name T771
Test name
Test status
Simulation time 696281671 ps
CPU time 21.09 seconds
Started Apr 23 03:01:43 PM PDT 24
Finished Apr 23 03:02:04 PM PDT 24
Peak memory 240412 kb
Host smart-a152499e-e9ab-45a2-91c4-90ced6d34326
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=797928057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_out
standing.797928057
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.3769812628
Short name T132
Test name
Test status
Simulation time 2229381080 ps
CPU time 157.44 seconds
Started Apr 23 03:01:39 PM PDT 24
Finished Apr 23 03:04:17 PM PDT 24
Peak memory 265324 kb
Host smart-cd3de70f-03d7-42b2-a15e-219af19c5634
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3769812628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.3769812628
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.666465295
Short name T740
Test name
Test status
Simulation time 404358414 ps
CPU time 10.39 seconds
Started Apr 23 03:01:39 PM PDT 24
Finished Apr 23 03:01:50 PM PDT 24
Peak memory 247584 kb
Host smart-e997e330-cb49-40c7-9281-daa5e2df33f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=666465295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.666465295
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.350229632
Short name T717
Test name
Test status
Simulation time 53580526 ps
CPU time 2.07 seconds
Started Apr 23 03:01:42 PM PDT 24
Finished Apr 23 03:01:44 PM PDT 24
Peak memory 236764 kb
Host smart-8ea07baa-3565-442c-ba4e-cbedbfb9b61a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=350229632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.350229632
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.785928732
Short name T706
Test name
Test status
Simulation time 151937911 ps
CPU time 8.31 seconds
Started Apr 23 03:01:47 PM PDT 24
Finished Apr 23 03:01:55 PM PDT 24
Peak memory 239692 kb
Host smart-bfec7bcc-c324-43d7-acf9-5bb369693d3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785928732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.alert_handler_csr_mem_rw_with_rand_reset.785928732
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.1572930602
Short name T777
Test name
Test status
Simulation time 186813041 ps
CPU time 7.19 seconds
Started Apr 23 03:01:45 PM PDT 24
Finished Apr 23 03:01:52 PM PDT 24
Peak memory 236544 kb
Host smart-a3505af2-294c-4e05-a4cb-fec8fd08fd55
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1572930602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.1572930602
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.2862855125
Short name T807
Test name
Test status
Simulation time 6486870 ps
CPU time 1.45 seconds
Started Apr 23 03:01:47 PM PDT 24
Finished Apr 23 03:01:49 PM PDT 24
Peak memory 236644 kb
Host smart-d74706ca-4aef-4b32-90ad-6bcc764cc89e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2862855125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.2862855125
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.1342844008
Short name T754
Test name
Test status
Simulation time 344370319 ps
CPU time 15.31 seconds
Started Apr 23 03:01:46 PM PDT 24
Finished Apr 23 03:02:02 PM PDT 24
Peak memory 240380 kb
Host smart-08a580e3-05e4-4c9d-bc18-9254b5ddac00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1342844008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.1342844008
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.1508131910
Short name T138
Test name
Test status
Simulation time 16714369451 ps
CPU time 1204.5 seconds
Started Apr 23 03:01:42 PM PDT 24
Finished Apr 23 03:21:47 PM PDT 24
Peak memory 265432 kb
Host smart-e056c666-5627-4889-89e2-975ef9e680c8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508131910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.1508131910
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.3991036816
Short name T703
Test name
Test status
Simulation time 108319813 ps
CPU time 10.14 seconds
Started Apr 23 03:01:42 PM PDT 24
Finished Apr 23 03:01:53 PM PDT 24
Peak memory 248636 kb
Host smart-64621220-52f7-427a-b3d2-1afbace30ad2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3991036816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.3991036816
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.2538374621
Short name T179
Test name
Test status
Simulation time 157379277 ps
CPU time 22.1 seconds
Started Apr 23 03:01:45 PM PDT 24
Finished Apr 23 03:02:08 PM PDT 24
Peak memory 239440 kb
Host smart-1009ce0f-267e-458c-a145-e99b629f1998
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2538374621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.2538374621
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.3304142528
Short name T798
Test name
Test status
Simulation time 84773012 ps
CPU time 7.28 seconds
Started Apr 23 03:01:52 PM PDT 24
Finished Apr 23 03:01:59 PM PDT 24
Peak memory 238192 kb
Host smart-9ef8a634-fceb-43a5-9df0-599b4c1aabc8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304142528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.3304142528
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.2709333756
Short name T708
Test name
Test status
Simulation time 107168695 ps
CPU time 8.17 seconds
Started Apr 23 03:01:50 PM PDT 24
Finished Apr 23 03:01:59 PM PDT 24
Peak memory 235736 kb
Host smart-0dafc8f5-6d0a-454a-b5e2-e107123d8e10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2709333756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.2709333756
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.4181643743
Short name T795
Test name
Test status
Simulation time 707869050 ps
CPU time 53.46 seconds
Started Apr 23 03:01:52 PM PDT 24
Finished Apr 23 03:02:46 PM PDT 24
Peak memory 248572 kb
Host smart-d3dd8f13-d45b-4d8b-8e32-cf8f03e0cb84
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4181643743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.4181643743
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.2548778399
Short name T697
Test name
Test status
Simulation time 279218723 ps
CPU time 10.15 seconds
Started Apr 23 03:01:49 PM PDT 24
Finished Apr 23 03:01:59 PM PDT 24
Peak memory 248212 kb
Host smart-cfc608c0-d6ca-4fe5-97f7-80d41b509968
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2548778399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.2548778399
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.3169788223
Short name T763
Test name
Test status
Simulation time 213771589 ps
CPU time 9 seconds
Started Apr 23 03:01:57 PM PDT 24
Finished Apr 23 03:02:06 PM PDT 24
Peak memory 255400 kb
Host smart-eaffe1f9-1e89-410f-b18f-80a7b56342ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169788223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.3169788223
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.1956368185
Short name T814
Test name
Test status
Simulation time 61689874 ps
CPU time 4.71 seconds
Started Apr 23 03:01:53 PM PDT 24
Finished Apr 23 03:01:59 PM PDT 24
Peak memory 235728 kb
Host smart-60f731f9-a31e-415b-a928-a712cbff0161
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1956368185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.1956368185
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.135712050
Short name T782
Test name
Test status
Simulation time 18453226 ps
CPU time 1.34 seconds
Started Apr 23 03:01:53 PM PDT 24
Finished Apr 23 03:01:55 PM PDT 24
Peak memory 236624 kb
Host smart-a345451d-ac6e-4399-8543-32830b7f5d95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=135712050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.135712050
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.219958853
Short name T753
Test name
Test status
Simulation time 685019068 ps
CPU time 50.66 seconds
Started Apr 23 03:01:54 PM PDT 24
Finished Apr 23 03:02:45 PM PDT 24
Peak memory 248572 kb
Host smart-6b8ea649-c6ec-4d91-8f7c-cb6376005c94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=219958853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_out
standing.219958853
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.1767761429
Short name T146
Test name
Test status
Simulation time 5566656072 ps
CPU time 97.29 seconds
Started Apr 23 03:01:53 PM PDT 24
Finished Apr 23 03:03:31 PM PDT 24
Peak memory 265212 kb
Host smart-e2ffe1c5-b7a5-4622-a42b-49c9c14368b0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1767761429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.1767761429
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.3202658574
Short name T767
Test name
Test status
Simulation time 82632181 ps
CPU time 10.76 seconds
Started Apr 23 03:01:53 PM PDT 24
Finished Apr 23 03:02:04 PM PDT 24
Peak memory 253516 kb
Host smart-3a55e1b9-39f9-45f7-a5c5-4b0b705d57b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3202658574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.3202658574
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.2291948288
Short name T813
Test name
Test status
Simulation time 870267280 ps
CPU time 10.25 seconds
Started Apr 23 03:02:01 PM PDT 24
Finished Apr 23 03:02:12 PM PDT 24
Peak memory 243588 kb
Host smart-2f90f4fc-0c92-4f95-b9cb-4e75de5ea7da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291948288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.2291948288
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.2101680058
Short name T808
Test name
Test status
Simulation time 457020889 ps
CPU time 6.02 seconds
Started Apr 23 03:01:59 PM PDT 24
Finished Apr 23 03:02:05 PM PDT 24
Peak memory 236612 kb
Host smart-6f09d479-ed2e-4ce1-8a3e-1b5ea750e979
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2101680058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.2101680058
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.1683955013
Short name T785
Test name
Test status
Simulation time 13523758 ps
CPU time 1.32 seconds
Started Apr 23 03:01:57 PM PDT 24
Finished Apr 23 03:01:59 PM PDT 24
Peak memory 236624 kb
Host smart-8d3677f9-4f61-4a27-9482-c45e8db257d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1683955013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.1683955013
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.3815227357
Short name T805
Test name
Test status
Simulation time 340978517 ps
CPU time 26.35 seconds
Started Apr 23 03:01:59 PM PDT 24
Finished Apr 23 03:02:26 PM PDT 24
Peak memory 240404 kb
Host smart-c4626a11-d698-4e8f-9676-7d953c70fe5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3815227357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.3815227357
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.3544067168
Short name T152
Test name
Test status
Simulation time 1025832484 ps
CPU time 124.91 seconds
Started Apr 23 03:01:58 PM PDT 24
Finished Apr 23 03:04:03 PM PDT 24
Peak memory 257060 kb
Host smart-c9bba651-837b-4492-b06c-2a93c1851881
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3544067168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.3544067168
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.1391853430
Short name T734
Test name
Test status
Simulation time 65079943 ps
CPU time 5.75 seconds
Started Apr 23 03:01:57 PM PDT 24
Finished Apr 23 03:02:03 PM PDT 24
Peak memory 248280 kb
Host smart-c57d9155-34ff-4d94-b192-35f46886bf9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1391853430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.1391853430
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.1161331874
Short name T720
Test name
Test status
Simulation time 415471927 ps
CPU time 9.28 seconds
Started Apr 23 03:02:07 PM PDT 24
Finished Apr 23 03:02:17 PM PDT 24
Peak memory 240456 kb
Host smart-32f41cd3-7929-465b-942f-9198eb69e6a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161331874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.1161331874
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.311527558
Short name T793
Test name
Test status
Simulation time 177245190 ps
CPU time 5.19 seconds
Started Apr 23 03:02:07 PM PDT 24
Finished Apr 23 03:02:13 PM PDT 24
Peak memory 239500 kb
Host smart-25c5cabd-94d4-41ee-bef9-719fd1baf36d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=311527558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.311527558
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.2567653566
Short name T167
Test name
Test status
Simulation time 31158839 ps
CPU time 1.32 seconds
Started Apr 23 03:02:04 PM PDT 24
Finished Apr 23 03:02:05 PM PDT 24
Peak memory 236536 kb
Host smart-19b90e63-f6e0-479c-9ac6-35693a10f4b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2567653566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.2567653566
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.1758272630
Short name T181
Test name
Test status
Simulation time 1440442035 ps
CPU time 47.32 seconds
Started Apr 23 03:02:06 PM PDT 24
Finished Apr 23 03:02:54 PM PDT 24
Peak memory 244800 kb
Host smart-8643c227-ffde-4111-9252-46078ed7f318
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1758272630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.1758272630
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3460881144
Short name T801
Test name
Test status
Simulation time 4567861178 ps
CPU time 369.72 seconds
Started Apr 23 03:02:01 PM PDT 24
Finished Apr 23 03:08:11 PM PDT 24
Peak memory 265568 kb
Host smart-d7016877-3254-4008-a113-c65093bb4c03
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460881144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.3460881144
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.1711096133
Short name T748
Test name
Test status
Simulation time 1473721529 ps
CPU time 20.61 seconds
Started Apr 23 03:02:03 PM PDT 24
Finished Apr 23 03:02:24 PM PDT 24
Peak memory 248128 kb
Host smart-e6b80a0f-5b79-4030-aa95-dbfbf9a5b4ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1711096133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.1711096133
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.1557641988
Short name T340
Test name
Test status
Simulation time 58241982 ps
CPU time 11.42 seconds
Started Apr 23 03:02:13 PM PDT 24
Finished Apr 23 03:02:25 PM PDT 24
Peak memory 256432 kb
Host smart-f4d29e23-ff2c-4154-b02e-de12635fed8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557641988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.1557641988
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.3562388903
Short name T781
Test name
Test status
Simulation time 120336742 ps
CPU time 6.9 seconds
Started Apr 23 03:02:11 PM PDT 24
Finished Apr 23 03:02:18 PM PDT 24
Peak memory 236644 kb
Host smart-a9a977c3-a74e-42ed-9818-72e43438165f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3562388903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.3562388903
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.2221475124
Short name T770
Test name
Test status
Simulation time 9737037 ps
CPU time 1.59 seconds
Started Apr 23 03:02:10 PM PDT 24
Finished Apr 23 03:02:12 PM PDT 24
Peak memory 235752 kb
Host smart-64af897d-01a8-4325-8b38-40fb208235a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2221475124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.2221475124
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.1785611191
Short name T707
Test name
Test status
Simulation time 1547447672 ps
CPU time 39.84 seconds
Started Apr 23 03:02:12 PM PDT 24
Finished Apr 23 03:02:52 PM PDT 24
Peak memory 244840 kb
Host smart-493da4ab-45ae-432f-a582-813893a91874
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1785611191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.1785611191
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.451225825
Short name T696
Test name
Test status
Simulation time 235668156 ps
CPU time 17.3 seconds
Started Apr 23 03:02:07 PM PDT 24
Finished Apr 23 03:02:25 PM PDT 24
Peak memory 254100 kb
Host smart-fe934361-4730-4a24-9b02-e0f78c21702e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=451225825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.451225825
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.2231766921
Short name T751
Test name
Test status
Simulation time 59724043 ps
CPU time 5.34 seconds
Started Apr 23 03:02:20 PM PDT 24
Finished Apr 23 03:02:26 PM PDT 24
Peak memory 240760 kb
Host smart-b514c2c3-0c68-437d-bc23-86ab11815a7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231766921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.2231766921
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.1626795142
Short name T761
Test name
Test status
Simulation time 321635634 ps
CPU time 7.74 seconds
Started Apr 23 03:02:16 PM PDT 24
Finished Apr 23 03:02:24 PM PDT 24
Peak memory 236604 kb
Host smart-ff3f003e-3f97-4475-8fef-6130ac648e6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1626795142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.1626795142
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.551232587
Short name T335
Test name
Test status
Simulation time 22040617 ps
CPU time 1.95 seconds
Started Apr 23 03:02:21 PM PDT 24
Finished Apr 23 03:02:23 PM PDT 24
Peak memory 236640 kb
Host smart-d50918f0-7af2-4fcc-989b-27ec14154e93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=551232587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.551232587
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.3918461181
Short name T711
Test name
Test status
Simulation time 493256046 ps
CPU time 35.69 seconds
Started Apr 23 03:02:20 PM PDT 24
Finished Apr 23 03:02:57 PM PDT 24
Peak memory 243968 kb
Host smart-977385d8-ec6c-4095-bde9-982c5b28ef25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3918461181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.3918461181
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.64493468
Short name T159
Test name
Test status
Simulation time 35142094067 ps
CPU time 324.64 seconds
Started Apr 23 03:02:14 PM PDT 24
Finished Apr 23 03:07:39 PM PDT 24
Peak memory 265396 kb
Host smart-ddb51612-5a30-4442-86e5-81e11e789c27
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64493468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.64493468
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.1764173172
Short name T742
Test name
Test status
Simulation time 1358917292 ps
CPU time 24.6 seconds
Started Apr 23 03:02:13 PM PDT 24
Finished Apr 23 03:02:38 PM PDT 24
Peak memory 254184 kb
Host smart-2b4f8d2a-a8ae-49d4-86c2-cc81379634c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1764173172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.1764173172
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.2990302805
Short name T700
Test name
Test status
Simulation time 1102373634 ps
CPU time 138.55 seconds
Started Apr 23 03:00:29 PM PDT 24
Finished Apr 23 03:02:48 PM PDT 24
Peak memory 239004 kb
Host smart-8dd35def-2fb5-4c93-aec5-a728723e11df
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2990302805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.2990302805
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.602583188
Short name T765
Test name
Test status
Simulation time 8563051924 ps
CPU time 284.47 seconds
Started Apr 23 03:00:31 PM PDT 24
Finished Apr 23 03:05:16 PM PDT 24
Peak memory 240516 kb
Host smart-b8cbda8d-bd9d-4604-b9ae-fce731846064
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=602583188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.602583188
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.4064371896
Short name T698
Test name
Test status
Simulation time 73566453 ps
CPU time 6.69 seconds
Started Apr 23 03:00:30 PM PDT 24
Finished Apr 23 03:00:37 PM PDT 24
Peak memory 240332 kb
Host smart-b6a04a1b-a2c6-4f40-a406-aa6858d3855b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4064371896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.4064371896
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.1551493966
Short name T718
Test name
Test status
Simulation time 73139516 ps
CPU time 5.79 seconds
Started Apr 23 03:00:32 PM PDT 24
Finished Apr 23 03:00:38 PM PDT 24
Peak memory 238560 kb
Host smart-6e51e409-cf91-4a33-a4e0-2e43e1c21570
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551493966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.1551493966
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.3908563767
Short name T789
Test name
Test status
Simulation time 190291236 ps
CPU time 4.56 seconds
Started Apr 23 03:00:32 PM PDT 24
Finished Apr 23 03:00:37 PM PDT 24
Peak memory 236544 kb
Host smart-d1e84ad5-16ab-4a08-8613-b23aab954793
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3908563767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.3908563767
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.2245158025
Short name T758
Test name
Test status
Simulation time 7842104 ps
CPU time 1.51 seconds
Started Apr 23 03:00:27 PM PDT 24
Finished Apr 23 03:00:29 PM PDT 24
Peak memory 236672 kb
Host smart-d9e823ba-62c1-4cdc-8346-7252458fedec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2245158025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.2245158025
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.1991074770
Short name T739
Test name
Test status
Simulation time 394791912 ps
CPU time 16.17 seconds
Started Apr 23 03:00:29 PM PDT 24
Finished Apr 23 03:00:45 PM PDT 24
Peak memory 244816 kb
Host smart-1466434c-55ab-48d3-84f3-7ef1b18e4cf0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1991074770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.1991074770
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.3114675892
Short name T343
Test name
Test status
Simulation time 6597088216 ps
CPU time 563.65 seconds
Started Apr 23 03:00:20 PM PDT 24
Finished Apr 23 03:09:44 PM PDT 24
Peak memory 268152 kb
Host smart-92eb6c21-2c0e-4223-84b9-074a002b4fb5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114675892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.3114675892
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.4096925977
Short name T815
Test name
Test status
Simulation time 335515715 ps
CPU time 13.68 seconds
Started Apr 23 03:00:23 PM PDT 24
Finished Apr 23 03:00:37 PM PDT 24
Peak memory 255112 kb
Host smart-1ca17624-a228-4354-bd2b-7f7911ba7bd5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4096925977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.4096925977
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.2662522817
Short name T759
Test name
Test status
Simulation time 14629372 ps
CPU time 1.56 seconds
Started Apr 23 03:02:17 PM PDT 24
Finished Apr 23 03:02:19 PM PDT 24
Peak memory 236604 kb
Host smart-860e3007-24c1-4956-a9a0-4c9aa24d9073
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2662522817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.2662522817
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.4259584613
Short name T768
Test name
Test status
Simulation time 10089216 ps
CPU time 1.54 seconds
Started Apr 23 03:02:20 PM PDT 24
Finished Apr 23 03:02:22 PM PDT 24
Peak memory 235680 kb
Host smart-e0ecd8f3-ad8e-4022-893c-e6b0c6986f78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4259584613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.4259584613
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.386074385
Short name T811
Test name
Test status
Simulation time 11717506 ps
CPU time 1.3 seconds
Started Apr 23 03:02:18 PM PDT 24
Finished Apr 23 03:02:20 PM PDT 24
Peak memory 235776 kb
Host smart-69b23f77-b3db-4249-bc6e-7c64b218403d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=386074385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.386074385
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.237041482
Short name T784
Test name
Test status
Simulation time 8197506 ps
CPU time 1.51 seconds
Started Apr 23 03:02:18 PM PDT 24
Finished Apr 23 03:02:20 PM PDT 24
Peak memory 234684 kb
Host smart-f26d4edf-4073-438c-b76a-801496b04fd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=237041482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.237041482
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.1843911686
Short name T732
Test name
Test status
Simulation time 10955954 ps
CPU time 1.65 seconds
Started Apr 23 03:02:22 PM PDT 24
Finished Apr 23 03:02:24 PM PDT 24
Peak memory 235768 kb
Host smart-08475d0e-3f5e-45b0-b6d6-e0ba679278ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1843911686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.1843911686
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.1100220107
Short name T775
Test name
Test status
Simulation time 9806897 ps
CPU time 1.57 seconds
Started Apr 23 03:02:22 PM PDT 24
Finished Apr 23 03:02:24 PM PDT 24
Peak memory 235668 kb
Host smart-bc64fc4b-f470-4755-9fd2-b5844fc01a98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1100220107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.1100220107
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.1787750601
Short name T332
Test name
Test status
Simulation time 28900795 ps
CPU time 1.29 seconds
Started Apr 23 03:02:22 PM PDT 24
Finished Apr 23 03:02:23 PM PDT 24
Peak memory 234604 kb
Host smart-0dab22a6-65b2-4a51-bcf6-74bf66e7c52b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1787750601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.1787750601
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.181971963
Short name T236
Test name
Test status
Simulation time 15799727 ps
CPU time 1.41 seconds
Started Apr 23 03:02:21 PM PDT 24
Finished Apr 23 03:02:23 PM PDT 24
Peak memory 236608 kb
Host smart-10609f6e-74af-4080-a408-11077afc45b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=181971963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.181971963
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.733429335
Short name T735
Test name
Test status
Simulation time 10192124 ps
CPU time 1.26 seconds
Started Apr 23 03:02:21 PM PDT 24
Finished Apr 23 03:02:22 PM PDT 24
Peak memory 236624 kb
Host smart-0b0c6da8-e9fb-4aca-9374-e6a21e9f3496
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=733429335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.733429335
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.1330772344
Short name T198
Test name
Test status
Simulation time 2772775467 ps
CPU time 166.29 seconds
Started Apr 23 03:00:36 PM PDT 24
Finished Apr 23 03:03:23 PM PDT 24
Peak memory 236652 kb
Host smart-125f4cec-45f5-4041-b9b5-db8c67c7263a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1330772344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.1330772344
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.3812063963
Short name T716
Test name
Test status
Simulation time 7821511864 ps
CPU time 402.63 seconds
Started Apr 23 03:00:31 PM PDT 24
Finished Apr 23 03:07:14 PM PDT 24
Peak memory 235836 kb
Host smart-8314aee2-5047-41e1-8183-aa7219f16279
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3812063963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.3812063963
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.691360808
Short name T702
Test name
Test status
Simulation time 31735316 ps
CPU time 4.61 seconds
Started Apr 23 03:00:32 PM PDT 24
Finished Apr 23 03:00:37 PM PDT 24
Peak memory 240368 kb
Host smart-6b652737-23b9-4ee3-9021-83b0bc8221f3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=691360808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.691360808
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.3251335011
Short name T180
Test name
Test status
Simulation time 1231474930 ps
CPU time 9.85 seconds
Started Apr 23 03:00:39 PM PDT 24
Finished Apr 23 03:00:49 PM PDT 24
Peak memory 240440 kb
Host smart-6a0f70d6-bc49-430c-8ebc-dbdf9c1780b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251335011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.3251335011
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.1256748975
Short name T704
Test name
Test status
Simulation time 52242443 ps
CPU time 4.71 seconds
Started Apr 23 03:00:33 PM PDT 24
Finished Apr 23 03:00:39 PM PDT 24
Peak memory 236652 kb
Host smart-49b90980-6a82-4f22-ab4b-c4078d744158
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1256748975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.1256748975
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.2562274207
Short name T715
Test name
Test status
Simulation time 20201429 ps
CPU time 1.21 seconds
Started Apr 23 03:00:35 PM PDT 24
Finished Apr 23 03:00:36 PM PDT 24
Peak memory 236412 kb
Host smart-d16eb661-0f5e-4154-97ef-ddab248c445c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2562274207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.2562274207
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.2439215961
Short name T240
Test name
Test status
Simulation time 333606942 ps
CPU time 21.8 seconds
Started Apr 23 03:00:39 PM PDT 24
Finished Apr 23 03:01:02 PM PDT 24
Peak memory 248584 kb
Host smart-826dd62a-6e5e-431f-91b6-37da73375b06
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2439215961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.2439215961
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.2091353720
Short name T154
Test name
Test status
Simulation time 1715525138 ps
CPU time 117.15 seconds
Started Apr 23 03:00:31 PM PDT 24
Finished Apr 23 03:02:29 PM PDT 24
Peak memory 265732 kb
Host smart-810e78bc-31ea-4706-aeb1-d6501dedb988
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2091353720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.2091353720
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.525659381
Short name T139
Test name
Test status
Simulation time 12748746557 ps
CPU time 590.03 seconds
Started Apr 23 03:00:30 PM PDT 24
Finished Apr 23 03:10:20 PM PDT 24
Peak memory 265352 kb
Host smart-8519222a-cbad-42cb-b287-7cecd8ee5acd
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525659381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.525659381
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.1522245128
Short name T695
Test name
Test status
Simulation time 146095393 ps
CPU time 9.27 seconds
Started Apr 23 03:00:35 PM PDT 24
Finished Apr 23 03:00:45 PM PDT 24
Peak memory 253644 kb
Host smart-4836e89d-3e40-4b0c-bff8-19c91a53766a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1522245128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.1522245128
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.2871405430
Short name T773
Test name
Test status
Simulation time 9530742 ps
CPU time 1.6 seconds
Started Apr 23 03:02:25 PM PDT 24
Finished Apr 23 03:02:27 PM PDT 24
Peak memory 235780 kb
Host smart-e3f7ea16-c378-4c90-b813-59cbe9c6b2c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2871405430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.2871405430
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.37444556
Short name T762
Test name
Test status
Simulation time 9671000 ps
CPU time 1.53 seconds
Started Apr 23 03:02:23 PM PDT 24
Finished Apr 23 03:02:25 PM PDT 24
Peak memory 234772 kb
Host smart-5207d974-22c3-4b85-a556-92b3e4b0e1c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=37444556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.37444556
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.364347888
Short name T328
Test name
Test status
Simulation time 10499440 ps
CPU time 1.22 seconds
Started Apr 23 03:02:27 PM PDT 24
Finished Apr 23 03:02:29 PM PDT 24
Peak memory 236624 kb
Host smart-93c3dc2f-49dd-4cd1-96a6-da1e574df7fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=364347888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.364347888
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.2634173673
Short name T731
Test name
Test status
Simulation time 43207063 ps
CPU time 1.27 seconds
Started Apr 23 03:02:27 PM PDT 24
Finished Apr 23 03:02:28 PM PDT 24
Peak memory 236500 kb
Host smart-1af00176-b9c2-4ac9-958f-e7e41b49efe5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2634173673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.2634173673
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.2681787344
Short name T330
Test name
Test status
Simulation time 9800041 ps
CPU time 1.33 seconds
Started Apr 23 03:02:28 PM PDT 24
Finished Apr 23 03:02:30 PM PDT 24
Peak memory 234692 kb
Host smart-f49633a8-d4a5-4e40-915c-4563e50c436f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2681787344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.2681787344
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.2963229625
Short name T800
Test name
Test status
Simulation time 11206742 ps
CPU time 1.66 seconds
Started Apr 23 03:02:28 PM PDT 24
Finished Apr 23 03:02:30 PM PDT 24
Peak memory 234760 kb
Host smart-b0493676-784e-4a38-9c6b-0aceb2c679d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2963229625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.2963229625
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.1803708415
Short name T766
Test name
Test status
Simulation time 11065700 ps
CPU time 1.27 seconds
Started Apr 23 03:02:28 PM PDT 24
Finished Apr 23 03:02:30 PM PDT 24
Peak memory 236592 kb
Host smart-a143a095-9758-42b2-972d-4383bc5ce319
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1803708415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.1803708415
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.3162622826
Short name T810
Test name
Test status
Simulation time 7378724 ps
CPU time 1.46 seconds
Started Apr 23 03:02:28 PM PDT 24
Finished Apr 23 03:02:30 PM PDT 24
Peak memory 234648 kb
Host smart-c2d754dd-2cb5-45d9-b700-8fbbacf6bfae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3162622826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.3162622826
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.516360709
Short name T747
Test name
Test status
Simulation time 14128019 ps
CPU time 1.45 seconds
Started Apr 23 03:02:33 PM PDT 24
Finished Apr 23 03:02:35 PM PDT 24
Peak memory 235780 kb
Host smart-e99c5cbd-9924-4500-b8f2-5f12322c9b18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=516360709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.516360709
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.432362657
Short name T806
Test name
Test status
Simulation time 8364490360 ps
CPU time 155.48 seconds
Started Apr 23 03:00:49 PM PDT 24
Finished Apr 23 03:03:24 PM PDT 24
Peak memory 240504 kb
Host smart-fac05d0a-4fed-4592-b83a-c743a3b63b77
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=432362657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.432362657
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.2138541169
Short name T726
Test name
Test status
Simulation time 34288722341 ps
CPU time 563.66 seconds
Started Apr 23 03:00:46 PM PDT 24
Finished Apr 23 03:10:10 PM PDT 24
Peak memory 236672 kb
Host smart-b54e5a16-1b7c-4ce4-afff-f280ddb507c2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2138541169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.2138541169
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.1900723477
Short name T166
Test name
Test status
Simulation time 32264260 ps
CPU time 5.12 seconds
Started Apr 23 03:00:44 PM PDT 24
Finished Apr 23 03:00:49 PM PDT 24
Peak memory 240364 kb
Host smart-23cb3de7-99e9-4065-ba44-c24d6ee2b621
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1900723477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.1900723477
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.2373100714
Short name T203
Test name
Test status
Simulation time 111999136 ps
CPU time 9.05 seconds
Started Apr 23 03:00:48 PM PDT 24
Finished Apr 23 03:00:58 PM PDT 24
Peak memory 243876 kb
Host smart-23ed54b1-145c-4f7e-9c4a-7940c98f0079
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373100714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.2373100714
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.1144303423
Short name T714
Test name
Test status
Simulation time 162994477 ps
CPU time 5.35 seconds
Started Apr 23 03:00:47 PM PDT 24
Finished Apr 23 03:00:52 PM PDT 24
Peak memory 239484 kb
Host smart-4ee4a759-cd1b-4639-bd19-36eba1df7860
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1144303423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.1144303423
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.2726802212
Short name T746
Test name
Test status
Simulation time 7595796 ps
CPU time 1.49 seconds
Started Apr 23 03:00:43 PM PDT 24
Finished Apr 23 03:00:45 PM PDT 24
Peak memory 236592 kb
Host smart-32ed5248-723d-4c02-b238-78008b88de84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2726802212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.2726802212
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.2595034072
Short name T743
Test name
Test status
Simulation time 98629117 ps
CPU time 11.39 seconds
Started Apr 23 03:00:49 PM PDT 24
Finished Apr 23 03:01:01 PM PDT 24
Peak memory 240368 kb
Host smart-53b3cb5f-8606-49af-ae08-cf9f18b2fac0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2595034072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.2595034072
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.3034740067
Short name T131
Test name
Test status
Simulation time 2190147098 ps
CPU time 386.04 seconds
Started Apr 23 03:00:44 PM PDT 24
Finished Apr 23 03:07:11 PM PDT 24
Peak memory 270772 kb
Host smart-65c4bb03-8765-443b-a873-99bd8d6cb7a8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034740067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.3034740067
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.1731130536
Short name T749
Test name
Test status
Simulation time 396138865 ps
CPU time 24.66 seconds
Started Apr 23 03:00:44 PM PDT 24
Finished Apr 23 03:01:09 PM PDT 24
Peak memory 248380 kb
Host smart-3a376a4a-8be7-4c41-b159-b9f430acb255
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1731130536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.1731130536
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.1626330863
Short name T745
Test name
Test status
Simulation time 8759547 ps
CPU time 1.49 seconds
Started Apr 23 03:02:29 PM PDT 24
Finished Apr 23 03:02:31 PM PDT 24
Peak memory 235756 kb
Host smart-7c36b670-d2a2-43cd-a004-291173400e84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1626330863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.1626330863
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.4242109134
Short name T336
Test name
Test status
Simulation time 8476304 ps
CPU time 1.53 seconds
Started Apr 23 03:02:31 PM PDT 24
Finished Apr 23 03:02:33 PM PDT 24
Peak memory 235736 kb
Host smart-36d7cdd9-253e-429b-ac24-174dbd5c7b9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4242109134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.4242109134
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.6383420
Short name T334
Test name
Test status
Simulation time 11964369 ps
CPU time 1.37 seconds
Started Apr 23 03:02:29 PM PDT 24
Finished Apr 23 03:02:30 PM PDT 24
Peak memory 236616 kb
Host smart-18cf9cb2-bf72-4f32-9a50-70679b323fd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=6383420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.6383420
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.3105304763
Short name T788
Test name
Test status
Simulation time 7691890 ps
CPU time 1.45 seconds
Started Apr 23 03:02:30 PM PDT 24
Finished Apr 23 03:02:32 PM PDT 24
Peak memory 234676 kb
Host smart-6584176e-94f2-40fd-b8b7-565742144a8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3105304763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.3105304763
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.1226517364
Short name T752
Test name
Test status
Simulation time 28092255 ps
CPU time 1.46 seconds
Started Apr 23 03:02:31 PM PDT 24
Finished Apr 23 03:02:33 PM PDT 24
Peak memory 235716 kb
Host smart-96fd1118-9f41-4be8-aead-c2d079613a92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1226517364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.1226517364
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.644334832
Short name T329
Test name
Test status
Simulation time 8251047 ps
CPU time 1.48 seconds
Started Apr 23 03:02:30 PM PDT 24
Finished Apr 23 03:02:32 PM PDT 24
Peak memory 236624 kb
Host smart-7dfbbe3e-f572-4665-bac6-64022e08a97b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=644334832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.644334832
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.3165391707
Short name T736
Test name
Test status
Simulation time 11449083 ps
CPU time 1.73 seconds
Started Apr 23 03:02:31 PM PDT 24
Finished Apr 23 03:02:34 PM PDT 24
Peak memory 235720 kb
Host smart-832afa11-64ab-461f-b6c6-4d91b34ba8d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3165391707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.3165391707
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.2339425349
Short name T729
Test name
Test status
Simulation time 14608685 ps
CPU time 1.26 seconds
Started Apr 23 03:02:33 PM PDT 24
Finished Apr 23 03:02:34 PM PDT 24
Peak memory 234664 kb
Host smart-ce4d2d9e-6a83-4635-8fe7-560dbc602618
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2339425349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.2339425349
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.3290210226
Short name T757
Test name
Test status
Simulation time 6735603 ps
CPU time 1.56 seconds
Started Apr 23 03:02:34 PM PDT 24
Finished Apr 23 03:02:36 PM PDT 24
Peak memory 236564 kb
Host smart-c3495003-4624-44a5-98e2-47fc334934ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3290210226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.3290210226
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.445170828
Short name T802
Test name
Test status
Simulation time 13856109 ps
CPU time 1.53 seconds
Started Apr 23 03:02:34 PM PDT 24
Finished Apr 23 03:02:36 PM PDT 24
Peak memory 236648 kb
Host smart-ec3be775-2266-41a3-8b12-dc8e6486154f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=445170828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.445170828
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.3535033842
Short name T733
Test name
Test status
Simulation time 146388517 ps
CPU time 7.19 seconds
Started Apr 23 03:01:03 PM PDT 24
Finished Apr 23 03:01:11 PM PDT 24
Peak memory 240424 kb
Host smart-f80afbaf-4eb7-45b3-bcc0-322c08d4774e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535033842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.3535033842
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.4165347887
Short name T337
Test name
Test status
Simulation time 56044883 ps
CPU time 4.28 seconds
Started Apr 23 03:00:58 PM PDT 24
Finished Apr 23 03:01:02 PM PDT 24
Peak memory 235676 kb
Host smart-101a9c49-1901-43f6-a3a1-ccb7f9d0a562
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4165347887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.4165347887
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.3661636829
Short name T792
Test name
Test status
Simulation time 8535858 ps
CPU time 1.39 seconds
Started Apr 23 03:00:59 PM PDT 24
Finished Apr 23 03:01:01 PM PDT 24
Peak memory 236592 kb
Host smart-9785db05-69ee-4083-bda2-37e6599de173
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3661636829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.3661636829
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.594316721
Short name T699
Test name
Test status
Simulation time 1877829482 ps
CPU time 37.12 seconds
Started Apr 23 03:01:04 PM PDT 24
Finished Apr 23 03:01:42 PM PDT 24
Peak memory 243924 kb
Host smart-4329a0d2-8746-4c00-89b7-cf781c892de3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=594316721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_outs
tanding.594316721
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.1171581937
Short name T796
Test name
Test status
Simulation time 5495433616 ps
CPU time 380.6 seconds
Started Apr 23 03:00:52 PM PDT 24
Finished Apr 23 03:07:13 PM PDT 24
Peak memory 265408 kb
Host smart-cd30c98d-9bdc-41e2-b94f-5e2ccd76b671
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1171581937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.1171581937
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3565356076
Short name T129
Test name
Test status
Simulation time 2344765751 ps
CPU time 351.04 seconds
Started Apr 23 03:00:53 PM PDT 24
Finished Apr 23 03:06:44 PM PDT 24
Peak memory 265324 kb
Host smart-5dc49d41-2297-4449-bdea-5a84e152daa7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565356076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.3565356076
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.4245890156
Short name T783
Test name
Test status
Simulation time 71812357 ps
CPU time 3.72 seconds
Started Apr 23 03:00:52 PM PDT 24
Finished Apr 23 03:00:56 PM PDT 24
Peak memory 248396 kb
Host smart-6c6c169d-6a5e-4d6d-bd2e-e01a2ec5a44d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4245890156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.4245890156
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.1237543112
Short name T339
Test name
Test status
Simulation time 154331250 ps
CPU time 12.33 seconds
Started Apr 23 03:01:09 PM PDT 24
Finished Apr 23 03:01:21 PM PDT 24
Peak memory 250964 kb
Host smart-f15c96eb-3c3a-494b-90d6-30b7b692cb64
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237543112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.1237543112
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.3972544298
Short name T760
Test name
Test status
Simulation time 37527724 ps
CPU time 6.71 seconds
Started Apr 23 03:01:05 PM PDT 24
Finished Apr 23 03:01:12 PM PDT 24
Peak memory 236628 kb
Host smart-751dbcc7-8f9f-4624-9c9d-4deed04237a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3972544298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.3972544298
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.195214162
Short name T730
Test name
Test status
Simulation time 25341141 ps
CPU time 2.05 seconds
Started Apr 23 03:01:06 PM PDT 24
Finished Apr 23 03:01:08 PM PDT 24
Peak memory 235740 kb
Host smart-4c9693c6-25b7-46f8-88da-44f8689ddc61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=195214162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.195214162
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.122661727
Short name T794
Test name
Test status
Simulation time 2633546696 ps
CPU time 53.57 seconds
Started Apr 23 03:01:06 PM PDT 24
Finished Apr 23 03:02:00 PM PDT 24
Peak memory 248648 kb
Host smart-89fd404a-0236-4c0f-b44e-813497515121
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=122661727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_outs
tanding.122661727
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.1815610831
Short name T812
Test name
Test status
Simulation time 264461184 ps
CPU time 11.95 seconds
Started Apr 23 03:01:03 PM PDT 24
Finished Apr 23 03:01:15 PM PDT 24
Peak memory 248332 kb
Host smart-81710d70-6d30-4a79-b541-06a3c97fb81a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1815610831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.1815610831
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.3601359832
Short name T338
Test name
Test status
Simulation time 128174239 ps
CPU time 5.97 seconds
Started Apr 23 03:01:16 PM PDT 24
Finished Apr 23 03:01:23 PM PDT 24
Peak memory 256452 kb
Host smart-54622f24-053f-4237-925b-2feb6ace1033
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601359832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.3601359832
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.2012885913
Short name T772
Test name
Test status
Simulation time 132064557 ps
CPU time 3.14 seconds
Started Apr 23 03:01:08 PM PDT 24
Finished Apr 23 03:01:11 PM PDT 24
Peak memory 239392 kb
Host smart-7515c073-7e03-4208-b042-0007e8d99e18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2012885913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.2012885913
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.2626333926
Short name T750
Test name
Test status
Simulation time 6209268 ps
CPU time 1.34 seconds
Started Apr 23 03:01:09 PM PDT 24
Finished Apr 23 03:01:10 PM PDT 24
Peak memory 236564 kb
Host smart-ebe8a207-324c-4eae-b2f1-4c741029e8b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2626333926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.2626333926
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.928616810
Short name T780
Test name
Test status
Simulation time 100796555 ps
CPU time 13.88 seconds
Started Apr 23 03:01:12 PM PDT 24
Finished Apr 23 03:01:26 PM PDT 24
Peak memory 244784 kb
Host smart-75d95e09-4fa6-47cb-991e-bb88189bcc85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=928616810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_outs
tanding.928616810
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.1404817412
Short name T142
Test name
Test status
Simulation time 5609773028 ps
CPU time 193.85 seconds
Started Apr 23 03:01:15 PM PDT 24
Finished Apr 23 03:04:29 PM PDT 24
Peak memory 265272 kb
Host smart-cd3c613f-2378-46f3-80d7-6345bf46dbf1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1404817412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.1404817412
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.1664671689
Short name T143
Test name
Test status
Simulation time 7967763410 ps
CPU time 679.23 seconds
Started Apr 23 03:01:10 PM PDT 24
Finished Apr 23 03:12:29 PM PDT 24
Peak memory 269188 kb
Host smart-f6641e79-7621-480f-af6f-e2b0764ff59d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664671689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.1664671689
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.136405038
Short name T741
Test name
Test status
Simulation time 331686181 ps
CPU time 10.4 seconds
Started Apr 23 03:01:09 PM PDT 24
Finished Apr 23 03:01:20 PM PDT 24
Peak memory 249960 kb
Host smart-e63b03e6-4cec-4b38-abc4-83ce9916f39e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=136405038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.136405038
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.998072073
Short name T202
Test name
Test status
Simulation time 34565313 ps
CPU time 5.56 seconds
Started Apr 23 03:01:18 PM PDT 24
Finished Apr 23 03:01:24 PM PDT 24
Peak memory 241816 kb
Host smart-a207178f-e43f-4c86-beb4-14492f47aa1f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998072073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.alert_handler_csr_mem_rw_with_rand_reset.998072073
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.1966550505
Short name T769
Test name
Test status
Simulation time 417894037 ps
CPU time 5.57 seconds
Started Apr 23 03:01:23 PM PDT 24
Finished Apr 23 03:01:29 PM PDT 24
Peak memory 236436 kb
Host smart-e134ab3b-33f0-40bf-afb7-73a3e049fd9a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1966550505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.1966550505
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.672338936
Short name T235
Test name
Test status
Simulation time 14993791 ps
CPU time 1.41 seconds
Started Apr 23 03:01:14 PM PDT 24
Finished Apr 23 03:01:16 PM PDT 24
Peak memory 236472 kb
Host smart-6aa7e84c-3777-40d4-93ce-7bab62046d32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=672338936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.672338936
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.1865752282
Short name T776
Test name
Test status
Simulation time 500912220 ps
CPU time 27.18 seconds
Started Apr 23 03:01:19 PM PDT 24
Finished Apr 23 03:01:46 PM PDT 24
Peak memory 244820 kb
Host smart-86642d89-eb64-497e-8fb7-1b3482456e8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1865752282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.1865752282
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.651513408
Short name T151
Test name
Test status
Simulation time 5922352106 ps
CPU time 376.89 seconds
Started Apr 23 03:01:16 PM PDT 24
Finished Apr 23 03:07:34 PM PDT 24
Peak memory 265364 kb
Host smart-3b1f1235-15ca-4a33-8ab7-f67632cd9dd1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=651513408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_error
s.651513408
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.4118654665
Short name T155
Test name
Test status
Simulation time 12709563417 ps
CPU time 518.28 seconds
Started Apr 23 03:01:17 PM PDT 24
Finished Apr 23 03:09:55 PM PDT 24
Peak memory 265268 kb
Host smart-c600abf4-1ed8-481e-b00b-450b4c84b68d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118654665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.4118654665
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.2469399536
Short name T725
Test name
Test status
Simulation time 229028628 ps
CPU time 7.63 seconds
Started Apr 23 03:01:16 PM PDT 24
Finished Apr 23 03:01:24 PM PDT 24
Peak memory 252876 kb
Host smart-b77b5ece-0956-4431-83f1-046fbb200fa2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2469399536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.2469399536
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.3767316058
Short name T779
Test name
Test status
Simulation time 379957565 ps
CPU time 8.78 seconds
Started Apr 23 03:01:24 PM PDT 24
Finished Apr 23 03:01:33 PM PDT 24
Peak memory 240408 kb
Host smart-a3fe4fb7-8d16-49a5-b6c6-3347062894f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767316058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.3767316058
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.3055768515
Short name T713
Test name
Test status
Simulation time 95496160 ps
CPU time 7.89 seconds
Started Apr 23 03:01:22 PM PDT 24
Finished Apr 23 03:01:30 PM PDT 24
Peak memory 236580 kb
Host smart-0662d8d5-bcf6-4db1-9ae3-3caae1423473
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3055768515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.3055768515
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.2430115349
Short name T764
Test name
Test status
Simulation time 9409484 ps
CPU time 1.57 seconds
Started Apr 23 03:01:24 PM PDT 24
Finished Apr 23 03:01:26 PM PDT 24
Peak memory 235724 kb
Host smart-4ba9d9f8-c7d9-4b87-accd-73b7be92565a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2430115349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.2430115349
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.2900990988
Short name T786
Test name
Test status
Simulation time 13474075852 ps
CPU time 42.21 seconds
Started Apr 23 03:01:22 PM PDT 24
Finished Apr 23 03:02:05 PM PDT 24
Peak memory 244852 kb
Host smart-2396077c-70c6-4245-ada5-05c30df8ac25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2900990988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.2900990988
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.2767780279
Short name T133
Test name
Test status
Simulation time 12391813398 ps
CPU time 554.51 seconds
Started Apr 23 03:01:25 PM PDT 24
Finished Apr 23 03:10:40 PM PDT 24
Peak memory 268600 kb
Host smart-58424422-1605-4124-a7a8-c2a0e01772c2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767780279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.2767780279
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.1303051827
Short name T797
Test name
Test status
Simulation time 51806159 ps
CPU time 7.67 seconds
Started Apr 23 03:01:24 PM PDT 24
Finished Apr 23 03:01:32 PM PDT 24
Peak memory 251752 kb
Host smart-a502c9f2-f667-44a6-8d76-3485ba94c5d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1303051827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.1303051827
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.804818518
Short name T128
Test name
Test status
Simulation time 35806650165 ps
CPU time 2039.36 seconds
Started Apr 23 03:02:38 PM PDT 24
Finished Apr 23 03:36:38 PM PDT 24
Peak memory 273268 kb
Host smart-3b19d942-2e45-4870-bd14-104152dd6001
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804818518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.804818518
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.409271271
Short name T554
Test name
Test status
Simulation time 173242441 ps
CPU time 9 seconds
Started Apr 23 03:02:40 PM PDT 24
Finished Apr 23 03:02:50 PM PDT 24
Peak memory 240452 kb
Host smart-7961ec95-69be-4625-b836-95fe522b5b9d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=409271271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.409271271
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.2088072599
Short name T222
Test name
Test status
Simulation time 4680877066 ps
CPU time 154.62 seconds
Started Apr 23 03:02:40 PM PDT 24
Finished Apr 23 03:05:15 PM PDT 24
Peak memory 256492 kb
Host smart-91eaa554-d7bc-4b1b-a6ba-11ba82ea22f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20880
72599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.2088072599
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.2982743303
Short name T596
Test name
Test status
Simulation time 406207079 ps
CPU time 43.81 seconds
Started Apr 23 03:02:37 PM PDT 24
Finished Apr 23 03:03:21 PM PDT 24
Peak memory 254568 kb
Host smart-3f461c20-ab16-4b62-a43e-fb2a2ba72ab9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29827
43303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.2982743303
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.1732354445
Short name T320
Test name
Test status
Simulation time 139188313127 ps
CPU time 2066.61 seconds
Started Apr 23 03:02:38 PM PDT 24
Finished Apr 23 03:37:05 PM PDT 24
Peak memory 289312 kb
Host smart-f2ed70c6-1bdc-4b72-b237-3b3ea05a7019
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732354445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.1732354445
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.2427597263
Short name T111
Test name
Test status
Simulation time 30016516901 ps
CPU time 1619.45 seconds
Started Apr 23 03:02:38 PM PDT 24
Finished Apr 23 03:29:38 PM PDT 24
Peak memory 288820 kb
Host smart-8e72f832-52cf-47c5-8f82-27f679da4f51
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427597263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.2427597263
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.1940009613
Short name T655
Test name
Test status
Simulation time 5311548169 ps
CPU time 119.64 seconds
Started Apr 23 03:02:36 PM PDT 24
Finished Apr 23 03:04:36 PM PDT 24
Peak memory 247604 kb
Host smart-f30f0844-6f46-41e0-a29a-f571bdbda3da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940009613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.1940009613
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.3652548546
Short name T477
Test name
Test status
Simulation time 558712064 ps
CPU time 21.74 seconds
Started Apr 23 03:02:34 PM PDT 24
Finished Apr 23 03:02:57 PM PDT 24
Peak memory 248740 kb
Host smart-f8cabc18-c87b-4186-8770-d7675289d2f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36525
48546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.3652548546
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.3719930559
Short name T574
Test name
Test status
Simulation time 3394316251 ps
CPU time 18.73 seconds
Started Apr 23 03:02:38 PM PDT 24
Finished Apr 23 03:02:57 PM PDT 24
Peak memory 254984 kb
Host smart-18a58d3a-e47d-4be3-89d7-5a3f6a63d1da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37199
30559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.3719930559
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.128052954
Short name T243
Test name
Test status
Simulation time 791832495 ps
CPU time 24.61 seconds
Started Apr 23 03:02:38 PM PDT 24
Finished Apr 23 03:03:03 PM PDT 24
Peak memory 254504 kb
Host smart-fdf9f650-0593-4c2c-a62f-efb67a0a0cf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12805
2954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.128052954
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.676527468
Short name T66
Test name
Test status
Simulation time 221585027 ps
CPU time 19.36 seconds
Started Apr 23 03:02:35 PM PDT 24
Finished Apr 23 03:02:54 PM PDT 24
Peak memory 248620 kb
Host smart-28e674e1-5c78-4b85-a2da-d60021070c81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67652
7468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.676527468
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.1901720906
Short name T479
Test name
Test status
Simulation time 17182149704 ps
CPU time 93.57 seconds
Started Apr 23 03:02:41 PM PDT 24
Finished Apr 23 03:04:15 PM PDT 24
Peak memory 256828 kb
Host smart-654c6f5b-7349-4526-bddd-3aa7367bb4b4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901720906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.1901720906
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.2151080104
Short name T435
Test name
Test status
Simulation time 280844536352 ps
CPU time 5529.17 seconds
Started Apr 23 03:02:40 PM PDT 24
Finished Apr 23 04:34:50 PM PDT 24
Peak memory 298772 kb
Host smart-58ef9b13-4d0d-48e5-9ace-aa74d54ae6bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151080104 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.2151080104
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.1094419626
Short name T273
Test name
Test status
Simulation time 444937400605 ps
CPU time 3310.73 seconds
Started Apr 23 03:02:51 PM PDT 24
Finished Apr 23 03:58:03 PM PDT 24
Peak memory 288824 kb
Host smart-f8545365-30a2-4df1-b4c2-247d15f40e36
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094419626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.1094419626
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.4235733224
Short name T433
Test name
Test status
Simulation time 1573547290 ps
CPU time 17.3 seconds
Started Apr 23 03:02:52 PM PDT 24
Finished Apr 23 03:03:09 PM PDT 24
Peak memory 248604 kb
Host smart-075c7824-b40c-4058-8bb1-5c15a6d79834
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4235733224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.4235733224
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.3884823978
Short name T387
Test name
Test status
Simulation time 7986733912 ps
CPU time 232.13 seconds
Started Apr 23 03:02:47 PM PDT 24
Finished Apr 23 03:06:40 PM PDT 24
Peak memory 256056 kb
Host smart-12bf801f-eb75-4175-9aba-27c43017238f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38848
23978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.3884823978
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.3238725418
Short name T358
Test name
Test status
Simulation time 520617199 ps
CPU time 12.61 seconds
Started Apr 23 03:02:44 PM PDT 24
Finished Apr 23 03:02:57 PM PDT 24
Peak memory 254560 kb
Host smart-dbac1e16-b9ad-4488-92a1-8b4d5deab4dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32387
25418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.3238725418
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.1010340706
Short name T298
Test name
Test status
Simulation time 16119146103 ps
CPU time 1433.03 seconds
Started Apr 23 03:02:51 PM PDT 24
Finished Apr 23 03:26:44 PM PDT 24
Peak memory 288620 kb
Host smart-5e81ccf8-0173-4c94-9d09-e70e3793fcd2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010340706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.1010340706
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.1717425502
Short name T485
Test name
Test status
Simulation time 120091526127 ps
CPU time 2003.61 seconds
Started Apr 23 03:02:51 PM PDT 24
Finished Apr 23 03:36:15 PM PDT 24
Peak memory 281396 kb
Host smart-b7fa7d72-be83-4e60-9dc5-7f9a7fd9ab33
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717425502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.1717425502
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.3684155053
Short name T674
Test name
Test status
Simulation time 10463716179 ps
CPU time 451.61 seconds
Started Apr 23 03:02:50 PM PDT 24
Finished Apr 23 03:10:22 PM PDT 24
Peak memory 247356 kb
Host smart-a1d38cfd-63bb-4737-a966-86bf995f5213
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684155053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.3684155053
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.950613165
Short name T410
Test name
Test status
Simulation time 1273067871 ps
CPU time 25.42 seconds
Started Apr 23 03:02:44 PM PDT 24
Finished Apr 23 03:03:10 PM PDT 24
Peak memory 248620 kb
Host smart-898ad9db-cd2f-44ad-8c7c-e445ca0981e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95061
3165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.950613165
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.2437625160
Short name T68
Test name
Test status
Simulation time 595630632 ps
CPU time 24.74 seconds
Started Apr 23 03:02:43 PM PDT 24
Finished Apr 23 03:03:08 PM PDT 24
Peak memory 247004 kb
Host smart-d33eb4c7-1fac-40e2-9302-f6145ba8656f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24376
25160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.2437625160
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.42487834
Short name T422
Test name
Test status
Simulation time 49632159 ps
CPU time 4.52 seconds
Started Apr 23 03:02:51 PM PDT 24
Finished Apr 23 03:02:55 PM PDT 24
Peak memory 238852 kb
Host smart-b82e899e-e76b-43b0-918c-1d638be5bee6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42487
834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.42487834
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.3201406511
Short name T444
Test name
Test status
Simulation time 239974703 ps
CPU time 15.81 seconds
Started Apr 23 03:02:43 PM PDT 24
Finished Apr 23 03:02:59 PM PDT 24
Peak memory 256792 kb
Host smart-0376542d-0642-46ae-bbc3-476aa24e30e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32014
06511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.3201406511
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.1006157151
Short name T541
Test name
Test status
Simulation time 31786245839 ps
CPU time 1911.38 seconds
Started Apr 23 03:02:54 PM PDT 24
Finished Apr 23 03:34:46 PM PDT 24
Peak memory 289016 kb
Host smart-ee30bba9-71bd-4e14-854a-e30ed4407d58
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006157151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.1006157151
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.333196135
Short name T43
Test name
Test status
Simulation time 67493944960 ps
CPU time 1238.03 seconds
Started Apr 23 03:02:54 PM PDT 24
Finished Apr 23 03:23:32 PM PDT 24
Peak memory 286072 kb
Host smart-1a55e282-fa71-45cf-92cd-89c42cd5fdee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333196135 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.333196135
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.1213487579
Short name T215
Test name
Test status
Simulation time 34235364 ps
CPU time 2.08 seconds
Started Apr 23 03:04:42 PM PDT 24
Finished Apr 23 03:04:45 PM PDT 24
Peak memory 248744 kb
Host smart-55d44248-23df-4bb9-8c0b-2ab8baa3eadd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1213487579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.1213487579
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.789947737
Short name T599
Test name
Test status
Simulation time 118509362243 ps
CPU time 1779.53 seconds
Started Apr 23 03:04:33 PM PDT 24
Finished Apr 23 03:34:13 PM PDT 24
Peak memory 271428 kb
Host smart-321517d8-e46a-40fc-9d68-67235b1a98bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789947737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.789947737
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.801630070
Short name T231
Test name
Test status
Simulation time 176225597 ps
CPU time 10.3 seconds
Started Apr 23 03:04:38 PM PDT 24
Finished Apr 23 03:04:48 PM PDT 24
Peak memory 252236 kb
Host smart-f3a8e25e-4c87-49af-ab56-695050370a6e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=801630070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.801630070
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.128014683
Short name T344
Test name
Test status
Simulation time 5722576514 ps
CPU time 149.64 seconds
Started Apr 23 03:04:32 PM PDT 24
Finished Apr 23 03:07:02 PM PDT 24
Peak memory 256400 kb
Host smart-c8249abd-9402-4ebd-91e2-ff92f53cc2a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12801
4683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.128014683
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.2486358243
Short name T250
Test name
Test status
Simulation time 2962479195 ps
CPU time 43.45 seconds
Started Apr 23 03:04:35 PM PDT 24
Finished Apr 23 03:05:18 PM PDT 24
Peak memory 255168 kb
Host smart-74f6795f-65c3-4b90-8981-8b588a55f38d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24863
58243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.2486358243
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.992677120
Short name T310
Test name
Test status
Simulation time 29936611691 ps
CPU time 1671.16 seconds
Started Apr 23 03:04:33 PM PDT 24
Finished Apr 23 03:32:24 PM PDT 24
Peak memory 266080 kb
Host smart-5441be83-5b86-4cf5-ab9c-9effef67792d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992677120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.992677120
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.896024513
Short name T376
Test name
Test status
Simulation time 59591734501 ps
CPU time 1703.08 seconds
Started Apr 23 03:04:35 PM PDT 24
Finished Apr 23 03:32:59 PM PDT 24
Peak memory 283128 kb
Host smart-fe54f9c8-7f97-4030-9fed-5eb8af72e3df
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896024513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.896024513
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.161315819
Short name T76
Test name
Test status
Simulation time 665860010 ps
CPU time 45.02 seconds
Started Apr 23 03:04:32 PM PDT 24
Finished Apr 23 03:05:18 PM PDT 24
Peak memory 248604 kb
Host smart-d7840b67-639f-4f90-9ed0-557edf9bc0f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16131
5819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.161315819
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.1835852262
Short name T395
Test name
Test status
Simulation time 1475457113 ps
CPU time 30.08 seconds
Started Apr 23 03:04:31 PM PDT 24
Finished Apr 23 03:05:02 PM PDT 24
Peak memory 255580 kb
Host smart-2ab696d5-1026-4825-965f-1508163b3a29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18358
52262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.1835852262
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.794851248
Short name T516
Test name
Test status
Simulation time 1097902691 ps
CPU time 63.25 seconds
Started Apr 23 03:04:32 PM PDT 24
Finished Apr 23 03:05:35 PM PDT 24
Peak memory 254800 kb
Host smart-0f574c93-44ba-40aa-af0e-98db7275eb8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79485
1248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.794851248
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.3283846735
Short name T491
Test name
Test status
Simulation time 3810803656 ps
CPU time 20.45 seconds
Started Apr 23 03:04:30 PM PDT 24
Finished Apr 23 03:04:51 PM PDT 24
Peak memory 256896 kb
Host smart-2c03c4e2-3dfe-4f48-901f-9a8c419d8d80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32838
46735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.3283846735
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.1212724779
Short name T258
Test name
Test status
Simulation time 535765747 ps
CPU time 46.61 seconds
Started Apr 23 03:04:39 PM PDT 24
Finished Apr 23 03:05:26 PM PDT 24
Peak memory 255964 kb
Host smart-7f411122-d355-4fe9-929a-2f50c9419145
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212724779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.1212724779
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.1876049910
Short name T210
Test name
Test status
Simulation time 160119278 ps
CPU time 3.57 seconds
Started Apr 23 03:04:46 PM PDT 24
Finished Apr 23 03:04:50 PM PDT 24
Peak memory 248708 kb
Host smart-fcb829bc-aa9d-4f99-b06a-ed8cfed01019
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1876049910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.1876049910
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.395565359
Short name T402
Test name
Test status
Simulation time 343786359739 ps
CPU time 1831.48 seconds
Started Apr 23 03:04:40 PM PDT 24
Finished Apr 23 03:35:12 PM PDT 24
Peak memory 266092 kb
Host smart-c3b53868-7dba-4309-8b7e-4dc6c530ba38
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395565359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.395565359
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.3785749722
Short name T408
Test name
Test status
Simulation time 182468248 ps
CPU time 10.92 seconds
Started Apr 23 03:04:44 PM PDT 24
Finished Apr 23 03:04:55 PM PDT 24
Peak memory 240432 kb
Host smart-d9ea4701-2d44-4146-b2cc-aa2265a3940c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3785749722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.3785749722
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.3021647372
Short name T437
Test name
Test status
Simulation time 1343097213 ps
CPU time 117.24 seconds
Started Apr 23 03:04:40 PM PDT 24
Finished Apr 23 03:06:38 PM PDT 24
Peak memory 256384 kb
Host smart-45bb96f7-8bc1-4815-b906-a5512d426abd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30216
47372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.3021647372
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.2602543892
Short name T546
Test name
Test status
Simulation time 1054965836 ps
CPU time 8.75 seconds
Started Apr 23 03:04:43 PM PDT 24
Finished Apr 23 03:04:52 PM PDT 24
Peak memory 251512 kb
Host smart-37f77ad4-0e54-47ed-a411-db4e4f3a1b5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26025
43892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.2602543892
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.1243027335
Short name T578
Test name
Test status
Simulation time 53594771404 ps
CPU time 977.98 seconds
Started Apr 23 03:04:43 PM PDT 24
Finished Apr 23 03:21:01 PM PDT 24
Peak memory 283344 kb
Host smart-1c8a04b2-3284-4d55-9bfc-96c987778f69
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243027335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.1243027335
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.1853192220
Short name T60
Test name
Test status
Simulation time 336660848099 ps
CPU time 3292.24 seconds
Started Apr 23 03:04:43 PM PDT 24
Finished Apr 23 03:59:36 PM PDT 24
Peak memory 289044 kb
Host smart-0b710ae1-322a-40ce-9e5f-b8e7a4fd10ab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853192220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.1853192220
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.886760241
Short name T439
Test name
Test status
Simulation time 61407644 ps
CPU time 6.59 seconds
Started Apr 23 03:04:39 PM PDT 24
Finished Apr 23 03:04:46 PM PDT 24
Peak memory 248556 kb
Host smart-187af933-6c33-4e56-9103-9e89b0a09710
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88676
0241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.886760241
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.2641344689
Short name T192
Test name
Test status
Simulation time 195597223 ps
CPU time 13.59 seconds
Started Apr 23 03:04:38 PM PDT 24
Finished Apr 23 03:04:52 PM PDT 24
Peak memory 248404 kb
Host smart-c23d4ece-5af2-4275-ae81-175c95d74f9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26413
44689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.2641344689
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.975476045
Short name T624
Test name
Test status
Simulation time 157525608 ps
CPU time 12.27 seconds
Started Apr 23 03:04:40 PM PDT 24
Finished Apr 23 03:04:52 PM PDT 24
Peak memory 256816 kb
Host smart-05db7b77-1567-457a-ab15-e50dd586500b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97547
6045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.975476045
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.1701441301
Short name T635
Test name
Test status
Simulation time 49922171343 ps
CPU time 1257.71 seconds
Started Apr 23 03:04:48 PM PDT 24
Finished Apr 23 03:25:46 PM PDT 24
Peak memory 288640 kb
Host smart-95382fd4-97bc-47c0-ac48-d07f7933aef9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701441301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.1701441301
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.3051512619
Short name T211
Test name
Test status
Simulation time 44880753 ps
CPU time 3.79 seconds
Started Apr 23 03:05:09 PM PDT 24
Finished Apr 23 03:05:13 PM PDT 24
Peak memory 248768 kb
Host smart-e4c83e9d-be0c-4bdf-b9cc-ea44802cd26b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3051512619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.3051512619
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.1833466914
Short name T9
Test name
Test status
Simulation time 57448301863 ps
CPU time 3004.96 seconds
Started Apr 23 03:05:05 PM PDT 24
Finished Apr 23 03:55:10 PM PDT 24
Peak memory 281448 kb
Host smart-aa224199-3596-4f98-91b2-d72a29b72794
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833466914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.1833466914
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.208931198
Short name T454
Test name
Test status
Simulation time 454194116 ps
CPU time 13.23 seconds
Started Apr 23 03:05:03 PM PDT 24
Finished Apr 23 03:05:16 PM PDT 24
Peak memory 240400 kb
Host smart-b25ee953-3fc1-4561-bb1f-b15d4a50a2c4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=208931198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.208931198
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.3700573032
Short name T572
Test name
Test status
Simulation time 19833845471 ps
CPU time 236.49 seconds
Started Apr 23 03:04:54 PM PDT 24
Finished Apr 23 03:08:50 PM PDT 24
Peak memory 256564 kb
Host smart-30d1f2e0-da7a-47a2-963e-987d734e0928
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37005
73032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.3700573032
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.220469523
Short name T684
Test name
Test status
Simulation time 1240280945 ps
CPU time 32.06 seconds
Started Apr 23 03:04:51 PM PDT 24
Finished Apr 23 03:05:24 PM PDT 24
Peak memory 253692 kb
Host smart-03ba9a05-6088-4b30-b41f-50f4622c9cf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22046
9523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.220469523
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.729548132
Short name T419
Test name
Test status
Simulation time 36319946846 ps
CPU time 2141.2 seconds
Started Apr 23 03:05:02 PM PDT 24
Finished Apr 23 03:40:44 PM PDT 24
Peak memory 282132 kb
Host smart-98953eb0-a767-4181-90fc-61c3e2a10996
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729548132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.729548132
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.2313127573
Short name T62
Test name
Test status
Simulation time 30465452348 ps
CPU time 345.79 seconds
Started Apr 23 03:05:02 PM PDT 24
Finished Apr 23 03:10:48 PM PDT 24
Peak memory 247416 kb
Host smart-eb549e4d-be18-4238-bc2a-45ac860d8476
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313127573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.2313127573
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.3976538896
Short name T575
Test name
Test status
Simulation time 1658149820 ps
CPU time 52.21 seconds
Started Apr 23 03:04:51 PM PDT 24
Finished Apr 23 03:05:44 PM PDT 24
Peak memory 248624 kb
Host smart-2bd99e80-c35c-4791-9111-9851c0b48ea1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39765
38896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.3976538896
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.1803835791
Short name T544
Test name
Test status
Simulation time 659978426 ps
CPU time 53 seconds
Started Apr 23 03:04:53 PM PDT 24
Finished Apr 23 03:05:46 PM PDT 24
Peak memory 247536 kb
Host smart-f092767f-98a3-44be-a213-7f34abe1d361
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18038
35791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.1803835791
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.1106495571
Short name T232
Test name
Test status
Simulation time 776352130 ps
CPU time 15.42 seconds
Started Apr 23 03:04:59 PM PDT 24
Finished Apr 23 03:05:15 PM PDT 24
Peak memory 251880 kb
Host smart-fc997030-fa0f-464b-a4cd-7603e47946e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11064
95571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.1106495571
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.2223507563
Short name T670
Test name
Test status
Simulation time 1766641568 ps
CPU time 32.16 seconds
Started Apr 23 03:04:51 PM PDT 24
Finished Apr 23 03:05:24 PM PDT 24
Peak memory 248732 kb
Host smart-49aa4e20-3f61-46f5-bbfa-ed25c50e2faf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22235
07563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.2223507563
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.59099955
Short name T115
Test name
Test status
Simulation time 66050007222 ps
CPU time 1127.01 seconds
Started Apr 23 03:05:14 PM PDT 24
Finished Apr 23 03:24:02 PM PDT 24
Peak memory 288680 kb
Host smart-861fe501-9f22-4e07-abf2-165b3e339025
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59099955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.59099955
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.3907388449
Short name T545
Test name
Test status
Simulation time 248510602 ps
CPU time 10.04 seconds
Started Apr 23 03:05:18 PM PDT 24
Finished Apr 23 03:05:28 PM PDT 24
Peak memory 240464 kb
Host smart-eb004992-b646-414b-83e3-185cfdf131ee
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3907388449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.3907388449
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.872077924
Short name T605
Test name
Test status
Simulation time 1941002563 ps
CPU time 104.67 seconds
Started Apr 23 03:05:11 PM PDT 24
Finished Apr 23 03:06:56 PM PDT 24
Peak memory 256428 kb
Host smart-f09c3f6a-1c2f-4b90-97b2-14cff26147ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87207
7924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.872077924
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.3292856950
Short name T50
Test name
Test status
Simulation time 423728008 ps
CPU time 27.96 seconds
Started Apr 23 03:05:10 PM PDT 24
Finished Apr 23 03:05:38 PM PDT 24
Peak memory 254136 kb
Host smart-238604e5-1d09-4500-9492-dc1d934bf215
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32928
56950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.3292856950
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.992721807
Short name T547
Test name
Test status
Simulation time 12958147241 ps
CPU time 1441.91 seconds
Started Apr 23 03:05:14 PM PDT 24
Finished Apr 23 03:29:16 PM PDT 24
Peak memory 288660 kb
Host smart-9e320ad8-c361-416a-b9e1-1d5e5a1b3891
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992721807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.992721807
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.2391376055
Short name T667
Test name
Test status
Simulation time 26157594938 ps
CPU time 1094.26 seconds
Started Apr 23 03:05:11 PM PDT 24
Finished Apr 23 03:23:26 PM PDT 24
Peak memory 289380 kb
Host smart-9bd8f300-14a1-4ea9-8f1a-dcbde6e19272
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391376055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.2391376055
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.519495220
Short name T293
Test name
Test status
Simulation time 36381062577 ps
CPU time 407.84 seconds
Started Apr 23 03:05:14 PM PDT 24
Finished Apr 23 03:12:02 PM PDT 24
Peak memory 247652 kb
Host smart-e1fc36f2-d29a-48cd-91f4-8b139df5501c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519495220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.519495220
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.125667863
Short name T347
Test name
Test status
Simulation time 305134026 ps
CPU time 11.5 seconds
Started Apr 23 03:05:12 PM PDT 24
Finished Apr 23 03:05:23 PM PDT 24
Peak memory 248528 kb
Host smart-a6762a05-44db-4db3-a512-d6a1bbcff5f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12566
7863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.125667863
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.3263956592
Short name T589
Test name
Test status
Simulation time 1612761364 ps
CPU time 49.62 seconds
Started Apr 23 03:05:11 PM PDT 24
Finished Apr 23 03:06:01 PM PDT 24
Peak memory 255064 kb
Host smart-43d172a4-75a6-45a9-af1b-3a961cfb1740
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32639
56592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.3263956592
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.2797429986
Short name T456
Test name
Test status
Simulation time 1303831694 ps
CPU time 50.12 seconds
Started Apr 23 03:05:12 PM PDT 24
Finished Apr 23 03:06:02 PM PDT 24
Peak memory 255156 kb
Host smart-d480b312-f38c-46b1-ab12-01663a817aee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27974
29986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.2797429986
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.1629978650
Short name T594
Test name
Test status
Simulation time 1700416510 ps
CPU time 44.57 seconds
Started Apr 23 03:05:11 PM PDT 24
Finished Apr 23 03:05:56 PM PDT 24
Peak memory 248776 kb
Host smart-5e7e44e7-6e73-4cc6-95ff-ad85f7e6ca93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16299
78650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.1629978650
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.3082855173
Short name T536
Test name
Test status
Simulation time 8364094191 ps
CPU time 132.83 seconds
Started Apr 23 03:05:15 PM PDT 24
Finished Apr 23 03:07:28 PM PDT 24
Peak memory 256900 kb
Host smart-1009a2b8-2fdd-4a3c-a712-8276f189fe1a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082855173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.3082855173
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.2612485047
Short name T369
Test name
Test status
Simulation time 59255321140 ps
CPU time 1727.31 seconds
Started Apr 23 03:05:23 PM PDT 24
Finished Apr 23 03:34:11 PM PDT 24
Peak memory 273256 kb
Host smart-1ff1a40f-0ada-4545-8043-95cb5f5c5418
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612485047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.2612485047
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.3596063939
Short name T682
Test name
Test status
Simulation time 792448126 ps
CPU time 35.49 seconds
Started Apr 23 03:05:22 PM PDT 24
Finished Apr 23 03:05:58 PM PDT 24
Peak memory 240404 kb
Host smart-4ce00700-9657-41c4-a545-9ed0b88d36d0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3596063939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.3596063939
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.1337048983
Short name T520
Test name
Test status
Simulation time 5946648030 ps
CPU time 65.76 seconds
Started Apr 23 03:05:22 PM PDT 24
Finished Apr 23 03:06:28 PM PDT 24
Peak memory 248212 kb
Host smart-e610a648-f48d-4b63-a97a-ce6c50ba0b41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13370
48983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.1337048983
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.1950333412
Short name T646
Test name
Test status
Simulation time 1155250109 ps
CPU time 20.25 seconds
Started Apr 23 03:05:19 PM PDT 24
Finished Apr 23 03:05:40 PM PDT 24
Peak memory 248184 kb
Host smart-d1dab86e-99b7-4215-b9fa-afe6e37e6170
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19503
33412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.1950333412
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.3714360398
Short name T688
Test name
Test status
Simulation time 174117234797 ps
CPU time 2102.2 seconds
Started Apr 23 03:05:25 PM PDT 24
Finished Apr 23 03:40:28 PM PDT 24
Peak memory 288244 kb
Host smart-570bb4ec-f53d-427b-9dda-499add49150a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714360398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.3714360398
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.3718607058
Short name T271
Test name
Test status
Simulation time 50894922136 ps
CPU time 1434.36 seconds
Started Apr 23 03:05:25 PM PDT 24
Finished Apr 23 03:29:20 PM PDT 24
Peak memory 272536 kb
Host smart-3822effd-1cf3-4ca2-a4c9-9650a8dbf3a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718607058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.3718607058
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.2437876939
Short name T268
Test name
Test status
Simulation time 1311933448 ps
CPU time 29.58 seconds
Started Apr 23 03:05:20 PM PDT 24
Finished Apr 23 03:05:50 PM PDT 24
Peak memory 255852 kb
Host smart-58ad7f74-c3bf-4e31-a190-938101682623
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24378
76939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.2437876939
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.3030466927
Short name T396
Test name
Test status
Simulation time 1785153139 ps
CPU time 52.52 seconds
Started Apr 23 03:05:20 PM PDT 24
Finished Apr 23 03:06:12 PM PDT 24
Peak memory 253768 kb
Host smart-33e857f8-8195-42f8-b43f-2df9fefeeda0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30304
66927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.3030466927
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.3543253247
Short name T120
Test name
Test status
Simulation time 921766539 ps
CPU time 26.1 seconds
Started Apr 23 03:05:22 PM PDT 24
Finished Apr 23 03:05:49 PM PDT 24
Peak memory 248596 kb
Host smart-8a395509-0a6a-4e36-99d9-4f4f23680247
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35432
53247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.3543253247
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.4195436446
Short name T218
Test name
Test status
Simulation time 56869897 ps
CPU time 3.27 seconds
Started Apr 23 03:05:48 PM PDT 24
Finished Apr 23 03:05:52 PM PDT 24
Peak memory 248804 kb
Host smart-a9cc0f81-d315-48d6-91f4-4c624442e4ef
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4195436446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.4195436446
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.4153752830
Short name T645
Test name
Test status
Simulation time 12024447650 ps
CPU time 1078.15 seconds
Started Apr 23 03:05:46 PM PDT 24
Finished Apr 23 03:23:45 PM PDT 24
Peak memory 273268 kb
Host smart-682ead68-a83d-4b9d-9ecf-14a7cef65fe2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153752830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.4153752830
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.1231226974
Short name T452
Test name
Test status
Simulation time 532029866 ps
CPU time 8.34 seconds
Started Apr 23 03:05:48 PM PDT 24
Finished Apr 23 03:05:56 PM PDT 24
Peak memory 240356 kb
Host smart-f3132396-fb39-4b86-9f23-51430596a564
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1231226974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.1231226974
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.1066933552
Short name T584
Test name
Test status
Simulation time 5349713866 ps
CPU time 57.52 seconds
Started Apr 23 03:05:44 PM PDT 24
Finished Apr 23 03:06:42 PM PDT 24
Peak memory 248712 kb
Host smart-4352397d-35a1-410e-b209-127c54157edd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10669
33552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.1066933552
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.1141382659
Short name T354
Test name
Test status
Simulation time 2788861013 ps
CPU time 21.42 seconds
Started Apr 23 03:05:44 PM PDT 24
Finished Apr 23 03:06:05 PM PDT 24
Peak memory 248780 kb
Host smart-c9ba3f9d-2796-44ca-9f94-a2c3d8ea1dea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11413
82659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.1141382659
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.2965427683
Short name T325
Test name
Test status
Simulation time 80759824141 ps
CPU time 2339.05 seconds
Started Apr 23 03:05:45 PM PDT 24
Finished Apr 23 03:44:45 PM PDT 24
Peak memory 286996 kb
Host smart-4781ca49-1501-4104-8c53-72d52d0ff11f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965427683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.2965427683
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.266144574
Short name T386
Test name
Test status
Simulation time 2170371362 ps
CPU time 76.22 seconds
Started Apr 23 03:05:37 PM PDT 24
Finished Apr 23 03:06:53 PM PDT 24
Peak memory 248684 kb
Host smart-c8dbae16-1259-48ae-8ab3-999ec1c3edc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26614
4574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.266144574
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.2318343120
Short name T425
Test name
Test status
Simulation time 860415955 ps
CPU time 15.22 seconds
Started Apr 23 03:05:44 PM PDT 24
Finished Apr 23 03:05:59 PM PDT 24
Peak memory 251588 kb
Host smart-f596e8c4-16da-4b9f-8d10-31ad5c3e9b3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23183
43120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.2318343120
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.4166102844
Short name T221
Test name
Test status
Simulation time 167876160 ps
CPU time 10.31 seconds
Started Apr 23 03:05:46 PM PDT 24
Finished Apr 23 03:05:57 PM PDT 24
Peak memory 255452 kb
Host smart-1741681b-84b5-49ad-8c42-b8ec88d89ac9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41661
02844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.4166102844
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.1975469475
Short name T348
Test name
Test status
Simulation time 10318292584 ps
CPU time 68.18 seconds
Started Apr 23 03:05:32 PM PDT 24
Finished Apr 23 03:06:41 PM PDT 24
Peak memory 248632 kb
Host smart-ad2d2faf-c855-4da7-97ec-2287eacdab31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19754
69475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.1975469475
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.1298457681
Short name T523
Test name
Test status
Simulation time 11655694897 ps
CPU time 1397.56 seconds
Started Apr 23 03:05:49 PM PDT 24
Finished Apr 23 03:29:07 PM PDT 24
Peak memory 288980 kb
Host smart-470626e6-0878-4b8c-98c9-a3c8e69a75a2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298457681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.1298457681
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.1583538574
Short name T205
Test name
Test status
Simulation time 20760787 ps
CPU time 2.68 seconds
Started Apr 23 03:06:09 PM PDT 24
Finished Apr 23 03:06:12 PM PDT 24
Peak memory 248848 kb
Host smart-2c27effb-389c-40e4-a23a-956863b98b82
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1583538574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.1583538574
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.4163224367
Short name T424
Test name
Test status
Simulation time 2191946578 ps
CPU time 24.03 seconds
Started Apr 23 03:06:05 PM PDT 24
Finished Apr 23 03:06:29 PM PDT 24
Peak memory 240480 kb
Host smart-7d64990c-a673-49f4-af54-72483b199bc6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4163224367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.4163224367
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.2220268801
Short name T457
Test name
Test status
Simulation time 3647746653 ps
CPU time 94.05 seconds
Started Apr 23 03:05:54 PM PDT 24
Finished Apr 23 03:07:28 PM PDT 24
Peak memory 256028 kb
Host smart-7977b9da-2164-4063-8ce7-bce6506375a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22202
68801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.2220268801
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.3566663234
Short name T458
Test name
Test status
Simulation time 2444679002 ps
CPU time 37.74 seconds
Started Apr 23 03:05:56 PM PDT 24
Finished Apr 23 03:06:34 PM PDT 24
Peak memory 255860 kb
Host smart-aea9faca-0c36-46a5-9a19-4139677bfc4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35666
63234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.3566663234
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.3059965404
Short name T628
Test name
Test status
Simulation time 214433228119 ps
CPU time 2719.45 seconds
Started Apr 23 03:06:01 PM PDT 24
Finished Apr 23 03:51:21 PM PDT 24
Peak memory 285320 kb
Host smart-eac5c4b4-f8ee-4ed0-a5a1-17c5c1aaaced
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059965404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.3059965404
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.2560842479
Short name T412
Test name
Test status
Simulation time 126416342905 ps
CPU time 1910.49 seconds
Started Apr 23 03:06:02 PM PDT 24
Finished Apr 23 03:37:53 PM PDT 24
Peak memory 273168 kb
Host smart-4730d501-31e9-4a0d-98c7-f7f2c441653f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560842479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.2560842479
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.1844223260
Short name T525
Test name
Test status
Simulation time 8299198548 ps
CPU time 350.64 seconds
Started Apr 23 03:06:02 PM PDT 24
Finished Apr 23 03:11:52 PM PDT 24
Peak memory 247384 kb
Host smart-5100a25f-ee39-4e3e-b6fa-8c8ca10656c0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844223260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.1844223260
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.301058446
Short name T92
Test name
Test status
Simulation time 240237170 ps
CPU time 26.06 seconds
Started Apr 23 03:05:50 PM PDT 24
Finished Apr 23 03:06:16 PM PDT 24
Peak memory 255404 kb
Host smart-9b526a9c-96f5-4387-9c76-d3463b4e6549
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30105
8446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.301058446
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.1910236486
Short name T644
Test name
Test status
Simulation time 92570333 ps
CPU time 9.52 seconds
Started Apr 23 03:05:54 PM PDT 24
Finished Apr 23 03:06:04 PM PDT 24
Peak memory 253296 kb
Host smart-ca8a3167-1eaa-441c-a84b-eba177afc35c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19102
36486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.1910236486
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.2739637756
Short name T537
Test name
Test status
Simulation time 440183584 ps
CPU time 33.5 seconds
Started Apr 23 03:05:54 PM PDT 24
Finished Apr 23 03:06:28 PM PDT 24
Peak memory 246932 kb
Host smart-eb400794-db98-4cc1-b7ef-44c5620ba824
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27396
37756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.2739637756
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.137063590
Short name T662
Test name
Test status
Simulation time 1091544562 ps
CPU time 36.16 seconds
Started Apr 23 03:05:50 PM PDT 24
Finished Apr 23 03:06:26 PM PDT 24
Peak memory 248240 kb
Host smart-3225a770-a252-4d13-bac8-cae322de47c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13706
3590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.137063590
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.3654853772
Short name T266
Test name
Test status
Simulation time 105445943465 ps
CPU time 1708.35 seconds
Started Apr 23 03:06:09 PM PDT 24
Finished Apr 23 03:34:38 PM PDT 24
Peak memory 288744 kb
Host smart-b4623979-a378-476e-8aec-b291fea46b55
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654853772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.3654853772
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.3537738430
Short name T212
Test name
Test status
Simulation time 16683276 ps
CPU time 3.52 seconds
Started Apr 23 03:06:26 PM PDT 24
Finished Apr 23 03:06:30 PM PDT 24
Peak memory 248740 kb
Host smart-2b0ea895-bfe1-4648-ab1f-c3425c53fcd8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3537738430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.3537738430
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.3897095709
Short name T528
Test name
Test status
Simulation time 24804816423 ps
CPU time 1383.75 seconds
Started Apr 23 03:06:21 PM PDT 24
Finished Apr 23 03:29:25 PM PDT 24
Peak memory 272976 kb
Host smart-f9dbdd40-a940-4031-942e-39ed71906119
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897095709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.3897095709
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.1421067936
Short name T366
Test name
Test status
Simulation time 296449200 ps
CPU time 14.77 seconds
Started Apr 23 03:06:22 PM PDT 24
Finished Apr 23 03:06:37 PM PDT 24
Peak memory 248592 kb
Host smart-387c3c10-6db7-4cbb-b942-143fa623df19
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1421067936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.1421067936
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.2670861949
Short name T365
Test name
Test status
Simulation time 14849348226 ps
CPU time 243.88 seconds
Started Apr 23 03:06:20 PM PDT 24
Finished Apr 23 03:10:24 PM PDT 24
Peak memory 256176 kb
Host smart-0c908892-4794-4f12-926b-079ae2bc3bbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26708
61949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.2670861949
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.4066458363
Short name T249
Test name
Test status
Simulation time 800556025 ps
CPU time 13.3 seconds
Started Apr 23 03:06:17 PM PDT 24
Finished Apr 23 03:06:30 PM PDT 24
Peak memory 252712 kb
Host smart-af0bb1ca-b305-469f-a4f1-1f94b5a04359
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40664
58363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.4066458363
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.3687144576
Short name T510
Test name
Test status
Simulation time 30942913057 ps
CPU time 1289.33 seconds
Started Apr 23 03:06:24 PM PDT 24
Finished Apr 23 03:27:54 PM PDT 24
Peak memory 273240 kb
Host smart-c47285f5-5d62-41e8-9d77-bbbdc849ead4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687144576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.3687144576
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.3103020130
Short name T502
Test name
Test status
Simulation time 28754283109 ps
CPU time 1722.25 seconds
Started Apr 23 03:06:23 PM PDT 24
Finished Apr 23 03:35:05 PM PDT 24
Peak memory 273240 kb
Host smart-43969fd2-d921-45ae-af31-4f3bbd028700
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103020130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.3103020130
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.2703028140
Short name T617
Test name
Test status
Simulation time 92303960 ps
CPU time 9.94 seconds
Started Apr 23 03:06:09 PM PDT 24
Finished Apr 23 03:06:19 PM PDT 24
Peak memory 248788 kb
Host smart-b67741d6-2a66-4912-ad2c-2a15df301a02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27030
28140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.2703028140
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.338723686
Short name T397
Test name
Test status
Simulation time 487353953 ps
CPU time 11.29 seconds
Started Apr 23 03:06:11 PM PDT 24
Finished Apr 23 03:06:23 PM PDT 24
Peak memory 247080 kb
Host smart-9c2ffc1b-e7b1-43c5-939e-bc0f69ba1c2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33872
3686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.338723686
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.2575952986
Short name T100
Test name
Test status
Simulation time 537639372 ps
CPU time 11.43 seconds
Started Apr 23 03:06:19 PM PDT 24
Finished Apr 23 03:06:31 PM PDT 24
Peak memory 253568 kb
Host smart-f716417a-c69e-4e7b-9a06-45a9088a5f54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25759
52986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.2575952986
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.3300979136
Short name T517
Test name
Test status
Simulation time 769590562 ps
CPU time 46.82 seconds
Started Apr 23 03:06:10 PM PDT 24
Finished Apr 23 03:06:57 PM PDT 24
Peak memory 255600 kb
Host smart-ed058c5b-193b-4768-b68f-98bcf9d544b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33009
79136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.3300979136
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.2453016158
Short name T471
Test name
Test status
Simulation time 46017129832 ps
CPU time 1690.42 seconds
Started Apr 23 03:06:25 PM PDT 24
Finished Apr 23 03:34:36 PM PDT 24
Peak memory 288892 kb
Host smart-7530bef4-9d07-4a5e-b140-fb6e037d8472
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453016158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.2453016158
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.1551274670
Short name T214
Test name
Test status
Simulation time 45860748 ps
CPU time 3.3 seconds
Started Apr 23 03:06:37 PM PDT 24
Finished Apr 23 03:06:41 PM PDT 24
Peak memory 248780 kb
Host smart-f15ada10-c62d-44b7-8b29-a2ba634e0984
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1551274670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.1551274670
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.1315647111
Short name T90
Test name
Test status
Simulation time 11126827148 ps
CPU time 909.32 seconds
Started Apr 23 03:06:34 PM PDT 24
Finished Apr 23 03:21:43 PM PDT 24
Peak memory 273252 kb
Host smart-974def0c-4380-40a6-8be8-7b7b7f8b2e54
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315647111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.1315647111
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.3370922220
Short name T475
Test name
Test status
Simulation time 2193936558 ps
CPU time 28.45 seconds
Started Apr 23 03:06:37 PM PDT 24
Finished Apr 23 03:07:05 PM PDT 24
Peak memory 252404 kb
Host smart-3a617754-3ae8-4e1f-951d-f916dffff314
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3370922220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.3370922220
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.914541290
Short name T654
Test name
Test status
Simulation time 1426655318 ps
CPU time 19.97 seconds
Started Apr 23 03:06:33 PM PDT 24
Finished Apr 23 03:06:53 PM PDT 24
Peak memory 255540 kb
Host smart-6f398639-4c82-421a-b614-fca4ab0540a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91454
1290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.914541290
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.3873178980
Short name T514
Test name
Test status
Simulation time 238933414 ps
CPU time 17.96 seconds
Started Apr 23 03:06:33 PM PDT 24
Finished Apr 23 03:06:51 PM PDT 24
Peak memory 254720 kb
Host smart-51bffa24-4225-4f27-9b48-0528f00ea258
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38731
78980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.3873178980
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.1155206971
Short name T194
Test name
Test status
Simulation time 11573172507 ps
CPU time 724.97 seconds
Started Apr 23 03:06:33 PM PDT 24
Finished Apr 23 03:18:39 PM PDT 24
Peak memory 272776 kb
Host smart-66120e24-a085-41ad-ba0e-0de92d0d60ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155206971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.1155206971
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.3097238740
Short name T642
Test name
Test status
Simulation time 65435676946 ps
CPU time 1871.54 seconds
Started Apr 23 03:06:37 PM PDT 24
Finished Apr 23 03:37:49 PM PDT 24
Peak memory 288504 kb
Host smart-5d37315b-1127-4223-8b32-b3446deb783a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097238740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.3097238740
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.1672911697
Short name T571
Test name
Test status
Simulation time 22839123695 ps
CPU time 462.15 seconds
Started Apr 23 03:06:33 PM PDT 24
Finished Apr 23 03:14:16 PM PDT 24
Peak memory 248688 kb
Host smart-b1ed350b-28d9-4958-93a0-24694c361e5a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672911697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.1672911697
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.3835356052
Short name T675
Test name
Test status
Simulation time 1963151163 ps
CPU time 26.93 seconds
Started Apr 23 03:06:31 PM PDT 24
Finished Apr 23 03:06:59 PM PDT 24
Peak memory 248656 kb
Host smart-d3314ff5-e9e9-4e93-9bd4-00c82b79d88b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38353
56052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.3835356052
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.2572202056
Short name T69
Test name
Test status
Simulation time 5823659897 ps
CPU time 28.17 seconds
Started Apr 23 03:06:32 PM PDT 24
Finished Apr 23 03:07:01 PM PDT 24
Peak memory 246832 kb
Host smart-a0172ddd-fcde-4579-b91b-edc4fc45722d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25722
02056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.2572202056
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.1891179330
Short name T482
Test name
Test status
Simulation time 90252366 ps
CPU time 4.44 seconds
Started Apr 23 03:06:34 PM PDT 24
Finished Apr 23 03:06:39 PM PDT 24
Peak memory 238768 kb
Host smart-d65055ea-c949-489d-aeeb-2f9bcd97e828
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18911
79330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.1891179330
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.2824546545
Short name T620
Test name
Test status
Simulation time 2307259851 ps
CPU time 43.29 seconds
Started Apr 23 03:06:33 PM PDT 24
Finished Apr 23 03:07:17 PM PDT 24
Peak memory 248704 kb
Host smart-6cdb4e1b-8e4e-4dc8-8713-3aad11019242
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28245
46545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.2824546545
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.4002919321
Short name T428
Test name
Test status
Simulation time 9644039938 ps
CPU time 165.61 seconds
Started Apr 23 03:06:37 PM PDT 24
Finished Apr 23 03:09:23 PM PDT 24
Peak memory 256816 kb
Host smart-74ba67a9-4c32-4c22-9654-7b7d5c44be84
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002919321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.4002919321
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.310995015
Short name T47
Test name
Test status
Simulation time 46542810533 ps
CPU time 2917.96 seconds
Started Apr 23 03:06:40 PM PDT 24
Finished Apr 23 03:55:19 PM PDT 24
Peak memory 304252 kb
Host smart-8470307d-6616-4b1c-9642-c6125ce95880
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310995015 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.310995015
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.3108553442
Short name T209
Test name
Test status
Simulation time 169460295 ps
CPU time 3.9 seconds
Started Apr 23 03:07:02 PM PDT 24
Finished Apr 23 03:07:06 PM PDT 24
Peak memory 248748 kb
Host smart-950208ae-83d5-4701-8f0d-ec4fe5af1fc5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3108553442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.3108553442
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.51631812
Short name T591
Test name
Test status
Simulation time 9603190013 ps
CPU time 866.56 seconds
Started Apr 23 03:06:50 PM PDT 24
Finished Apr 23 03:21:17 PM PDT 24
Peak memory 273212 kb
Host smart-e29bb8ac-e43e-43dc-95ac-6d24ea0e566e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51631812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.51631812
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.953033540
Short name T548
Test name
Test status
Simulation time 3389253897 ps
CPU time 30.67 seconds
Started Apr 23 03:06:55 PM PDT 24
Finished Apr 23 03:07:26 PM PDT 24
Peak memory 240500 kb
Host smart-3826fab1-8431-4bac-b3a3-711676bccd1f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=953033540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.953033540
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.742750351
Short name T363
Test name
Test status
Simulation time 4008167587 ps
CPU time 214.19 seconds
Started Apr 23 03:06:44 PM PDT 24
Finished Apr 23 03:10:19 PM PDT 24
Peak memory 256328 kb
Host smart-51c945a1-f3c4-4831-b940-de179c9541fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74275
0351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.742750351
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.668858567
Short name T88
Test name
Test status
Simulation time 46368925 ps
CPU time 3.67 seconds
Started Apr 23 03:06:44 PM PDT 24
Finished Apr 23 03:06:48 PM PDT 24
Peak memory 240440 kb
Host smart-fb998259-449e-47e3-9854-51a0c9b16479
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66885
8567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.668858567
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.3254359162
Short name T326
Test name
Test status
Simulation time 134755269362 ps
CPU time 2064.37 seconds
Started Apr 23 03:06:50 PM PDT 24
Finished Apr 23 03:41:15 PM PDT 24
Peak memory 282640 kb
Host smart-a86a9b31-c91f-4677-850e-9619a43ccf78
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254359162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.3254359162
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.3663145912
Short name T530
Test name
Test status
Simulation time 155055110646 ps
CPU time 2384.43 seconds
Started Apr 23 03:06:50 PM PDT 24
Finished Apr 23 03:46:35 PM PDT 24
Peak memory 289444 kb
Host smart-b6d76790-593f-43a1-8079-35ddfeea98a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663145912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.3663145912
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.3831640622
Short name T59
Test name
Test status
Simulation time 6195362272 ps
CPU time 260.37 seconds
Started Apr 23 03:06:49 PM PDT 24
Finished Apr 23 03:11:10 PM PDT 24
Peak memory 247684 kb
Host smart-7985cba9-97cf-4d5b-aff5-23059802d29c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831640622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.3831640622
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.3055613524
Short name T650
Test name
Test status
Simulation time 1733735990 ps
CPU time 29.25 seconds
Started Apr 23 03:06:46 PM PDT 24
Finished Apr 23 03:07:16 PM PDT 24
Peak memory 255204 kb
Host smart-73818ca4-0ff5-4c2f-8225-0c414da0e848
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30556
13524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.3055613524
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.1401170461
Short name T583
Test name
Test status
Simulation time 1133038957 ps
CPU time 25.49 seconds
Started Apr 23 03:06:45 PM PDT 24
Finished Apr 23 03:07:11 PM PDT 24
Peak memory 254400 kb
Host smart-eced894d-728e-4f19-8962-57798657ddbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14011
70461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.1401170461
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.1195943951
Short name T257
Test name
Test status
Simulation time 1226483507 ps
CPU time 48.08 seconds
Started Apr 23 03:06:49 PM PDT 24
Finished Apr 23 03:07:38 PM PDT 24
Peak memory 255016 kb
Host smart-f55e8c83-1d74-4a63-8f42-e403ecb3e4e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11959
43951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.1195943951
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.2212669447
Short name T65
Test name
Test status
Simulation time 1450535960 ps
CPU time 56.15 seconds
Started Apr 23 03:06:45 PM PDT 24
Finished Apr 23 03:07:42 PM PDT 24
Peak memory 256780 kb
Host smart-479518e0-95b3-4964-9542-5f69d4d16afa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22126
69447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.2212669447
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.4143847223
Short name T678
Test name
Test status
Simulation time 128809978672 ps
CPU time 2894.08 seconds
Started Apr 23 03:07:02 PM PDT 24
Finished Apr 23 03:55:16 PM PDT 24
Peak memory 289096 kb
Host smart-252982cd-f6a4-4333-b1d5-389f862abeac
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143847223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.4143847223
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.1978219729
Short name T204
Test name
Test status
Simulation time 34509688 ps
CPU time 3.84 seconds
Started Apr 23 03:03:01 PM PDT 24
Finished Apr 23 03:03:05 PM PDT 24
Peak memory 248792 kb
Host smart-2d29079e-500e-4f71-b12a-ae63711edb08
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1978219729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.1978219729
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.2280650173
Short name T451
Test name
Test status
Simulation time 12667729968 ps
CPU time 698.41 seconds
Started Apr 23 03:02:58 PM PDT 24
Finished Apr 23 03:14:37 PM PDT 24
Peak memory 265088 kb
Host smart-4e28a765-c60c-4b55-a142-e6af199da187
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280650173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.2280650173
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.2168594542
Short name T393
Test name
Test status
Simulation time 144049898 ps
CPU time 9.81 seconds
Started Apr 23 03:02:59 PM PDT 24
Finished Apr 23 03:03:09 PM PDT 24
Peak memory 240420 kb
Host smart-9a13cc60-04d1-43d0-9a27-4aa184e7c28e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2168594542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.2168594542
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.1431958381
Short name T607
Test name
Test status
Simulation time 1107524949 ps
CPU time 92.7 seconds
Started Apr 23 03:03:03 PM PDT 24
Finished Apr 23 03:04:36 PM PDT 24
Peak memory 256284 kb
Host smart-147a085f-fae6-4495-b7fb-fc8ba746aca8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14319
58381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.1431958381
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.1522475717
Short name T681
Test name
Test status
Simulation time 619421419 ps
CPU time 14.65 seconds
Started Apr 23 03:02:59 PM PDT 24
Finished Apr 23 03:03:14 PM PDT 24
Peak memory 254888 kb
Host smart-beeb2a6d-5c5b-4565-a5f7-083c89837638
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15224
75717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.1522475717
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.2941789162
Short name T625
Test name
Test status
Simulation time 29196548358 ps
CPU time 1705.22 seconds
Started Apr 23 03:03:03 PM PDT 24
Finished Apr 23 03:31:28 PM PDT 24
Peak memory 273048 kb
Host smart-ff236551-14fb-4c8e-97c2-d593016d85d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941789162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.2941789162
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.1456634444
Short name T295
Test name
Test status
Simulation time 26042009306 ps
CPU time 265.78 seconds
Started Apr 23 03:02:57 PM PDT 24
Finished Apr 23 03:07:23 PM PDT 24
Peak memory 246624 kb
Host smart-bda0c801-745a-464d-bf37-a4d4c5ec5232
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456634444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.1456634444
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.739552474
Short name T378
Test name
Test status
Simulation time 486980100 ps
CPU time 19.7 seconds
Started Apr 23 03:03:01 PM PDT 24
Finished Apr 23 03:03:21 PM PDT 24
Peak memory 255588 kb
Host smart-586549bd-513a-440a-b94b-d792365a2946
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73955
2474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.739552474
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.1978788822
Short name T480
Test name
Test status
Simulation time 354141022 ps
CPU time 32.56 seconds
Started Apr 23 03:02:59 PM PDT 24
Finished Apr 23 03:03:32 PM PDT 24
Peak memory 255248 kb
Host smart-a8542ae8-a1c8-4866-9738-976288a56eaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19787
88822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.1978788822
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.3843739002
Short name T429
Test name
Test status
Simulation time 138451357 ps
CPU time 20.45 seconds
Started Apr 23 03:03:03 PM PDT 24
Finished Apr 23 03:03:24 PM PDT 24
Peak memory 246980 kb
Host smart-da89abb0-4789-4884-99cb-d1ccacf6551d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38437
39002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.3843739002
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.2317405813
Short name T580
Test name
Test status
Simulation time 285753850 ps
CPU time 15.55 seconds
Started Apr 23 03:02:59 PM PDT 24
Finished Apr 23 03:03:15 PM PDT 24
Peak memory 248628 kb
Host smart-0707dafb-0ff8-4d49-986a-4a1ccdf1174f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23174
05813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.2317405813
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.1175361596
Short name T117
Test name
Test status
Simulation time 52237260099 ps
CPU time 1655.05 seconds
Started Apr 23 03:07:01 PM PDT 24
Finished Apr 23 03:34:36 PM PDT 24
Peak memory 273040 kb
Host smart-45f970d5-3777-4ee3-88de-79c1e3a69fde
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175361596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.1175361596
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.2967877750
Short name T436
Test name
Test status
Simulation time 6724497590 ps
CPU time 161.97 seconds
Started Apr 23 03:07:02 PM PDT 24
Finished Apr 23 03:09:44 PM PDT 24
Peak memory 256836 kb
Host smart-df194db4-f776-4268-8d94-4e05b1f0a0d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29678
77750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.2967877750
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.3909756776
Short name T657
Test name
Test status
Simulation time 754602890 ps
CPU time 8.89 seconds
Started Apr 23 03:07:05 PM PDT 24
Finished Apr 23 03:07:14 PM PDT 24
Peak memory 249432 kb
Host smart-98d0f529-fd59-4e82-b9e0-17186a806ef2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39097
56776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.3909756776
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.999018004
Short name T324
Test name
Test status
Simulation time 111218123210 ps
CPU time 2764.25 seconds
Started Apr 23 03:07:01 PM PDT 24
Finished Apr 23 03:53:06 PM PDT 24
Peak memory 287564 kb
Host smart-377405d4-769c-44b8-9e16-a05ca31138ac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999018004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.999018004
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.2973996370
Short name T300
Test name
Test status
Simulation time 10012909046 ps
CPU time 110.33 seconds
Started Apr 23 03:07:04 PM PDT 24
Finished Apr 23 03:08:55 PM PDT 24
Peak memory 247636 kb
Host smart-5351f2a3-4812-4549-9060-dcc0a6c7f919
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973996370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.2973996370
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.2051981210
Short name T379
Test name
Test status
Simulation time 91720970 ps
CPU time 4.48 seconds
Started Apr 23 03:06:58 PM PDT 24
Finished Apr 23 03:07:03 PM PDT 24
Peak memory 240672 kb
Host smart-41da282c-7392-41b5-9d08-b2f6736c7c0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20519
81210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.2051981210
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.3281194799
Short name T73
Test name
Test status
Simulation time 493009364 ps
CPU time 32.66 seconds
Started Apr 23 03:06:58 PM PDT 24
Finished Apr 23 03:07:31 PM PDT 24
Peak memory 255060 kb
Host smart-1ecd13a7-5d60-4164-a90c-7c6832df1b6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32811
94799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.3281194799
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.1289830561
Short name T515
Test name
Test status
Simulation time 345397834 ps
CPU time 25.8 seconds
Started Apr 23 03:07:06 PM PDT 24
Finished Apr 23 03:07:32 PM PDT 24
Peak memory 255352 kb
Host smart-cb337945-b070-495c-9e0a-3b8f884e3c13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12898
30561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.1289830561
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.1509321339
Short name T466
Test name
Test status
Simulation time 239878743 ps
CPU time 28.04 seconds
Started Apr 23 03:06:59 PM PDT 24
Finished Apr 23 03:07:28 PM PDT 24
Peak memory 248712 kb
Host smart-046ae94d-d839-4372-8cfe-1297befe3578
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15093
21339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.1509321339
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.1758146666
Short name T278
Test name
Test status
Simulation time 3878968704 ps
CPU time 237.92 seconds
Started Apr 23 03:07:09 PM PDT 24
Finished Apr 23 03:11:08 PM PDT 24
Peak memory 251384 kb
Host smart-23d164ff-b82f-4304-a2e0-b3e70e87fdd9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758146666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.1758146666
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.1907095543
Short name T75
Test name
Test status
Simulation time 50282482539 ps
CPU time 2686.89 seconds
Started Apr 23 03:07:13 PM PDT 24
Finished Apr 23 03:52:00 PM PDT 24
Peak memory 289032 kb
Host smart-8ed6dbe2-6aa2-4c0c-a174-5f392c5563d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907095543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.1907095543
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.4022325022
Short name T394
Test name
Test status
Simulation time 1247004180 ps
CPU time 75.77 seconds
Started Apr 23 03:07:13 PM PDT 24
Finished Apr 23 03:08:29 PM PDT 24
Peak memory 255820 kb
Host smart-1fec3659-7edc-449c-b8ba-93c595077c79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40223
25022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.4022325022
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.3295825156
Short name T391
Test name
Test status
Simulation time 1015149996 ps
CPU time 37.03 seconds
Started Apr 23 03:07:10 PM PDT 24
Finished Apr 23 03:07:48 PM PDT 24
Peak memory 255172 kb
Host smart-36386203-b2c7-406c-905b-b32eb67e24e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32958
25156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.3295825156
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.3517306131
Short name T519
Test name
Test status
Simulation time 217861251919 ps
CPU time 1524.97 seconds
Started Apr 23 03:07:14 PM PDT 24
Finished Apr 23 03:32:39 PM PDT 24
Peak memory 267088 kb
Host smart-9b593e51-56b8-431c-8daa-ed268d895a95
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517306131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.3517306131
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.3680464997
Short name T619
Test name
Test status
Simulation time 2992761748 ps
CPU time 17.37 seconds
Started Apr 23 03:07:08 PM PDT 24
Finished Apr 23 03:07:25 PM PDT 24
Peak memory 248652 kb
Host smart-c3c5faca-a372-4325-bae7-918b94892282
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36804
64997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.3680464997
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.2892993767
Short name T421
Test name
Test status
Simulation time 348117837 ps
CPU time 19.99 seconds
Started Apr 23 03:07:09 PM PDT 24
Finished Apr 23 03:07:29 PM PDT 24
Peak memory 255208 kb
Host smart-f595a0d5-f9b1-493f-a13e-2dc7e832a840
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28929
93767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.2892993767
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.107199526
Short name T237
Test name
Test status
Simulation time 633756301 ps
CPU time 7.03 seconds
Started Apr 23 03:07:11 PM PDT 24
Finished Apr 23 03:07:18 PM PDT 24
Peak memory 251168 kb
Host smart-0a3d88c4-ec1f-47ba-a95c-f0ab0e8b81e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10719
9526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.107199526
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.1762039245
Short name T627
Test name
Test status
Simulation time 919365425 ps
CPU time 11.23 seconds
Started Apr 23 03:07:09 PM PDT 24
Finished Apr 23 03:07:20 PM PDT 24
Peak memory 248636 kb
Host smart-7cd54b7f-cc3a-4e53-aeea-2c56170873fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17620
39245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.1762039245
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.3484773459
Short name T553
Test name
Test status
Simulation time 249435775 ps
CPU time 17.96 seconds
Started Apr 23 03:07:20 PM PDT 24
Finished Apr 23 03:07:38 PM PDT 24
Peak memory 248600 kb
Host smart-1ace842b-00c8-4319-b85f-b7cbf5f9f5c0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484773459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.3484773459
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.2664286213
Short name T636
Test name
Test status
Simulation time 15561565294 ps
CPU time 1762.16 seconds
Started Apr 23 03:07:18 PM PDT 24
Finished Apr 23 03:36:41 PM PDT 24
Peak memory 289732 kb
Host smart-39ebdcdf-f2fa-476c-adc9-71063e45ffce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664286213 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.2664286213
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.585700171
Short name T494
Test name
Test status
Simulation time 98484042231 ps
CPU time 1593.42 seconds
Started Apr 23 03:07:28 PM PDT 24
Finished Apr 23 03:34:02 PM PDT 24
Peak memory 272928 kb
Host smart-a8c2ac8c-e823-4555-91a8-8c81e240547d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585700171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.585700171
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.3389503224
Short name T568
Test name
Test status
Simulation time 43342311892 ps
CPU time 398.42 seconds
Started Apr 23 03:07:25 PM PDT 24
Finished Apr 23 03:14:04 PM PDT 24
Peak memory 250728 kb
Host smart-638122c6-216f-4bb4-9b8d-0a455742c95f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33895
03224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.3389503224
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.786664941
Short name T223
Test name
Test status
Simulation time 309171692 ps
CPU time 29.64 seconds
Started Apr 23 03:07:27 PM PDT 24
Finished Apr 23 03:07:57 PM PDT 24
Peak memory 255156 kb
Host smart-83d2ed6b-d212-498e-ab8a-26dd9c011206
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78666
4941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.786664941
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.2157519812
Short name T318
Test name
Test status
Simulation time 98796145419 ps
CPU time 1377.87 seconds
Started Apr 23 03:07:32 PM PDT 24
Finished Apr 23 03:30:31 PM PDT 24
Peak memory 282824 kb
Host smart-a4faa1bd-2125-4e08-857d-ccbf62398a30
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157519812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.2157519812
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.2458201387
Short name T392
Test name
Test status
Simulation time 8092386076 ps
CPU time 815.22 seconds
Started Apr 23 03:07:37 PM PDT 24
Finished Apr 23 03:21:13 PM PDT 24
Peak memory 273200 kb
Host smart-242a38a3-1fd4-4369-b8cc-6096510068f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458201387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.2458201387
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.1930796326
Short name T297
Test name
Test status
Simulation time 5554585742 ps
CPU time 233.58 seconds
Started Apr 23 03:07:29 PM PDT 24
Finished Apr 23 03:11:23 PM PDT 24
Peak memory 247624 kb
Host smart-15510eb6-2f01-4177-90a3-118510301975
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930796326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.1930796326
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.2922330018
Short name T230
Test name
Test status
Simulation time 271187988 ps
CPU time 14.42 seconds
Started Apr 23 03:07:25 PM PDT 24
Finished Apr 23 03:07:40 PM PDT 24
Peak memory 248620 kb
Host smart-54670a50-64eb-4b9d-b93d-1a27cc0f19da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29223
30018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.2922330018
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.2318255874
Short name T590
Test name
Test status
Simulation time 4082817928 ps
CPU time 66.62 seconds
Started Apr 23 03:07:24 PM PDT 24
Finished Apr 23 03:08:31 PM PDT 24
Peak memory 254696 kb
Host smart-31826873-14f5-498c-8c7a-2867227fcfd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23182
55874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.2318255874
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.1818206576
Short name T694
Test name
Test status
Simulation time 1917075448 ps
CPU time 32.74 seconds
Started Apr 23 03:07:29 PM PDT 24
Finished Apr 23 03:08:02 PM PDT 24
Peak memory 248624 kb
Host smart-c2f43640-a93c-4450-aca9-246844f33e08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18182
06576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.1818206576
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.1401029256
Short name T93
Test name
Test status
Simulation time 1092177985 ps
CPU time 25.09 seconds
Started Apr 23 03:07:23 PM PDT 24
Finished Apr 23 03:07:48 PM PDT 24
Peak memory 248628 kb
Host smart-4f69a8aa-de79-4444-b668-c22de559de38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14010
29256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.1401029256
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.2095717824
Short name T384
Test name
Test status
Simulation time 62273796684 ps
CPU time 774.11 seconds
Started Apr 23 03:07:42 PM PDT 24
Finished Apr 23 03:20:37 PM PDT 24
Peak memory 273216 kb
Host smart-4becb4e5-3cd1-4166-88a2-c04a15a3871e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095717824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.2095717824
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.3604930987
Short name T505
Test name
Test status
Simulation time 5085606216 ps
CPU time 102.99 seconds
Started Apr 23 03:07:38 PM PDT 24
Finished Apr 23 03:09:21 PM PDT 24
Peak memory 256304 kb
Host smart-5d72f058-4d14-4b16-b54f-f321ce3a473d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36049
30987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.3604930987
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.4035936616
Short name T95
Test name
Test status
Simulation time 4059738242 ps
CPU time 70.71 seconds
Started Apr 23 03:07:38 PM PDT 24
Finished Apr 23 03:08:49 PM PDT 24
Peak memory 255124 kb
Host smart-f4b4b0ea-ac1e-4bbd-9727-52e5b5c9a580
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40359
36616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.4035936616
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.3662349953
Short name T621
Test name
Test status
Simulation time 46606748408 ps
CPU time 2517.19 seconds
Started Apr 23 03:07:46 PM PDT 24
Finished Apr 23 03:49:44 PM PDT 24
Peak memory 281352 kb
Host smart-f9f98d98-77d0-4f98-9b06-fd9af7068058
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662349953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.3662349953
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.1841250585
Short name T288
Test name
Test status
Simulation time 13387876848 ps
CPU time 559.16 seconds
Started Apr 23 03:07:44 PM PDT 24
Finished Apr 23 03:17:04 PM PDT 24
Peak memory 247524 kb
Host smart-7c2d7ad1-0969-4f51-a31f-bb586df25409
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841250585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.1841250585
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.1776919755
Short name T423
Test name
Test status
Simulation time 464913319 ps
CPU time 38.02 seconds
Started Apr 23 03:07:36 PM PDT 24
Finished Apr 23 03:08:14 PM PDT 24
Peak memory 248616 kb
Host smart-be2a3020-3f71-4a8b-9e4a-c7ee93268a84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17769
19755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.1776919755
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.1748672937
Short name T18
Test name
Test status
Simulation time 351175423 ps
CPU time 24.7 seconds
Started Apr 23 03:07:42 PM PDT 24
Finished Apr 23 03:08:06 PM PDT 24
Peak memory 247028 kb
Host smart-56d5b7bc-3877-41e2-afb2-545920991c9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17486
72937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.1748672937
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.2830442988
Short name T689
Test name
Test status
Simulation time 9973934902 ps
CPU time 48.62 seconds
Started Apr 23 03:07:40 PM PDT 24
Finished Apr 23 03:08:28 PM PDT 24
Peak memory 254768 kb
Host smart-99e46785-c2b3-4635-9d3e-e363b466df49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28304
42988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.2830442988
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.233291660
Short name T562
Test name
Test status
Simulation time 576943216 ps
CPU time 36.34 seconds
Started Apr 23 03:07:37 PM PDT 24
Finished Apr 23 03:08:13 PM PDT 24
Peak memory 248568 kb
Host smart-2897cccd-d037-4028-aaef-eb75360e1cde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23329
1660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.233291660
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.592033427
Short name T116
Test name
Test status
Simulation time 35380980839 ps
CPU time 2215.39 seconds
Started Apr 23 03:07:52 PM PDT 24
Finished Apr 23 03:44:48 PM PDT 24
Peak memory 288868 kb
Host smart-7aadca27-3e0a-4c8c-a705-ebe1e6e58a0e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592033427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.592033427
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.3327390741
Short name T401
Test name
Test status
Simulation time 14990641515 ps
CPU time 208.55 seconds
Started Apr 23 03:07:50 PM PDT 24
Finished Apr 23 03:11:18 PM PDT 24
Peak memory 256344 kb
Host smart-87f4bc65-d4fd-404d-ae03-80d786837778
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33273
90741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.3327390741
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.933881793
Short name T651
Test name
Test status
Simulation time 3200099960 ps
CPU time 30.46 seconds
Started Apr 23 03:07:49 PM PDT 24
Finished Apr 23 03:08:19 PM PDT 24
Peak memory 254700 kb
Host smart-aa180881-7e5d-4794-8cc8-aac5eebd6af3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93388
1793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.933881793
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.1508158032
Short name T323
Test name
Test status
Simulation time 49989833755 ps
CPU time 2750.49 seconds
Started Apr 23 03:07:56 PM PDT 24
Finished Apr 23 03:53:47 PM PDT 24
Peak memory 283084 kb
Host smart-227e92db-08cd-40be-8c84-008813d77d87
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508158032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.1508158032
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.3650162650
Short name T561
Test name
Test status
Simulation time 11539256159 ps
CPU time 1061.18 seconds
Started Apr 23 03:07:55 PM PDT 24
Finished Apr 23 03:25:37 PM PDT 24
Peak memory 283192 kb
Host smart-5f7ca4ab-53a9-4094-860d-3ba9cb9f4040
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650162650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.3650162650
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.1565239223
Short name T291
Test name
Test status
Simulation time 38436500617 ps
CPU time 142.59 seconds
Started Apr 23 03:07:52 PM PDT 24
Finished Apr 23 03:10:14 PM PDT 24
Peak memory 247544 kb
Host smart-6c9aaf7a-9e18-4a1a-8b02-324afc47ec1e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565239223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.1565239223
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.2622171736
Short name T441
Test name
Test status
Simulation time 344261471 ps
CPU time 8.84 seconds
Started Apr 23 03:07:47 PM PDT 24
Finished Apr 23 03:07:56 PM PDT 24
Peak memory 248608 kb
Host smart-fdc564d2-595c-45b1-a8fe-f196aab7b844
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26221
71736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.2622171736
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.1576984149
Short name T21
Test name
Test status
Simulation time 347490880 ps
CPU time 32.31 seconds
Started Apr 23 03:07:46 PM PDT 24
Finished Apr 23 03:08:19 PM PDT 24
Peak memory 255612 kb
Host smart-e8d3c6df-cf27-45f0-9a22-9ac2c69787f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15769
84149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.1576984149
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.1379752317
Short name T247
Test name
Test status
Simulation time 142830118 ps
CPU time 18.32 seconds
Started Apr 23 03:07:50 PM PDT 24
Finished Apr 23 03:08:08 PM PDT 24
Peak memory 254192 kb
Host smart-007e5dbf-a4e1-42d1-b878-01399017780a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13797
52317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.1379752317
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.1553654742
Short name T355
Test name
Test status
Simulation time 859566948 ps
CPU time 54.8 seconds
Started Apr 23 03:07:46 PM PDT 24
Finished Apr 23 03:08:42 PM PDT 24
Peak memory 248672 kb
Host smart-eafd3984-a318-4767-a6b6-eefd73486b31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15536
54742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.1553654742
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.4262396335
Short name T49
Test name
Test status
Simulation time 48956139140 ps
CPU time 2996.49 seconds
Started Apr 23 03:07:56 PM PDT 24
Finished Apr 23 03:57:53 PM PDT 24
Peak memory 305716 kb
Host smart-abc8a3e7-5dfa-48b0-a50c-584b4f9d4900
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262396335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.4262396335
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.1771922049
Short name T72
Test name
Test status
Simulation time 142323395588 ps
CPU time 3097.36 seconds
Started Apr 23 03:07:59 PM PDT 24
Finished Apr 23 03:59:37 PM PDT 24
Peak memory 289704 kb
Host smart-c29fb97f-9d1f-4770-82d5-6ef21a209690
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771922049 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.1771922049
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.1668716379
Short name T573
Test name
Test status
Simulation time 103422368520 ps
CPU time 2993.54 seconds
Started Apr 23 03:08:03 PM PDT 24
Finished Apr 23 03:57:57 PM PDT 24
Peak memory 288908 kb
Host smart-a13c9e79-4868-4513-a3a6-17ec00603d6e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668716379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.1668716379
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.2350918148
Short name T362
Test name
Test status
Simulation time 2909062651 ps
CPU time 203.56 seconds
Started Apr 23 03:08:03 PM PDT 24
Finished Apr 23 03:11:27 PM PDT 24
Peak memory 249672 kb
Host smart-4b2bc1d5-d6d2-4937-8279-365e3cdfe34d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23509
18148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.2350918148
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.3938274493
Short name T540
Test name
Test status
Simulation time 3273530817 ps
CPU time 54.71 seconds
Started Apr 23 03:08:03 PM PDT 24
Finished Apr 23 03:08:58 PM PDT 24
Peak memory 248648 kb
Host smart-af0535ff-c3a2-4021-b4cc-8ffea29b550b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39382
74493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.3938274493
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.261981526
Short name T368
Test name
Test status
Simulation time 2650020698 ps
CPU time 116.88 seconds
Started Apr 23 03:08:03 PM PDT 24
Finished Apr 23 03:10:01 PM PDT 24
Peak memory 254124 kb
Host smart-171368da-ebfd-4db3-8dde-d0d45077a625
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261981526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.261981526
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.950546513
Short name T601
Test name
Test status
Simulation time 400753751 ps
CPU time 28.35 seconds
Started Apr 23 03:07:59 PM PDT 24
Finished Apr 23 03:08:28 PM PDT 24
Peak memory 248648 kb
Host smart-db3fba3a-c1b5-452f-bf83-b3268dc95eb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95054
6513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.950546513
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.1157259665
Short name T563
Test name
Test status
Simulation time 4137848067 ps
CPU time 52.65 seconds
Started Apr 23 03:08:03 PM PDT 24
Finished Apr 23 03:08:56 PM PDT 24
Peak memory 248416 kb
Host smart-49e82c18-ce99-4a69-ad30-d0495f4d4d6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11572
59665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.1157259665
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.1236699354
Short name T400
Test name
Test status
Simulation time 222064891 ps
CPU time 23.95 seconds
Started Apr 23 03:08:02 PM PDT 24
Finished Apr 23 03:08:26 PM PDT 24
Peak memory 248624 kb
Host smart-fec6619c-b0ab-406d-8825-eaf4078f506a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12366
99354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.1236699354
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.891464011
Short name T374
Test name
Test status
Simulation time 154014692 ps
CPU time 10.3 seconds
Started Apr 23 03:07:59 PM PDT 24
Finished Apr 23 03:08:10 PM PDT 24
Peak memory 248576 kb
Host smart-0236d58d-2e67-4308-b001-e3f07aacb914
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89146
4011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.891464011
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.1049387491
Short name T687
Test name
Test status
Simulation time 42166611616 ps
CPU time 1831.79 seconds
Started Apr 23 03:08:06 PM PDT 24
Finished Apr 23 03:38:38 PM PDT 24
Peak memory 299044 kb
Host smart-0e44f5a5-c03d-4ba5-ae4d-89d054dc0870
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049387491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.1049387491
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.1876629002
Short name T70
Test name
Test status
Simulation time 45823056275 ps
CPU time 1482.78 seconds
Started Apr 23 03:08:10 PM PDT 24
Finished Apr 23 03:32:53 PM PDT 24
Peak memory 289124 kb
Host smart-8373c5b0-fdd8-4072-b449-c99a83cd3439
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876629002 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.1876629002
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.2529892919
Short name T127
Test name
Test status
Simulation time 62209363178 ps
CPU time 1556.97 seconds
Started Apr 23 03:08:12 PM PDT 24
Finished Apr 23 03:34:10 PM PDT 24
Peak memory 289052 kb
Host smart-ee6b5c78-d5f4-4f5e-91e1-127b12bc02f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529892919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.2529892919
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.552149167
Short name T474
Test name
Test status
Simulation time 1632069313 ps
CPU time 143.49 seconds
Started Apr 23 03:08:13 PM PDT 24
Finished Apr 23 03:10:37 PM PDT 24
Peak memory 255980 kb
Host smart-fd2f2d25-c269-420d-9421-19dee421c159
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55214
9167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.552149167
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.4150966392
Short name T512
Test name
Test status
Simulation time 954646898 ps
CPU time 18.24 seconds
Started Apr 23 03:08:13 PM PDT 24
Finished Apr 23 03:08:31 PM PDT 24
Peak memory 253964 kb
Host smart-07167c2a-6ec1-40e9-9b73-f7aeeecc595b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41509
66392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.4150966392
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.2443374337
Short name T314
Test name
Test status
Simulation time 124419249762 ps
CPU time 1703.31 seconds
Started Apr 23 03:08:19 PM PDT 24
Finished Apr 23 03:36:43 PM PDT 24
Peak memory 270352 kb
Host smart-53aada7e-2852-442c-9c26-7b7a92b11b31
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443374337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.2443374337
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.2178586840
Short name T364
Test name
Test status
Simulation time 143021375477 ps
CPU time 2136.34 seconds
Started Apr 23 03:08:19 PM PDT 24
Finished Apr 23 03:43:56 PM PDT 24
Peak memory 273268 kb
Host smart-a21b58a3-055d-4cad-a3de-d77da087abf5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178586840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.2178586840
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.3791080403
Short name T294
Test name
Test status
Simulation time 41854907828 ps
CPU time 452.33 seconds
Started Apr 23 03:08:15 PM PDT 24
Finished Apr 23 03:15:48 PM PDT 24
Peak memory 247268 kb
Host smart-ea27796f-cafe-4023-a408-37dd8624bb32
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791080403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.3791080403
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.2263427956
Short name T5
Test name
Test status
Simulation time 3339523458 ps
CPU time 57.65 seconds
Started Apr 23 03:08:13 PM PDT 24
Finished Apr 23 03:09:11 PM PDT 24
Peak memory 248904 kb
Host smart-716dfb51-1980-49de-ac3e-178494b679fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22634
27956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.2263427956
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.2241606592
Short name T690
Test name
Test status
Simulation time 330080457 ps
CPU time 5.99 seconds
Started Apr 23 03:08:13 PM PDT 24
Finished Apr 23 03:08:19 PM PDT 24
Peak memory 238572 kb
Host smart-61f5e834-2c33-4dd6-a76a-37c2efa559b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22416
06592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.2241606592
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.151791721
Short name T253
Test name
Test status
Simulation time 146801877 ps
CPU time 18.61 seconds
Started Apr 23 03:08:12 PM PDT 24
Finished Apr 23 03:08:31 PM PDT 24
Peak memory 255048 kb
Host smart-9ef3ae54-7318-4cf2-80f2-8113348b719c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15179
1721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.151791721
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.2522542522
Short name T431
Test name
Test status
Simulation time 775921565 ps
CPU time 53.11 seconds
Started Apr 23 03:08:09 PM PDT 24
Finished Apr 23 03:09:03 PM PDT 24
Peak memory 248580 kb
Host smart-8efae904-af90-4061-afe7-8869016fcd66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25225
42522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.2522542522
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.710548176
Short name T658
Test name
Test status
Simulation time 10374074842 ps
CPU time 902.58 seconds
Started Apr 23 03:08:31 PM PDT 24
Finished Apr 23 03:23:34 PM PDT 24
Peak memory 268100 kb
Host smart-162ad1be-5ee9-4a1a-bc8a-748b6c107e5f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710548176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.710548176
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.4083500165
Short name T48
Test name
Test status
Simulation time 3411193191 ps
CPU time 190.93 seconds
Started Apr 23 03:08:30 PM PDT 24
Finished Apr 23 03:11:41 PM PDT 24
Peak memory 256564 kb
Host smart-04115bfa-6b30-48ea-b6f6-1de382f8058b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40835
00165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.4083500165
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.249115007
Short name T28
Test name
Test status
Simulation time 458018090 ps
CPU time 27.61 seconds
Started Apr 23 03:08:26 PM PDT 24
Finished Apr 23 03:08:53 PM PDT 24
Peak memory 253868 kb
Host smart-5d3cbd5c-a1e9-423a-a2bb-219257a9f32f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24911
5007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.249115007
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.3928954001
Short name T463
Test name
Test status
Simulation time 191103049433 ps
CPU time 1273.82 seconds
Started Apr 23 03:08:32 PM PDT 24
Finished Apr 23 03:29:47 PM PDT 24
Peak memory 288800 kb
Host smart-59198021-55be-4c7a-bd67-eacb69207d77
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928954001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.3928954001
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.3696250344
Short name T639
Test name
Test status
Simulation time 195063790933 ps
CPU time 482.33 seconds
Started Apr 23 03:08:30 PM PDT 24
Finished Apr 23 03:16:33 PM PDT 24
Peak memory 247252 kb
Host smart-862ca484-0c86-4cd9-bc62-191313748fd4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696250344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.3696250344
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.1301145133
Short name T472
Test name
Test status
Simulation time 2937782682 ps
CPU time 45.34 seconds
Started Apr 23 03:08:23 PM PDT 24
Finished Apr 23 03:09:08 PM PDT 24
Peak memory 248688 kb
Host smart-75f17975-3ab8-4244-b998-e475e6dd6a3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13011
45133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.1301145133
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.2121985431
Short name T24
Test name
Test status
Simulation time 2816976337 ps
CPU time 22.11 seconds
Started Apr 23 03:08:22 PM PDT 24
Finished Apr 23 03:08:45 PM PDT 24
Peak memory 253692 kb
Host smart-6e78f045-1869-412a-9903-51c2e167df57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21219
85431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.2121985431
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.843231863
Short name T629
Test name
Test status
Simulation time 1848063216 ps
CPU time 34 seconds
Started Apr 23 03:08:28 PM PDT 24
Finished Apr 23 03:09:02 PM PDT 24
Peak memory 255472 kb
Host smart-bdac4e5e-5c5c-41fb-8994-805867fcf783
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84323
1863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.843231863
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.99887713
Short name T556
Test name
Test status
Simulation time 3658204848 ps
CPU time 23.22 seconds
Started Apr 23 03:08:19 PM PDT 24
Finished Apr 23 03:08:42 PM PDT 24
Peak memory 248652 kb
Host smart-86cb737c-1171-4ef6-aea4-89ac40a4bfd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99887
713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.99887713
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.422466733
Short name T438
Test name
Test status
Simulation time 36398212131 ps
CPU time 1767.21 seconds
Started Apr 23 03:08:37 PM PDT 24
Finished Apr 23 03:38:05 PM PDT 24
Peak memory 297964 kb
Host smart-8d5e99a9-8b2d-4a6b-a64e-fa08c2bbc936
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422466733 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.422466733
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.2510698997
Short name T647
Test name
Test status
Simulation time 25658723290 ps
CPU time 1627.5 seconds
Started Apr 23 03:08:44 PM PDT 24
Finished Apr 23 03:35:52 PM PDT 24
Peak memory 273216 kb
Host smart-f45112fb-a1c4-4f9d-b224-1e8b57f341a4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510698997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.2510698997
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.879420420
Short name T370
Test name
Test status
Simulation time 72407540 ps
CPU time 5.98 seconds
Started Apr 23 03:08:46 PM PDT 24
Finished Apr 23 03:08:52 PM PDT 24
Peak memory 238572 kb
Host smart-c95df7d7-781a-4847-bf56-010a37f8e5a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87942
0420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.879420420
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.1355144446
Short name T20
Test name
Test status
Simulation time 918449468 ps
CPU time 18.72 seconds
Started Apr 23 03:08:44 PM PDT 24
Finished Apr 23 03:09:03 PM PDT 24
Peak memory 254504 kb
Host smart-42b0cdb9-a91a-432c-9b1d-ecfec3d47ff5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13551
44446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.1355144446
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.510494041
Short name T281
Test name
Test status
Simulation time 50524735771 ps
CPU time 953.25 seconds
Started Apr 23 03:08:47 PM PDT 24
Finished Apr 23 03:24:41 PM PDT 24
Peak memory 268160 kb
Host smart-631ee398-af35-4e38-a62a-f6f8ce68c987
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510494041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.510494041
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.1511174516
Short name T500
Test name
Test status
Simulation time 76618492662 ps
CPU time 1148.7 seconds
Started Apr 23 03:08:45 PM PDT 24
Finished Apr 23 03:27:54 PM PDT 24
Peak memory 272104 kb
Host smart-3cc92fc1-5265-4382-bb10-d9a1e2887190
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511174516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.1511174516
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.3472485127
Short name T669
Test name
Test status
Simulation time 52419517252 ps
CPU time 478.45 seconds
Started Apr 23 03:08:47 PM PDT 24
Finished Apr 23 03:16:45 PM PDT 24
Peak memory 247648 kb
Host smart-6659c860-c418-4e37-8959-74d1d3c4fe48
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472485127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.3472485127
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.1634597950
Short name T103
Test name
Test status
Simulation time 300991723 ps
CPU time 33.49 seconds
Started Apr 23 03:08:39 PM PDT 24
Finished Apr 23 03:09:13 PM PDT 24
Peak memory 248632 kb
Host smart-bb67fa39-a46b-4862-9c54-7ff04e2084e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16345
97950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.1634597950
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.3766267029
Short name T8
Test name
Test status
Simulation time 1396572181 ps
CPU time 40.91 seconds
Started Apr 23 03:08:41 PM PDT 24
Finished Apr 23 03:09:22 PM PDT 24
Peak memory 255120 kb
Host smart-c6fd9334-d9a0-4c4e-972a-e00ae69678ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37662
67029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.3766267029
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.1538972133
Short name T668
Test name
Test status
Simulation time 2971978905 ps
CPU time 45.81 seconds
Started Apr 23 03:08:44 PM PDT 24
Finished Apr 23 03:09:30 PM PDT 24
Peak memory 255680 kb
Host smart-3116869a-e20a-4afb-929f-82f501c80585
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15389
72133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.1538972133
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.1335979640
Short name T228
Test name
Test status
Simulation time 297123998 ps
CPU time 18.3 seconds
Started Apr 23 03:08:41 PM PDT 24
Finished Apr 23 03:08:59 PM PDT 24
Peak memory 248656 kb
Host smart-e6f0650d-485e-4cfd-8bc6-3d982328bc3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13359
79640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.1335979640
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.1648610015
Short name T119
Test name
Test status
Simulation time 1532397318 ps
CPU time 165.1 seconds
Started Apr 23 03:08:48 PM PDT 24
Finished Apr 23 03:11:33 PM PDT 24
Peak memory 256756 kb
Host smart-27e290f7-4054-463a-a78a-a8ba9a257ab7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648610015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.1648610015
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.3742878466
Short name T262
Test name
Test status
Simulation time 24184375593 ps
CPU time 671.92 seconds
Started Apr 23 03:09:01 PM PDT 24
Finished Apr 23 03:20:13 PM PDT 24
Peak memory 265064 kb
Host smart-e138f30b-de79-4b07-a3fd-066ed37c7ce0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742878466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.3742878466
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.3896866814
Short name T535
Test name
Test status
Simulation time 531009078 ps
CPU time 33.43 seconds
Started Apr 23 03:08:56 PM PDT 24
Finished Apr 23 03:09:30 PM PDT 24
Peak memory 255360 kb
Host smart-db74e107-e256-4586-a59f-e7d8c05caa06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38968
66814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.3896866814
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.2397062672
Short name T31
Test name
Test status
Simulation time 900273735 ps
CPU time 19.09 seconds
Started Apr 23 03:08:51 PM PDT 24
Finished Apr 23 03:09:11 PM PDT 24
Peak memory 247216 kb
Host smart-c28cc5aa-28f3-4ba9-bb24-5eb4860a5711
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23970
62672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.2397062672
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.3433956863
Short name T543
Test name
Test status
Simulation time 58967003423 ps
CPU time 1250.77 seconds
Started Apr 23 03:09:01 PM PDT 24
Finished Apr 23 03:29:52 PM PDT 24
Peak memory 288708 kb
Host smart-9dbe4e29-39a9-41ce-9104-915f16db8112
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433956863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.3433956863
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.77271195
Short name T377
Test name
Test status
Simulation time 8310045098 ps
CPU time 757.31 seconds
Started Apr 23 03:09:02 PM PDT 24
Finished Apr 23 03:21:40 PM PDT 24
Peak memory 265020 kb
Host smart-223919f4-643e-4041-81b0-67ced1158567
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77271195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.77271195
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.4236749029
Short name T61
Test name
Test status
Simulation time 110241381861 ps
CPU time 229.48 seconds
Started Apr 23 03:09:01 PM PDT 24
Finished Apr 23 03:12:51 PM PDT 24
Peak memory 247380 kb
Host smart-761c3100-1ad0-4050-b8e2-d303766a8a92
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236749029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.4236749029
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.414332041
Short name T264
Test name
Test status
Simulation time 1303570253 ps
CPU time 21.08 seconds
Started Apr 23 03:08:50 PM PDT 24
Finished Apr 23 03:09:12 PM PDT 24
Peak memory 248604 kb
Host smart-27e14f5c-938e-406c-8245-8b96f1fb27c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41433
2041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.414332041
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.1032096893
Short name T275
Test name
Test status
Simulation time 10900858390 ps
CPU time 33.62 seconds
Started Apr 23 03:08:50 PM PDT 24
Finished Apr 23 03:09:24 PM PDT 24
Peak memory 247572 kb
Host smart-7031e8f1-573f-438c-a392-c2535d4e6eaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10320
96893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.1032096893
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.1840244689
Short name T252
Test name
Test status
Simulation time 553969906 ps
CPU time 33.64 seconds
Started Apr 23 03:08:59 PM PDT 24
Finished Apr 23 03:09:33 PM PDT 24
Peak memory 254424 kb
Host smart-b50825bb-0404-48ba-8d95-b132d189bd7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18402
44689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.1840244689
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.2966240547
Short name T118
Test name
Test status
Simulation time 823194105 ps
CPU time 43.99 seconds
Started Apr 23 03:08:49 PM PDT 24
Finished Apr 23 03:09:33 PM PDT 24
Peak memory 256836 kb
Host smart-7f44f0bd-86b7-43eb-bd71-7533833d1232
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29662
40547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.2966240547
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.3926773440
Short name T469
Test name
Test status
Simulation time 21273585980 ps
CPU time 1744.14 seconds
Started Apr 23 03:09:02 PM PDT 24
Finished Apr 23 03:38:06 PM PDT 24
Peak memory 297372 kb
Host smart-7e9b70fc-e0a0-4b02-96a3-a8e37b675b31
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926773440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.3926773440
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.1128848364
Short name T86
Test name
Test status
Simulation time 151292690 ps
CPU time 3.39 seconds
Started Apr 23 03:03:04 PM PDT 24
Finished Apr 23 03:03:08 PM PDT 24
Peak memory 248812 kb
Host smart-0dfb806e-6e6e-4c92-a58d-797e5dc47961
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1128848364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.1128848364
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.1811729397
Short name T633
Test name
Test status
Simulation time 56836592829 ps
CPU time 2045.4 seconds
Started Apr 23 03:03:02 PM PDT 24
Finished Apr 23 03:37:08 PM PDT 24
Peak memory 280956 kb
Host smart-a91254d5-7835-4bcd-b667-019ad34f9f6b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811729397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.1811729397
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.2673772476
Short name T373
Test name
Test status
Simulation time 287386378 ps
CPU time 10.66 seconds
Started Apr 23 03:03:05 PM PDT 24
Finished Apr 23 03:03:16 PM PDT 24
Peak memory 240412 kb
Host smart-587f7da5-cbf4-4957-b965-0fc2fc077e14
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2673772476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.2673772476
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.605512057
Short name T585
Test name
Test status
Simulation time 3473663092 ps
CPU time 97.24 seconds
Started Apr 23 03:03:03 PM PDT 24
Finished Apr 23 03:04:40 PM PDT 24
Peak memory 256696 kb
Host smart-1f456091-dace-4e24-ab44-20f31d613cd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60551
2057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.605512057
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.1027187632
Short name T244
Test name
Test status
Simulation time 1507839433 ps
CPU time 22.92 seconds
Started Apr 23 03:03:02 PM PDT 24
Finished Apr 23 03:03:26 PM PDT 24
Peak memory 254848 kb
Host smart-e86617a2-e298-4915-b260-43b2657f0f34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10271
87632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.1027187632
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.1408985793
Short name T56
Test name
Test status
Simulation time 19891014715 ps
CPU time 1276.63 seconds
Started Apr 23 03:03:03 PM PDT 24
Finished Apr 23 03:24:20 PM PDT 24
Peak memory 267096 kb
Host smart-8d30b696-2eb4-4568-88b1-8426543552be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408985793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.1408985793
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.2659759892
Short name T287
Test name
Test status
Simulation time 6841169042 ps
CPU time 287.15 seconds
Started Apr 23 03:03:02 PM PDT 24
Finished Apr 23 03:07:50 PM PDT 24
Peak memory 247620 kb
Host smart-1ff92f6f-eda8-45f7-a148-e490ef2b94bc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659759892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.2659759892
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.2000233679
Short name T193
Test name
Test status
Simulation time 930947084 ps
CPU time 15.38 seconds
Started Apr 23 03:03:00 PM PDT 24
Finished Apr 23 03:03:15 PM PDT 24
Peak memory 248600 kb
Host smart-6501da86-899a-41b6-b02c-c66e28e5bb2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20002
33679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.2000233679
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.3512391244
Short name T372
Test name
Test status
Simulation time 78557316 ps
CPU time 7.94 seconds
Started Apr 23 03:04:37 PM PDT 24
Finished Apr 23 03:04:45 PM PDT 24
Peak memory 252504 kb
Host smart-a215814b-c1bb-4aca-a08f-aaf8bc78505a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35123
91244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.3512391244
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.3708105726
Short name T496
Test name
Test status
Simulation time 84848018 ps
CPU time 11.95 seconds
Started Apr 23 03:03:01 PM PDT 24
Finished Apr 23 03:03:13 PM PDT 24
Peak memory 246936 kb
Host smart-345df406-d304-4b7a-8304-259e1a477a12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37081
05726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.3708105726
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.701198155
Short name T603
Test name
Test status
Simulation time 718805596 ps
CPU time 47.14 seconds
Started Apr 23 03:03:01 PM PDT 24
Finished Apr 23 03:03:49 PM PDT 24
Peak memory 248648 kb
Host smart-4728782d-7626-4735-afcb-d18bf68c266e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70119
8155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.701198155
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.3998724085
Short name T566
Test name
Test status
Simulation time 20333102663 ps
CPU time 347.78 seconds
Started Apr 23 03:04:16 PM PDT 24
Finished Apr 23 03:10:04 PM PDT 24
Peak memory 255420 kb
Host smart-b2bab6eb-33c8-43ab-9482-ffa398a69bbf
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998724085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.3998724085
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.3728391933
Short name T470
Test name
Test status
Simulation time 21337641669 ps
CPU time 232.76 seconds
Started Apr 23 03:09:14 PM PDT 24
Finished Apr 23 03:13:07 PM PDT 24
Peak memory 256860 kb
Host smart-21181160-b741-4b82-8535-44b1343778d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37283
91933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.3728391933
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.3153704044
Short name T406
Test name
Test status
Simulation time 2251256957 ps
CPU time 34.84 seconds
Started Apr 23 03:09:02 PM PDT 24
Finished Apr 23 03:09:38 PM PDT 24
Peak memory 255248 kb
Host smart-db0bda05-8c1a-4d67-9a0c-9be944344799
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31537
04044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.3153704044
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.1657817881
Short name T282
Test name
Test status
Simulation time 66204474673 ps
CPU time 1833.43 seconds
Started Apr 23 03:09:15 PM PDT 24
Finished Apr 23 03:39:49 PM PDT 24
Peak memory 284500 kb
Host smart-e02f1c0b-3d5e-459a-a5e7-3b8c69f6acff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657817881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.1657817881
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.2621554290
Short name T551
Test name
Test status
Simulation time 16754537189 ps
CPU time 1365.62 seconds
Started Apr 23 03:09:15 PM PDT 24
Finished Apr 23 03:32:01 PM PDT 24
Peak memory 281052 kb
Host smart-be204747-01e8-4a51-a724-d49a7e4009a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621554290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.2621554290
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.1300563126
Short name T303
Test name
Test status
Simulation time 9558788524 ps
CPU time 404.86 seconds
Started Apr 23 03:09:17 PM PDT 24
Finished Apr 23 03:16:02 PM PDT 24
Peak memory 247612 kb
Host smart-1ddfe07c-2c5f-43dd-a164-e2554ccfe81a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300563126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.1300563126
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.337656067
Short name T581
Test name
Test status
Simulation time 289412498 ps
CPU time 18.02 seconds
Started Apr 23 03:09:03 PM PDT 24
Finished Apr 23 03:09:21 PM PDT 24
Peak memory 254856 kb
Host smart-762b86f1-93b0-4e12-8e13-b803a927c1c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33765
6067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.337656067
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.2608078355
Short name T380
Test name
Test status
Simulation time 3846408327 ps
CPU time 31.86 seconds
Started Apr 23 03:09:02 PM PDT 24
Finished Apr 23 03:09:34 PM PDT 24
Peak memory 253588 kb
Host smart-ac4e5335-fe6f-4d98-b1c1-57e967173d8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26080
78355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.2608078355
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.368381711
Short name T495
Test name
Test status
Simulation time 346215322 ps
CPU time 15.24 seconds
Started Apr 23 03:09:15 PM PDT 24
Finished Apr 23 03:09:30 PM PDT 24
Peak memory 253644 kb
Host smart-74f8e151-6cad-4940-98ff-c77a98b4150b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36838
1711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.368381711
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.2634098555
Short name T398
Test name
Test status
Simulation time 42468403 ps
CPU time 6.11 seconds
Started Apr 23 03:09:03 PM PDT 24
Finished Apr 23 03:09:10 PM PDT 24
Peak memory 248736 kb
Host smart-c2b0354e-d32e-42d0-8a2d-3e2b6ad5c82a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26340
98555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.2634098555
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.271800546
Short name T459
Test name
Test status
Simulation time 24921484931 ps
CPU time 3124.77 seconds
Started Apr 23 03:09:15 PM PDT 24
Finished Apr 23 04:01:21 PM PDT 24
Peak memory 322208 kb
Host smart-ba4eba66-b3bd-4aa4-8f28-fa22d46d84d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271800546 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.271800546
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.1232111847
Short name T465
Test name
Test status
Simulation time 15266133073 ps
CPU time 1476.36 seconds
Started Apr 23 03:09:28 PM PDT 24
Finished Apr 23 03:34:05 PM PDT 24
Peak memory 289184 kb
Host smart-d04225d5-f27e-40a9-a5c6-6f9af3cb6e83
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232111847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.1232111847
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.4013057918
Short name T356
Test name
Test status
Simulation time 5137319839 ps
CPU time 115.55 seconds
Started Apr 23 03:09:24 PM PDT 24
Finished Apr 23 03:11:20 PM PDT 24
Peak memory 249484 kb
Host smart-44e0a18b-1906-4624-9346-ce8d1842b84b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40130
57918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.4013057918
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.3611849299
Short name T509
Test name
Test status
Simulation time 410850640 ps
CPU time 24.26 seconds
Started Apr 23 03:09:23 PM PDT 24
Finished Apr 23 03:09:48 PM PDT 24
Peak memory 247280 kb
Host smart-8601909a-2eaf-47a8-8b9e-0e312b903732
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36118
49299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.3611849299
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.1495246544
Short name T227
Test name
Test status
Simulation time 35675890726 ps
CPU time 1943.87 seconds
Started Apr 23 03:09:27 PM PDT 24
Finished Apr 23 03:41:51 PM PDT 24
Peak memory 283336 kb
Host smart-7955e2f4-ee51-43c8-b328-3199be48933f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495246544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.1495246544
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.991985544
Short name T529
Test name
Test status
Simulation time 58417487678 ps
CPU time 3417.38 seconds
Started Apr 23 03:09:27 PM PDT 24
Finished Apr 23 04:06:25 PM PDT 24
Peak memory 289400 kb
Host smart-27c478b6-b0e8-4de8-b2e6-004a5230174e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991985544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.991985544
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.2747080354
Short name T302
Test name
Test status
Simulation time 65756781588 ps
CPU time 171.61 seconds
Started Apr 23 03:09:27 PM PDT 24
Finished Apr 23 03:12:19 PM PDT 24
Peak memory 247468 kb
Host smart-5d961b0d-3ee9-496b-a4ed-4fcbd82c793d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747080354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.2747080354
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.3859928702
Short name T671
Test name
Test status
Simulation time 1045762732 ps
CPU time 34.01 seconds
Started Apr 23 03:09:20 PM PDT 24
Finished Apr 23 03:09:54 PM PDT 24
Peak memory 255596 kb
Host smart-f97069de-2de9-4369-a6a9-5020fff6a098
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38599
28702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.3859928702
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.1992411684
Short name T692
Test name
Test status
Simulation time 395490749 ps
CPU time 40.02 seconds
Started Apr 23 03:09:18 PM PDT 24
Finished Apr 23 03:09:59 PM PDT 24
Peak memory 255252 kb
Host smart-61e2d95b-d24e-4e5d-b9f8-e53143987ee8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19924
11684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.1992411684
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.1812798248
Short name T245
Test name
Test status
Simulation time 1052814266 ps
CPU time 70.05 seconds
Started Apr 23 03:09:22 PM PDT 24
Finished Apr 23 03:10:32 PM PDT 24
Peak memory 255964 kb
Host smart-9b1a0fc4-fc6b-4bbe-90f6-b2a8eba68571
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18127
98248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.1812798248
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.1255327744
Short name T225
Test name
Test status
Simulation time 426848659 ps
CPU time 32.1 seconds
Started Apr 23 03:09:16 PM PDT 24
Finished Apr 23 03:09:48 PM PDT 24
Peak memory 248796 kb
Host smart-60a68214-35ba-4382-8362-1217f0d3a497
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12553
27744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.1255327744
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.1665544817
Short name T33
Test name
Test status
Simulation time 15051104328 ps
CPU time 423.4 seconds
Started Apr 23 03:09:25 PM PDT 24
Finished Apr 23 03:16:28 PM PDT 24
Peak memory 256804 kb
Host smart-62539c92-04cb-4f90-b11e-0c4368a369b4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665544817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.1665544817
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.4009809175
Short name T12
Test name
Test status
Simulation time 119973482506 ps
CPU time 1038 seconds
Started Apr 23 03:09:36 PM PDT 24
Finished Apr 23 03:26:54 PM PDT 24
Peak memory 283696 kb
Host smart-a8c43f2f-bd61-47a2-90b8-4362d133c552
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009809175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.4009809175
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.2240238523
Short name T582
Test name
Test status
Simulation time 3406544714 ps
CPU time 236.05 seconds
Started Apr 23 03:09:36 PM PDT 24
Finished Apr 23 03:13:33 PM PDT 24
Peak memory 256800 kb
Host smart-9b24974e-6448-4732-84d9-67e9c652ce06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22402
38523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.2240238523
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.4142504098
Short name T91
Test name
Test status
Simulation time 914587825 ps
CPU time 17.52 seconds
Started Apr 23 03:09:37 PM PDT 24
Finished Apr 23 03:09:55 PM PDT 24
Peak memory 252640 kb
Host smart-119c7f63-e958-484f-9490-c00d743c05e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41425
04098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.4142504098
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.1187762047
Short name T565
Test name
Test status
Simulation time 61093767551 ps
CPU time 1036.99 seconds
Started Apr 23 03:09:45 PM PDT 24
Finished Apr 23 03:27:03 PM PDT 24
Peak memory 272732 kb
Host smart-3f7b8da4-5a77-479f-a01e-2ca15fe2e97e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187762047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.1187762047
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.1981440141
Short name T357
Test name
Test status
Simulation time 130427118377 ps
CPU time 2210.92 seconds
Started Apr 23 03:09:45 PM PDT 24
Finished Apr 23 03:46:37 PM PDT 24
Peak memory 283412 kb
Host smart-1aa4e01c-14c9-481f-9cba-0a20a0d8f03a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981440141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.1981440141
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.3049280505
Short name T478
Test name
Test status
Simulation time 44338814536 ps
CPU time 518.57 seconds
Started Apr 23 03:09:40 PM PDT 24
Finished Apr 23 03:18:19 PM PDT 24
Peak memory 247656 kb
Host smart-0f3328c5-3a3c-4d8f-a478-f1a17011095f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049280505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.3049280505
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.619224917
Short name T493
Test name
Test status
Simulation time 265861690 ps
CPU time 13.28 seconds
Started Apr 23 03:09:31 PM PDT 24
Finished Apr 23 03:09:45 PM PDT 24
Peak memory 248580 kb
Host smart-41dda341-26a8-4f31-9ac4-294112677835
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61922
4917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.619224917
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.3607567418
Short name T598
Test name
Test status
Simulation time 1694015779 ps
CPU time 30.31 seconds
Started Apr 23 03:09:32 PM PDT 24
Finished Apr 23 03:10:02 PM PDT 24
Peak memory 254568 kb
Host smart-5629880e-9f41-4092-83ff-69f61ee8cc5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36075
67418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.3607567418
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.1095504090
Short name T564
Test name
Test status
Simulation time 1062894264 ps
CPU time 37.56 seconds
Started Apr 23 03:09:37 PM PDT 24
Finished Apr 23 03:10:15 PM PDT 24
Peak memory 254384 kb
Host smart-5d3480b4-a328-472d-b214-d63bf54a3cd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10955
04090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.1095504090
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.4099574382
Short name T532
Test name
Test status
Simulation time 1364533687 ps
CPU time 44.54 seconds
Started Apr 23 03:09:29 PM PDT 24
Finished Apr 23 03:10:14 PM PDT 24
Peak memory 248600 kb
Host smart-c6701e36-0204-46cb-a777-f01d78a45847
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40995
74382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.4099574382
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.1544354375
Short name T37
Test name
Test status
Simulation time 87313842496 ps
CPU time 1127.03 seconds
Started Apr 23 03:09:42 PM PDT 24
Finished Apr 23 03:28:29 PM PDT 24
Peak memory 288904 kb
Host smart-61cbe99e-0839-4218-b006-fdcd4bda2898
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544354375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.1544354375
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.1707264206
Short name T587
Test name
Test status
Simulation time 33435624054 ps
CPU time 532.46 seconds
Started Apr 23 03:09:50 PM PDT 24
Finished Apr 23 03:18:42 PM PDT 24
Peak memory 273236 kb
Host smart-cee83c55-df6e-41cf-ac6a-1e6a317fcd37
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707264206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.1707264206
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.700511875
Short name T349
Test name
Test status
Simulation time 2425328085 ps
CPU time 121.56 seconds
Started Apr 23 03:09:46 PM PDT 24
Finished Apr 23 03:11:48 PM PDT 24
Peak memory 249700 kb
Host smart-5c91346d-4686-4a97-8b79-3b0cf54fd4b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70051
1875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.700511875
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.3178318212
Short name T414
Test name
Test status
Simulation time 2058843225 ps
CPU time 59.77 seconds
Started Apr 23 03:09:47 PM PDT 24
Finished Apr 23 03:10:47 PM PDT 24
Peak memory 256056 kb
Host smart-e4df88b6-cafc-4b0f-8a61-69379080b507
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31783
18212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.3178318212
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.2550515536
Short name T595
Test name
Test status
Simulation time 36958751005 ps
CPU time 1084.67 seconds
Started Apr 23 03:09:55 PM PDT 24
Finished Apr 23 03:28:00 PM PDT 24
Peak memory 288276 kb
Host smart-2968c261-e8ac-4f4b-908a-611688dac7f9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550515536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.2550515536
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.890398534
Short name T263
Test name
Test status
Simulation time 181754450 ps
CPU time 9.68 seconds
Started Apr 23 03:09:43 PM PDT 24
Finished Apr 23 03:09:53 PM PDT 24
Peak memory 248732 kb
Host smart-6830cb01-b01f-416c-a343-fb3df02461f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89039
8534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.890398534
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.2504976010
Short name T683
Test name
Test status
Simulation time 1874698457 ps
CPU time 24.77 seconds
Started Apr 23 03:09:45 PM PDT 24
Finished Apr 23 03:10:10 PM PDT 24
Peak memory 248508 kb
Host smart-28c4e358-1a9a-414d-85d1-1067546ba018
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25049
76010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.2504976010
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.1034626783
Short name T570
Test name
Test status
Simulation time 71860145 ps
CPU time 5.82 seconds
Started Apr 23 03:09:49 PM PDT 24
Finished Apr 23 03:09:56 PM PDT 24
Peak memory 238840 kb
Host smart-bd6553ce-a2af-47f1-a580-21b7dbb8aaa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10346
26783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.1034626783
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.3951905902
Short name T361
Test name
Test status
Simulation time 343144216 ps
CPU time 9.68 seconds
Started Apr 23 03:09:42 PM PDT 24
Finished Apr 23 03:09:52 PM PDT 24
Peak memory 248604 kb
Host smart-251fee14-ea12-47ee-b67b-72d18f4f7233
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39519
05902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.3951905902
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.2825197956
Short name T652
Test name
Test status
Simulation time 19602452791 ps
CPU time 790.16 seconds
Started Apr 23 03:10:03 PM PDT 24
Finished Apr 23 03:23:14 PM PDT 24
Peak memory 265004 kb
Host smart-8001d5d7-17fb-4b5b-a332-8ca7e2bd4505
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825197956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.2825197956
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.1378462683
Short name T453
Test name
Test status
Simulation time 4678551119 ps
CPU time 153.31 seconds
Started Apr 23 03:10:04 PM PDT 24
Finished Apr 23 03:12:38 PM PDT 24
Peak memory 256488 kb
Host smart-2009c030-38e3-4a6b-8356-a329638eb154
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13784
62683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.1378462683
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.95948061
Short name T195
Test name
Test status
Simulation time 415667088 ps
CPU time 23.34 seconds
Started Apr 23 03:10:03 PM PDT 24
Finished Apr 23 03:10:27 PM PDT 24
Peak memory 247436 kb
Host smart-f1e1012e-2c1e-4dbf-a289-f3b2fa315b34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95948
061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.95948061
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.3732754090
Short name T473
Test name
Test status
Simulation time 42686150187 ps
CPU time 1321.9 seconds
Started Apr 23 03:10:07 PM PDT 24
Finished Apr 23 03:32:09 PM PDT 24
Peak memory 282984 kb
Host smart-8908000b-92fc-4b4c-a297-f1fc579d6604
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732754090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.3732754090
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.2333736670
Short name T23
Test name
Test status
Simulation time 58781316233 ps
CPU time 1770.21 seconds
Started Apr 23 03:10:05 PM PDT 24
Finished Apr 23 03:39:36 PM PDT 24
Peak memory 270380 kb
Host smart-f5f88a52-fbb5-48ab-9ed1-128a36751ac8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333736670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.2333736670
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.1644702599
Short name T640
Test name
Test status
Simulation time 14343369195 ps
CPU time 543.24 seconds
Started Apr 23 03:10:06 PM PDT 24
Finished Apr 23 03:19:09 PM PDT 24
Peak memory 247344 kb
Host smart-eef25eb3-9bc9-4b84-8063-0bd5b374f7f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644702599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.1644702599
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.4154059457
Short name T550
Test name
Test status
Simulation time 1316982571 ps
CPU time 43.35 seconds
Started Apr 23 03:09:56 PM PDT 24
Finished Apr 23 03:10:39 PM PDT 24
Peak memory 255436 kb
Host smart-187fd9bc-eeb0-4e63-b245-b8e332afb463
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41540
59457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.4154059457
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.1361735699
Short name T615
Test name
Test status
Simulation time 4195346782 ps
CPU time 68.64 seconds
Started Apr 23 03:09:56 PM PDT 24
Finished Apr 23 03:11:05 PM PDT 24
Peak memory 256120 kb
Host smart-8f092f74-2f53-4aff-9d74-365d33561d90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13617
35699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.1361735699
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.3356884002
Short name T623
Test name
Test status
Simulation time 636758336 ps
CPU time 35.45 seconds
Started Apr 23 03:09:55 PM PDT 24
Finished Apr 23 03:10:31 PM PDT 24
Peak memory 248880 kb
Host smart-955d9daa-14fd-4916-8c65-41e4b3f0bc05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33568
84002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.3356884002
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.1095180495
Short name T38
Test name
Test status
Simulation time 9413667860 ps
CPU time 71.25 seconds
Started Apr 23 03:10:10 PM PDT 24
Finished Apr 23 03:11:22 PM PDT 24
Peak memory 256824 kb
Host smart-c90168b5-bb2e-4fd5-8a4c-e136b88edbd6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095180495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.1095180495
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.283956550
Short name T490
Test name
Test status
Simulation time 134182122678 ps
CPU time 1359.52 seconds
Started Apr 23 03:10:09 PM PDT 24
Finished Apr 23 03:32:49 PM PDT 24
Peak memory 288788 kb
Host smart-a121ea85-2bb4-4bd4-8d2a-f27fc415bd0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283956550 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.283956550
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.531279868
Short name T511
Test name
Test status
Simulation time 29846923067 ps
CPU time 1303.56 seconds
Started Apr 23 03:10:19 PM PDT 24
Finished Apr 23 03:32:03 PM PDT 24
Peak memory 281448 kb
Host smart-b430e46f-f913-4103-a826-6494101c4acd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531279868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.531279868
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.1973130843
Short name T418
Test name
Test status
Simulation time 2718022702 ps
CPU time 182.08 seconds
Started Apr 23 03:10:20 PM PDT 24
Finished Apr 23 03:13:22 PM PDT 24
Peak memory 256828 kb
Host smart-1f826473-24a8-4049-82bc-5133c25092f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19731
30843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.1973130843
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.4141071118
Short name T513
Test name
Test status
Simulation time 1051495818 ps
CPU time 31.27 seconds
Started Apr 23 03:10:16 PM PDT 24
Finished Apr 23 03:10:48 PM PDT 24
Peak memory 255180 kb
Host smart-f682175e-772a-4784-ac5b-ea426993d1a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41410
71118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.4141071118
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.2028645863
Short name T319
Test name
Test status
Simulation time 44049343970 ps
CPU time 1254.91 seconds
Started Apr 23 03:10:24 PM PDT 24
Finished Apr 23 03:31:19 PM PDT 24
Peak memory 265088 kb
Host smart-59e3cde3-682b-47ce-a394-df5c1a24cb3e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028645863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.2028645863
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.1145885455
Short name T559
Test name
Test status
Simulation time 20505814229 ps
CPU time 1336.88 seconds
Started Apr 23 03:10:23 PM PDT 24
Finished Apr 23 03:32:40 PM PDT 24
Peak memory 273236 kb
Host smart-5965d82b-e7cc-45e9-b14e-7f1640da1cdb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145885455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.1145885455
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.1789402194
Short name T576
Test name
Test status
Simulation time 13092302629 ps
CPU time 520.83 seconds
Started Apr 23 03:10:23 PM PDT 24
Finished Apr 23 03:19:04 PM PDT 24
Peak memory 247568 kb
Host smart-e7244437-a3cb-4814-bb4c-9a99ff450479
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789402194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.1789402194
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.71328270
Short name T81
Test name
Test status
Simulation time 768948900 ps
CPU time 41.08 seconds
Started Apr 23 03:10:16 PM PDT 24
Finished Apr 23 03:10:58 PM PDT 24
Peak memory 248604 kb
Host smart-a42aafc8-e9ca-4084-9b08-50736d95d5b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71328
270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.71328270
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.2003313361
Short name T507
Test name
Test status
Simulation time 285752934 ps
CPU time 25.52 seconds
Started Apr 23 03:10:16 PM PDT 24
Finished Apr 23 03:10:42 PM PDT 24
Peak memory 248124 kb
Host smart-a1712fb1-50be-44c5-b7df-e169d696a08f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20033
13361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.2003313361
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.511731618
Short name T442
Test name
Test status
Simulation time 634147574 ps
CPU time 42.65 seconds
Started Apr 23 03:10:20 PM PDT 24
Finished Apr 23 03:11:03 PM PDT 24
Peak memory 248580 kb
Host smart-6d3c7abb-2dae-4fbc-839a-c71869ca2183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51173
1618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.511731618
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.513535542
Short name T522
Test name
Test status
Simulation time 565284491 ps
CPU time 44.72 seconds
Started Apr 23 03:10:14 PM PDT 24
Finished Apr 23 03:11:00 PM PDT 24
Peak memory 248852 kb
Host smart-f01dc3ef-01a6-4052-b074-565467068dcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51353
5542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.513535542
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.3348593696
Short name T30
Test name
Test status
Simulation time 17582350548 ps
CPU time 361.7 seconds
Started Apr 23 03:10:26 PM PDT 24
Finished Apr 23 03:16:28 PM PDT 24
Peak memory 256820 kb
Host smart-c04953f0-c824-4c05-a13d-91b706b42948
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348593696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.3348593696
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.3411508100
Short name T498
Test name
Test status
Simulation time 20290424544 ps
CPU time 1499.11 seconds
Started Apr 23 03:10:32 PM PDT 24
Finished Apr 23 03:35:31 PM PDT 24
Peak memory 268064 kb
Host smart-528e0049-98ef-4b24-a78c-41ed4cd68a97
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411508100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.3411508100
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.3297397099
Short name T602
Test name
Test status
Simulation time 3163041524 ps
CPU time 60.3 seconds
Started Apr 23 03:10:28 PM PDT 24
Finished Apr 23 03:11:28 PM PDT 24
Peak memory 248732 kb
Host smart-edfba028-e414-4e5c-a941-68df17e04537
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32973
97099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.3297397099
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.2313222873
Short name T555
Test name
Test status
Simulation time 451178507 ps
CPU time 8.58 seconds
Started Apr 23 03:10:29 PM PDT 24
Finished Apr 23 03:10:38 PM PDT 24
Peak memory 249236 kb
Host smart-ea0cf1b7-9395-4ea8-9626-699f12b11593
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23132
22873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.2313222873
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.3210460455
Short name T649
Test name
Test status
Simulation time 68365409598 ps
CPU time 1333.07 seconds
Started Apr 23 03:10:36 PM PDT 24
Finished Apr 23 03:32:49 PM PDT 24
Peak memory 288564 kb
Host smart-8f7aaf3c-9a11-432f-aeb8-6f3d1c06a6d6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210460455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.3210460455
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.4096431961
Short name T367
Test name
Test status
Simulation time 36911719756 ps
CPU time 2331.31 seconds
Started Apr 23 03:10:36 PM PDT 24
Finished Apr 23 03:49:28 PM PDT 24
Peak memory 289544 kb
Host smart-93dd04f3-bec3-4608-b749-6b1c55592381
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096431961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.4096431961
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.705023531
Short name T55
Test name
Test status
Simulation time 1063498413 ps
CPU time 22.87 seconds
Started Apr 23 03:10:27 PM PDT 24
Finished Apr 23 03:10:50 PM PDT 24
Peak memory 255448 kb
Host smart-63b8928e-4f43-4569-8482-9a0daa0a3837
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70502
3531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.705023531
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.2188712216
Short name T254
Test name
Test status
Simulation time 2093587738 ps
CPU time 34.99 seconds
Started Apr 23 03:10:28 PM PDT 24
Finished Apr 23 03:11:04 PM PDT 24
Peak memory 255052 kb
Host smart-390244fe-9f8f-4373-adcf-5bd20922d217
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21887
12216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.2188712216
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.3633680712
Short name T83
Test name
Test status
Simulation time 413318065 ps
CPU time 14.76 seconds
Started Apr 23 03:10:28 PM PDT 24
Finished Apr 23 03:10:43 PM PDT 24
Peak memory 247068 kb
Host smart-49e030bb-3368-4e82-bfb4-32f3a7766203
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36336
80712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.3633680712
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.3669618294
Short name T385
Test name
Test status
Simulation time 790307052 ps
CPU time 34.67 seconds
Started Apr 23 03:10:28 PM PDT 24
Finished Apr 23 03:11:03 PM PDT 24
Peak memory 255604 kb
Host smart-0e526379-616d-4df4-9118-9f7114db8fbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36696
18294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.3669618294
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.1944545980
Short name T593
Test name
Test status
Simulation time 9439950089 ps
CPU time 1108.82 seconds
Started Apr 23 03:10:43 PM PDT 24
Finished Apr 23 03:29:12 PM PDT 24
Peak memory 289428 kb
Host smart-3c8efac0-e4b8-4b96-b180-a9293ef1df7a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944545980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.1944545980
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.3040358867
Short name T15
Test name
Test status
Simulation time 91094300795 ps
CPU time 2215.53 seconds
Started Apr 23 03:10:41 PM PDT 24
Finished Apr 23 03:47:37 PM PDT 24
Peak memory 289724 kb
Host smart-1521666a-8982-4435-b411-d76c535ad446
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040358867 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.3040358867
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.1110873586
Short name T11
Test name
Test status
Simulation time 58768353938 ps
CPU time 3264.38 seconds
Started Apr 23 03:10:48 PM PDT 24
Finished Apr 23 04:05:13 PM PDT 24
Peak memory 287792 kb
Host smart-867e7b46-1496-4dad-beb8-aa8915006335
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110873586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.1110873586
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.2044266905
Short name T534
Test name
Test status
Simulation time 11694916610 ps
CPU time 200.37 seconds
Started Apr 23 03:10:46 PM PDT 24
Finished Apr 23 03:14:06 PM PDT 24
Peak memory 256292 kb
Host smart-499bff6b-8935-4f85-b537-67a34496ac14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20442
66905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.2044266905
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.3733218568
Short name T403
Test name
Test status
Simulation time 1651112356 ps
CPU time 16.11 seconds
Started Apr 23 03:10:44 PM PDT 24
Finished Apr 23 03:11:01 PM PDT 24
Peak memory 255136 kb
Host smart-f8ee422e-e2c6-4bda-98fa-b32b5aab4b9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37332
18568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.3733218568
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.2905310043
Short name T280
Test name
Test status
Simulation time 24895794910 ps
CPU time 947.33 seconds
Started Apr 23 03:10:51 PM PDT 24
Finished Apr 23 03:26:39 PM PDT 24
Peak memory 266108 kb
Host smart-00b684f3-e32b-471c-83d2-1b177357e680
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905310043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.2905310043
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.2077508258
Short name T112
Test name
Test status
Simulation time 28106914196 ps
CPU time 629.58 seconds
Started Apr 23 03:10:51 PM PDT 24
Finished Apr 23 03:21:21 PM PDT 24
Peak memory 271768 kb
Host smart-f7a1498e-e839-4891-9d0d-8f7872e7e350
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077508258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.2077508258
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.4114182430
Short name T290
Test name
Test status
Simulation time 13877137229 ps
CPU time 325.94 seconds
Started Apr 23 03:10:48 PM PDT 24
Finished Apr 23 03:16:14 PM PDT 24
Peak memory 247396 kb
Host smart-2cbbc04c-f015-443e-8b97-402f8178bcb3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114182430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.4114182430
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.1723769565
Short name T276
Test name
Test status
Simulation time 651931136 ps
CPU time 20.75 seconds
Started Apr 23 03:10:46 PM PDT 24
Finished Apr 23 03:11:07 PM PDT 24
Peak memory 248608 kb
Host smart-15ec2537-dace-4129-a04c-87d84af73ae0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17237
69565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.1723769565
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.2404382202
Short name T113
Test name
Test status
Simulation time 564995495 ps
CPU time 36.02 seconds
Started Apr 23 03:10:45 PM PDT 24
Finished Apr 23 03:11:21 PM PDT 24
Peak memory 255508 kb
Host smart-e73354d2-acf0-45ee-97d9-fa7ac2739626
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24043
82202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.2404382202
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.1124374789
Short name T85
Test name
Test status
Simulation time 3091039430 ps
CPU time 49.41 seconds
Started Apr 23 03:10:41 PM PDT 24
Finished Apr 23 03:11:31 PM PDT 24
Peak memory 248636 kb
Host smart-be985c69-a474-4f04-b374-b391d2739df2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11243
74789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.1124374789
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.4245433543
Short name T411
Test name
Test status
Simulation time 17279129662 ps
CPU time 960.09 seconds
Started Apr 23 03:10:56 PM PDT 24
Finished Apr 23 03:26:56 PM PDT 24
Peak memory 283216 kb
Host smart-a458630f-afd9-4961-a080-a7d4a20bd4a9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245433543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.4245433543
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.386286046
Short name T63
Test name
Test status
Simulation time 46825059782 ps
CPU time 1534.68 seconds
Started Apr 23 03:11:09 PM PDT 24
Finished Apr 23 03:36:44 PM PDT 24
Peak memory 267500 kb
Host smart-f9074192-acff-49e4-8752-4adab34b8480
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386286046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.386286046
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.3251592969
Short name T381
Test name
Test status
Simulation time 6801781334 ps
CPU time 138.78 seconds
Started Apr 23 03:11:05 PM PDT 24
Finished Apr 23 03:13:24 PM PDT 24
Peak memory 256360 kb
Host smart-bad2f6ee-65a8-4ee6-ab24-d61f41ab0647
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32515
92969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.3251592969
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.3964935894
Short name T539
Test name
Test status
Simulation time 1659023677 ps
CPU time 28 seconds
Started Apr 23 03:11:06 PM PDT 24
Finished Apr 23 03:11:34 PM PDT 24
Peak memory 254380 kb
Host smart-d655431b-6e95-42d6-9dec-d7b4b4d4a24e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39649
35894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.3964935894
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.4145457749
Short name T606
Test name
Test status
Simulation time 92474174867 ps
CPU time 2028.5 seconds
Started Apr 23 03:11:12 PM PDT 24
Finished Apr 23 03:45:01 PM PDT 24
Peak memory 268092 kb
Host smart-2cb9ebe9-f3be-4f60-9095-4b1342c4e229
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145457749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.4145457749
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.1493567320
Short name T557
Test name
Test status
Simulation time 15195702278 ps
CPU time 1065.56 seconds
Started Apr 23 03:11:14 PM PDT 24
Finished Apr 23 03:29:00 PM PDT 24
Peak memory 273248 kb
Host smart-49773525-862f-40d5-897f-7dcff7694f3b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493567320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.1493567320
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.1846842442
Short name T301
Test name
Test status
Simulation time 14083722371 ps
CPU time 563.07 seconds
Started Apr 23 03:11:11 PM PDT 24
Finished Apr 23 03:20:34 PM PDT 24
Peak memory 247516 kb
Host smart-9a642186-9dca-49f0-8ce5-14aaba855b60
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846842442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.1846842442
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.1485835212
Short name T461
Test name
Test status
Simulation time 1118730914 ps
CPU time 38.41 seconds
Started Apr 23 03:10:58 PM PDT 24
Finished Apr 23 03:11:36 PM PDT 24
Peak memory 255160 kb
Host smart-02590791-6ffa-42cc-aeb6-db6f36fa5f3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14858
35212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.1485835212
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.306199116
Short name T455
Test name
Test status
Simulation time 3487360956 ps
CPU time 39.4 seconds
Started Apr 23 03:10:57 PM PDT 24
Finished Apr 23 03:11:37 PM PDT 24
Peak memory 254672 kb
Host smart-48cd3cfc-4f1d-4d7d-8723-71c073f0c190
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30619
9116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.306199116
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.2835841733
Short name T77
Test name
Test status
Simulation time 3167680159 ps
CPU time 47.81 seconds
Started Apr 23 03:11:08 PM PDT 24
Finished Apr 23 03:11:56 PM PDT 24
Peak memory 255288 kb
Host smart-1425921f-f68b-4949-8245-f7448891baf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28358
41733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.2835841733
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.3978685211
Short name T609
Test name
Test status
Simulation time 982974994 ps
CPU time 58.41 seconds
Started Apr 23 03:10:56 PM PDT 24
Finished Apr 23 03:11:55 PM PDT 24
Peak memory 255552 kb
Host smart-4d81703a-2c77-4d8f-bf5b-ef21c4606183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39786
85211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.3978685211
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.2895045241
Short name T186
Test name
Test status
Simulation time 18466281363 ps
CPU time 552.72 seconds
Started Apr 23 03:11:19 PM PDT 24
Finished Apr 23 03:20:32 PM PDT 24
Peak memory 273324 kb
Host smart-0ee835d5-9e73-4880-a53a-ca1e4e7c77d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895045241 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.2895045241
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.2075034478
Short name T524
Test name
Test status
Simulation time 21792783140 ps
CPU time 1416.62 seconds
Started Apr 23 03:11:25 PM PDT 24
Finished Apr 23 03:35:02 PM PDT 24
Peak memory 289272 kb
Host smart-0655669d-0953-4128-9904-ab2b045d0976
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075034478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.2075034478
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.2061710703
Short name T44
Test name
Test status
Simulation time 8308518792 ps
CPU time 259.12 seconds
Started Apr 23 03:11:24 PM PDT 24
Finished Apr 23 03:15:44 PM PDT 24
Peak memory 250628 kb
Host smart-6d369ff8-cede-455e-a001-aed778adab34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20617
10703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.2061710703
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.1253097022
Short name T89
Test name
Test status
Simulation time 337732873 ps
CPU time 21.11 seconds
Started Apr 23 03:11:21 PM PDT 24
Finished Apr 23 03:11:42 PM PDT 24
Peak memory 254932 kb
Host smart-6611e99c-afcc-4c89-ac22-86694b6c90e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12530
97022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.1253097022
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.2958134978
Short name T307
Test name
Test status
Simulation time 46362617783 ps
CPU time 1396.08 seconds
Started Apr 23 03:11:27 PM PDT 24
Finished Apr 23 03:34:43 PM PDT 24
Peak memory 273100 kb
Host smart-09e8936b-c600-40bc-8507-6d951fc65ce4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958134978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.2958134978
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.2545623071
Short name T666
Test name
Test status
Simulation time 169475091138 ps
CPU time 1184.37 seconds
Started Apr 23 03:11:36 PM PDT 24
Finished Apr 23 03:31:21 PM PDT 24
Peak memory 271924 kb
Host smart-751c6110-413f-42a4-9108-68c6f0909156
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545623071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.2545623071
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.623353180
Short name T420
Test name
Test status
Simulation time 2344394640 ps
CPU time 90.59 seconds
Started Apr 23 03:11:23 PM PDT 24
Finished Apr 23 03:12:54 PM PDT 24
Peak memory 247376 kb
Host smart-7a04e7bd-0bda-4ea0-8c66-516e14b5df3a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623353180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.623353180
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.3456972596
Short name T560
Test name
Test status
Simulation time 417870198 ps
CPU time 38.05 seconds
Started Apr 23 03:11:22 PM PDT 24
Finished Apr 23 03:12:01 PM PDT 24
Peak memory 248532 kb
Host smart-9b094b37-864e-40c1-b1d5-13d6e57b7a23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34569
72596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.3456972596
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.2937347564
Short name T643
Test name
Test status
Simulation time 12252142530 ps
CPU time 37.47 seconds
Started Apr 23 03:11:22 PM PDT 24
Finished Apr 23 03:11:59 PM PDT 24
Peak memory 254924 kb
Host smart-f656170f-6839-47f6-8663-e98de91d7df1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29373
47564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.2937347564
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.909109377
Short name T269
Test name
Test status
Simulation time 2746713587 ps
CPU time 58.05 seconds
Started Apr 23 03:11:18 PM PDT 24
Finished Apr 23 03:12:17 PM PDT 24
Peak memory 248724 kb
Host smart-32ca55b9-e1e4-461d-89e5-cad5d1f3fb8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90910
9377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.909109377
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.2742192496
Short name T260
Test name
Test status
Simulation time 24718675578 ps
CPU time 567.39 seconds
Started Apr 23 03:11:31 PM PDT 24
Finished Apr 23 03:20:59 PM PDT 24
Peak memory 265080 kb
Host smart-0f052720-4d7c-444d-8e32-ca1df7cc8707
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742192496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.2742192496
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.3530718479
Short name T219
Test name
Test status
Simulation time 55750039 ps
CPU time 4.29 seconds
Started Apr 23 03:03:20 PM PDT 24
Finished Apr 23 03:03:25 PM PDT 24
Peak memory 248776 kb
Host smart-e97e3921-e9d6-4015-af38-a906deb8ac2c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3530718479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.3530718479
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.1709240809
Short name T549
Test name
Test status
Simulation time 53246604719 ps
CPU time 1711.51 seconds
Started Apr 23 03:03:08 PM PDT 24
Finished Apr 23 03:31:40 PM PDT 24
Peak memory 272980 kb
Host smart-ba5d69ac-fb05-47d1-9511-893f611fa1fe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709240809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.1709240809
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.3484137120
Short name T430
Test name
Test status
Simulation time 515376903 ps
CPU time 46.64 seconds
Started Apr 23 03:03:07 PM PDT 24
Finished Apr 23 03:03:54 PM PDT 24
Peak memory 256248 kb
Host smart-67be5c18-f40a-43ae-baf6-dcd73f088cb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34841
37120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.3484137120
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.1282680877
Short name T664
Test name
Test status
Simulation time 745500557 ps
CPU time 22.02 seconds
Started Apr 23 03:03:05 PM PDT 24
Finished Apr 23 03:03:27 PM PDT 24
Peak memory 255244 kb
Host smart-08eabf7c-6377-44b7-b3bd-bb642fa1bbe3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12826
80877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.1282680877
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.2651377917
Short name T270
Test name
Test status
Simulation time 143637645856 ps
CPU time 2034.66 seconds
Started Apr 23 03:03:11 PM PDT 24
Finished Apr 23 03:37:07 PM PDT 24
Peak memory 281456 kb
Host smart-fafe0b0e-8b1a-4f83-99c8-5dfd3af4580b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651377917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.2651377917
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.3042458420
Short name T286
Test name
Test status
Simulation time 28569097458 ps
CPU time 598.57 seconds
Started Apr 23 03:03:08 PM PDT 24
Finished Apr 23 03:13:08 PM PDT 24
Peak memory 247400 kb
Host smart-f5cbfb5a-e74a-4b65-a84f-11871fe4f0db
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042458420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.3042458420
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.1375098314
Short name T104
Test name
Test status
Simulation time 1543241657 ps
CPU time 45.26 seconds
Started Apr 23 03:03:06 PM PDT 24
Finished Apr 23 03:03:51 PM PDT 24
Peak memory 256752 kb
Host smart-ed425fba-2357-400e-a091-a3d58dd9b6fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13750
98314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.1375098314
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.618282613
Short name T409
Test name
Test status
Simulation time 803230548 ps
CPU time 54.89 seconds
Started Apr 23 03:03:06 PM PDT 24
Finished Apr 23 03:04:01 PM PDT 24
Peak memory 254556 kb
Host smart-c3fb9ac4-2c75-4806-bd3d-197d92cf3cc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61828
2613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.618282613
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.1553327702
Short name T40
Test name
Test status
Simulation time 696324781 ps
CPU time 43.45 seconds
Started Apr 23 03:03:07 PM PDT 24
Finished Apr 23 03:03:51 PM PDT 24
Peak memory 246984 kb
Host smart-23213fcf-a6a7-4c0e-b59f-9714c433dc2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15533
27702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.1553327702
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.3276115536
Short name T359
Test name
Test status
Simulation time 567050183 ps
CPU time 38.58 seconds
Started Apr 23 03:03:04 PM PDT 24
Finished Apr 23 03:03:43 PM PDT 24
Peak memory 248640 kb
Host smart-5e7821cf-0303-420e-b21f-9eb6565650dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32761
15536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.3276115536
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.2475149068
Short name T98
Test name
Test status
Simulation time 25230091296 ps
CPU time 1709.16 seconds
Started Apr 23 03:03:29 PM PDT 24
Finished Apr 23 03:31:59 PM PDT 24
Peak memory 289740 kb
Host smart-d8e53c1c-1c48-425f-84fe-641515a71f8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475149068 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.2475149068
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.702490379
Short name T680
Test name
Test status
Simulation time 10199708955 ps
CPU time 1126.01 seconds
Started Apr 23 03:11:38 PM PDT 24
Finished Apr 23 03:30:24 PM PDT 24
Peak memory 273264 kb
Host smart-f594ad7e-60c6-440e-8795-21f1cfa69d2e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702490379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.702490379
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.3344401217
Short name T383
Test name
Test status
Simulation time 2984712973 ps
CPU time 100.8 seconds
Started Apr 23 03:11:37 PM PDT 24
Finished Apr 23 03:13:18 PM PDT 24
Peak memory 256220 kb
Host smart-773198a7-fb15-4f58-98de-b17610bb36df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33444
01217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.3344401217
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.3554794861
Short name T586
Test name
Test status
Simulation time 530182088 ps
CPU time 37.74 seconds
Started Apr 23 03:11:36 PM PDT 24
Finished Apr 23 03:12:14 PM PDT 24
Peak memory 248316 kb
Host smart-4f4ea468-44ac-4718-8ce9-596fa4eb31b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35547
94861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.3554794861
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.3640885445
Short name T618
Test name
Test status
Simulation time 11027300231 ps
CPU time 1008.48 seconds
Started Apr 23 03:11:42 PM PDT 24
Finished Apr 23 03:28:31 PM PDT 24
Peak memory 273236 kb
Host smart-b6d58cb8-01da-4041-8a9b-b26339f451ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640885445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.3640885445
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.2638948276
Short name T432
Test name
Test status
Simulation time 169478526096 ps
CPU time 2425.38 seconds
Started Apr 23 03:11:43 PM PDT 24
Finished Apr 23 03:52:08 PM PDT 24
Peak memory 282040 kb
Host smart-3402fcdd-aae3-43c4-935a-8813a12ee60e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638948276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.2638948276
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.712370300
Short name T29
Test name
Test status
Simulation time 10168114695 ps
CPU time 203.79 seconds
Started Apr 23 03:11:38 PM PDT 24
Finished Apr 23 03:15:02 PM PDT 24
Peak memory 247612 kb
Host smart-2099e95b-125e-429f-aaf7-fc0627ce1611
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712370300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.712370300
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.2493455181
Short name T106
Test name
Test status
Simulation time 2139287486 ps
CPU time 35.25 seconds
Started Apr 23 03:11:35 PM PDT 24
Finished Apr 23 03:12:10 PM PDT 24
Peak memory 248592 kb
Host smart-89257de4-33a5-4264-bde5-91689af4fd07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24934
55181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.2493455181
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.2697122745
Short name T346
Test name
Test status
Simulation time 713332261 ps
CPU time 27.01 seconds
Started Apr 23 03:11:35 PM PDT 24
Finished Apr 23 03:12:02 PM PDT 24
Peak memory 247032 kb
Host smart-572697ef-2e47-4e0e-b32f-a5defb2c2107
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26971
22745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.2697122745
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.1756485624
Short name T101
Test name
Test status
Simulation time 2539938780 ps
CPU time 35.02 seconds
Started Apr 23 03:11:37 PM PDT 24
Finished Apr 23 03:12:13 PM PDT 24
Peak memory 255184 kb
Host smart-1601d246-ad29-40a0-a8f6-5bd49f62f8f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17564
85624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.1756485624
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.3452172758
Short name T464
Test name
Test status
Simulation time 390739113 ps
CPU time 43.09 seconds
Started Apr 23 03:11:34 PM PDT 24
Finished Apr 23 03:12:18 PM PDT 24
Peak memory 248600 kb
Host smart-01aa1915-a6a6-461a-bdfa-a30e52af465d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34521
72758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.3452172758
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.3383511481
Short name T382
Test name
Test status
Simulation time 16054610663 ps
CPU time 690.41 seconds
Started Apr 23 03:11:54 PM PDT 24
Finished Apr 23 03:23:25 PM PDT 24
Peak memory 271712 kb
Host smart-2ecca050-1af4-41c0-bbd2-87fabbfc55ef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383511481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.3383511481
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.3972586372
Short name T388
Test name
Test status
Simulation time 3754563348 ps
CPU time 222.49 seconds
Started Apr 23 03:11:56 PM PDT 24
Finished Apr 23 03:15:39 PM PDT 24
Peak memory 256484 kb
Host smart-92aed302-33bb-4081-9700-4a818951ffcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39725
86372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.3972586372
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.2875944321
Short name T87
Test name
Test status
Simulation time 461001043 ps
CPU time 13.18 seconds
Started Apr 23 03:11:51 PM PDT 24
Finished Apr 23 03:12:04 PM PDT 24
Peak memory 254560 kb
Host smart-3a62f55a-1fd1-4e90-8f27-050d47a4fe7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28759
44321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.2875944321
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.2306433027
Short name T316
Test name
Test status
Simulation time 154859990846 ps
CPU time 2037.96 seconds
Started Apr 23 03:11:58 PM PDT 24
Finished Apr 23 03:45:57 PM PDT 24
Peak memory 271580 kb
Host smart-8cce0fce-9013-4886-a523-3e689d7b19de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306433027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.2306433027
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.668215625
Short name T630
Test name
Test status
Simulation time 43022122688 ps
CPU time 1267.64 seconds
Started Apr 23 03:11:58 PM PDT 24
Finished Apr 23 03:33:07 PM PDT 24
Peak memory 284476 kb
Host smart-56214a2f-0f4b-425c-98b0-1c8f43e0db97
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668215625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.668215625
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.952133817
Short name T305
Test name
Test status
Simulation time 27238633319 ps
CPU time 545.8 seconds
Started Apr 23 03:11:56 PM PDT 24
Finished Apr 23 03:21:02 PM PDT 24
Peak memory 247596 kb
Host smart-e6e8e92d-b956-4c00-8673-b85d9c945254
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952133817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.952133817
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.2041790381
Short name T443
Test name
Test status
Simulation time 168943613 ps
CPU time 14.41 seconds
Started Apr 23 03:11:52 PM PDT 24
Finished Apr 23 03:12:07 PM PDT 24
Peak memory 255124 kb
Host smart-96c9b604-fed5-4a64-abd4-0a52d5511684
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20417
90381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.2041790381
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.2835951774
Short name T126
Test name
Test status
Simulation time 290433230 ps
CPU time 8.16 seconds
Started Apr 23 03:11:51 PM PDT 24
Finished Apr 23 03:12:00 PM PDT 24
Peak memory 248244 kb
Host smart-05bf7646-5ec1-4d6d-ac33-587b0fd12c95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28359
51774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.2835951774
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.3919430628
Short name T641
Test name
Test status
Simulation time 453166513 ps
CPU time 28.31 seconds
Started Apr 23 03:11:56 PM PDT 24
Finished Apr 23 03:12:25 PM PDT 24
Peak memory 247140 kb
Host smart-d3329a6f-8c27-4281-84cb-d02bf6dcd390
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39194
30628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.3919430628
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.4197877433
Short name T503
Test name
Test status
Simulation time 973945895 ps
CPU time 27.49 seconds
Started Apr 23 03:11:51 PM PDT 24
Finished Apr 23 03:12:19 PM PDT 24
Peak memory 248700 kb
Host smart-f5a7aa50-bf23-42a2-844f-e38f8ba92fbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41978
77433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.4197877433
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.2466239776
Short name T673
Test name
Test status
Simulation time 9517511603 ps
CPU time 969.87 seconds
Started Apr 23 03:12:00 PM PDT 24
Finished Apr 23 03:28:10 PM PDT 24
Peak memory 268184 kb
Host smart-a2c0d8f4-d8a0-400f-b20f-136d0c021de1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466239776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.2466239776
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.3481744823
Short name T125
Test name
Test status
Simulation time 134665222403 ps
CPU time 975.56 seconds
Started Apr 23 03:12:14 PM PDT 24
Finished Apr 23 03:28:30 PM PDT 24
Peak memory 272672 kb
Host smart-474ba211-b44b-40f8-bfc8-fdeb9c980c16
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481744823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.3481744823
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.923334048
Short name T468
Test name
Test status
Simulation time 187805198 ps
CPU time 16.49 seconds
Started Apr 23 03:12:14 PM PDT 24
Finished Apr 23 03:12:31 PM PDT 24
Peak memory 254396 kb
Host smart-2d7a011e-0336-4426-9c61-0cbc957c46f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92333
4048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.923334048
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.3693410934
Short name T188
Test name
Test status
Simulation time 179231830 ps
CPU time 8.38 seconds
Started Apr 23 03:12:06 PM PDT 24
Finished Apr 23 03:12:14 PM PDT 24
Peak memory 252768 kb
Host smart-1152e1a4-12e3-4bb2-b73b-a302f4f291de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36934
10934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.3693410934
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.2671920843
Short name T25
Test name
Test status
Simulation time 75359070570 ps
CPU time 1228.68 seconds
Started Apr 23 03:12:15 PM PDT 24
Finished Apr 23 03:32:44 PM PDT 24
Peak memory 288548 kb
Host smart-5a66b3d3-2e7c-416b-a97a-9f2853849518
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671920843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.2671920843
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.4124350377
Short name T226
Test name
Test status
Simulation time 48617081744 ps
CPU time 3100.4 seconds
Started Apr 23 03:12:16 PM PDT 24
Finished Apr 23 04:03:57 PM PDT 24
Peak memory 285564 kb
Host smart-2cd7257d-15d9-4076-8d7c-1bb7b0d1995a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124350377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.4124350377
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.1635755211
Short name T3
Test name
Test status
Simulation time 19086465661 ps
CPU time 148.59 seconds
Started Apr 23 03:12:14 PM PDT 24
Finished Apr 23 03:14:43 PM PDT 24
Peak memory 247868 kb
Host smart-d629a1e8-dcb3-4a68-81f6-536140f06106
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635755211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.1635755211
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.734919128
Short name T659
Test name
Test status
Simulation time 351261399 ps
CPU time 21.29 seconds
Started Apr 23 03:12:04 PM PDT 24
Finished Apr 23 03:12:26 PM PDT 24
Peak memory 255332 kb
Host smart-0d25be65-fb4e-4dab-918b-4af943df543f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73491
9128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.734919128
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.802234266
Short name T604
Test name
Test status
Simulation time 1364858592 ps
CPU time 52.84 seconds
Started Apr 23 03:12:05 PM PDT 24
Finished Apr 23 03:12:58 PM PDT 24
Peak memory 255180 kb
Host smart-7e4ed2a1-de5d-4128-b240-d1d43aefbb60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80223
4266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.802234266
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.3603548209
Short name T94
Test name
Test status
Simulation time 160987583 ps
CPU time 15.05 seconds
Started Apr 23 03:12:14 PM PDT 24
Finished Apr 23 03:12:30 PM PDT 24
Peak memory 251072 kb
Host smart-23e7ba24-9b11-48ec-ad47-7f85571cac23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36035
48209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.3603548209
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.220506144
Short name T672
Test name
Test status
Simulation time 1654984083 ps
CPU time 54.51 seconds
Started Apr 23 03:12:01 PM PDT 24
Finished Apr 23 03:12:56 PM PDT 24
Peak memory 256788 kb
Host smart-dda16dd1-67ea-4173-a723-e08c7cc4aba3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22050
6144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.220506144
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.924305821
Short name T484
Test name
Test status
Simulation time 506341662139 ps
CPU time 3497.91 seconds
Started Apr 23 03:12:16 PM PDT 24
Finished Apr 23 04:10:34 PM PDT 24
Peak memory 304664 kb
Host smart-0d91b0c9-8567-41a6-85ca-3dc6c4ba8bab
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924305821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_han
dler_stress_all.924305821
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.1323952010
Short name T447
Test name
Test status
Simulation time 47671186103 ps
CPU time 2600.44 seconds
Started Apr 23 03:12:30 PM PDT 24
Finished Apr 23 03:55:51 PM PDT 24
Peak memory 289064 kb
Host smart-5384cc3d-d62a-431c-ae45-0bb866f9c727
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323952010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.1323952010
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.3962902374
Short name T569
Test name
Test status
Simulation time 3178404216 ps
CPU time 127.89 seconds
Started Apr 23 03:12:25 PM PDT 24
Finished Apr 23 03:14:34 PM PDT 24
Peak memory 249680 kb
Host smart-85c5e4d3-e966-4b1d-a74e-1c5790489ca1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39629
02374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.3962902374
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.1981659752
Short name T32
Test name
Test status
Simulation time 3388591079 ps
CPU time 46.69 seconds
Started Apr 23 03:12:26 PM PDT 24
Finished Apr 23 03:13:13 PM PDT 24
Peak memory 248432 kb
Host smart-27a2917c-5606-4864-88ca-faaf4cd2a4f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19816
59752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.1981659752
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.1835283889
Short name T277
Test name
Test status
Simulation time 98552124914 ps
CPU time 3057.56 seconds
Started Apr 23 03:12:27 PM PDT 24
Finished Apr 23 04:03:25 PM PDT 24
Peak memory 289080 kb
Host smart-c1c172a3-0304-4732-a358-cb538b2992d8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835283889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.1835283889
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.1377104018
Short name T632
Test name
Test status
Simulation time 23719663221 ps
CPU time 270.28 seconds
Started Apr 23 03:12:30 PM PDT 24
Finished Apr 23 03:17:00 PM PDT 24
Peak memory 247364 kb
Host smart-8e368840-348c-471d-a58d-4a38abc4c069
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377104018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.1377104018
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.1637230716
Short name T350
Test name
Test status
Simulation time 990367797 ps
CPU time 40.72 seconds
Started Apr 23 03:12:18 PM PDT 24
Finished Apr 23 03:12:59 PM PDT 24
Peak memory 248628 kb
Host smart-7bbfc02a-b8e7-43d7-b89e-71781398c2c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16372
30716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.1637230716
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.651351756
Short name T353
Test name
Test status
Simulation time 236206649 ps
CPU time 14.02 seconds
Started Apr 23 03:12:23 PM PDT 24
Finished Apr 23 03:12:37 PM PDT 24
Peak memory 246816 kb
Host smart-e034ebfb-4cfd-4289-9501-0ef1270704fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65135
1756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.651351756
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.3581921835
Short name T84
Test name
Test status
Simulation time 108963381 ps
CPU time 7.62 seconds
Started Apr 23 03:12:26 PM PDT 24
Finished Apr 23 03:12:34 PM PDT 24
Peak memory 247024 kb
Host smart-53381801-86e1-4112-a5ab-38da9ffc142e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35819
21835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.3581921835
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.3615125193
Short name T637
Test name
Test status
Simulation time 1499222564 ps
CPU time 44.2 seconds
Started Apr 23 03:12:19 PM PDT 24
Finished Apr 23 03:13:03 PM PDT 24
Peak memory 248776 kb
Host smart-59fa8a76-7cf1-4339-8a82-cf5962d2d049
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36151
25193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.3615125193
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.2092295730
Short name T78
Test name
Test status
Simulation time 15502320314 ps
CPU time 730.02 seconds
Started Apr 23 03:12:35 PM PDT 24
Finished Apr 23 03:24:45 PM PDT 24
Peak memory 265032 kb
Host smart-5ba6d8f5-bacb-4031-8ef8-9c67168b6a65
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092295730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.2092295730
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.4090541637
Short name T518
Test name
Test status
Simulation time 2795357541 ps
CPU time 42.13 seconds
Started Apr 23 03:12:35 PM PDT 24
Finished Apr 23 03:13:17 PM PDT 24
Peak memory 255896 kb
Host smart-428f1810-3976-4a20-8a6f-73a0760fc1fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40905
41637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.4090541637
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.2919911275
Short name T521
Test name
Test status
Simulation time 185643091 ps
CPU time 22.83 seconds
Started Apr 23 03:12:32 PM PDT 24
Finished Apr 23 03:12:56 PM PDT 24
Peak memory 255024 kb
Host smart-8afa597e-cb90-414e-bb18-e4d703b3539e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29199
11275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.2919911275
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.1504169764
Short name T588
Test name
Test status
Simulation time 38701932389 ps
CPU time 2410.06 seconds
Started Apr 23 03:12:38 PM PDT 24
Finished Apr 23 03:52:49 PM PDT 24
Peak memory 289212 kb
Host smart-ac475f6a-f7ba-4f6f-b9bb-5225bf8ee9a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504169764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.1504169764
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.3026425971
Short name T631
Test name
Test status
Simulation time 96954666459 ps
CPU time 2781.2 seconds
Started Apr 23 03:12:38 PM PDT 24
Finished Apr 23 03:59:00 PM PDT 24
Peak memory 284824 kb
Host smart-19cc0bac-e3a2-4e4b-8d89-5a5eed06f58d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026425971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.3026425971
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.1499280843
Short name T304
Test name
Test status
Simulation time 64213786600 ps
CPU time 420.87 seconds
Started Apr 23 03:12:38 PM PDT 24
Finished Apr 23 03:19:40 PM PDT 24
Peak memory 247540 kb
Host smart-7b302b15-8eb5-4108-9809-51863f8f9d41
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499280843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.1499280843
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.2537804361
Short name T371
Test name
Test status
Simulation time 136662480 ps
CPU time 5.87 seconds
Started Apr 23 03:12:34 PM PDT 24
Finished Apr 23 03:12:40 PM PDT 24
Peak memory 248560 kb
Host smart-33f22318-b2fe-4b4f-bade-742143e04f35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25378
04361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.2537804361
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.1471222192
Short name T622
Test name
Test status
Simulation time 219348895 ps
CPU time 14.51 seconds
Started Apr 23 03:12:33 PM PDT 24
Finished Apr 23 03:12:47 PM PDT 24
Peak memory 246876 kb
Host smart-b906e1da-3ce7-48da-95b6-cde50a6774c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14712
22192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.1471222192
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.971479715
Short name T256
Test name
Test status
Simulation time 1366172762 ps
CPU time 13.68 seconds
Started Apr 23 03:12:35 PM PDT 24
Finished Apr 23 03:12:49 PM PDT 24
Peak memory 247036 kb
Host smart-9f328a2a-2f5d-4c26-80d1-dee0a8f9a32c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97147
9715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.971479715
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.2650395625
Short name T638
Test name
Test status
Simulation time 1123568726 ps
CPU time 30.34 seconds
Started Apr 23 03:12:43 PM PDT 24
Finished Apr 23 03:13:13 PM PDT 24
Peak memory 248512 kb
Host smart-3c5d1a7f-99f9-4a0d-a821-68f747d58956
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26503
95625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.2650395625
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.4143302605
Short name T679
Test name
Test status
Simulation time 3346099298 ps
CPU time 23.01 seconds
Started Apr 23 03:12:41 PM PDT 24
Finished Apr 23 03:13:05 PM PDT 24
Peak memory 255520 kb
Host smart-a175ed88-bffe-4eef-b470-a67f4a9fca07
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143302605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.4143302605
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.2552188430
Short name T201
Test name
Test status
Simulation time 38408753801 ps
CPU time 1965.2 seconds
Started Apr 23 03:12:46 PM PDT 24
Finished Apr 23 03:45:31 PM PDT 24
Peak memory 305448 kb
Host smart-a35f0c48-df20-48a3-8525-7b112f3bc7da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552188430 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.2552188430
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.2389812486
Short name T417
Test name
Test status
Simulation time 13134342187 ps
CPU time 1163.96 seconds
Started Apr 23 03:12:48 PM PDT 24
Finished Apr 23 03:32:13 PM PDT 24
Peak memory 281444 kb
Host smart-cc2bf417-a978-487e-bd6b-8b68d9c381c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389812486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.2389812486
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.1533688103
Short name T224
Test name
Test status
Simulation time 8493448378 ps
CPU time 190.11 seconds
Started Apr 23 03:12:46 PM PDT 24
Finished Apr 23 03:15:57 PM PDT 24
Peak memory 256640 kb
Host smart-c3121510-407a-400d-b773-95a96bedcf61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15336
88103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.1533688103
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.3730050951
Short name T446
Test name
Test status
Simulation time 387760690 ps
CPU time 44.16 seconds
Started Apr 23 03:12:48 PM PDT 24
Finished Apr 23 03:13:32 PM PDT 24
Peak memory 255192 kb
Host smart-2fb70177-2499-42a6-b9e4-bf3a6458490e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37300
50951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.3730050951
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.3955496198
Short name T322
Test name
Test status
Simulation time 7838639112 ps
CPU time 742.75 seconds
Started Apr 23 03:12:52 PM PDT 24
Finished Apr 23 03:25:15 PM PDT 24
Peak memory 272968 kb
Host smart-f5599e80-fe7c-4842-8206-59fa2195fd56
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955496198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.3955496198
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.1207058671
Short name T592
Test name
Test status
Simulation time 18976642777 ps
CPU time 967.32 seconds
Started Apr 23 03:12:51 PM PDT 24
Finished Apr 23 03:28:59 PM PDT 24
Peak memory 270196 kb
Host smart-67075f0f-19df-4825-ae0d-ff35c80a9bc9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207058671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.1207058671
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.3266143938
Short name T189
Test name
Test status
Simulation time 58303171947 ps
CPU time 548.84 seconds
Started Apr 23 03:12:48 PM PDT 24
Finished Apr 23 03:21:57 PM PDT 24
Peak memory 247348 kb
Host smart-0bb62a21-4fb2-4635-af93-119e47a6e412
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266143938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.3266143938
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.1469408812
Short name T665
Test name
Test status
Simulation time 183182707 ps
CPU time 22.2 seconds
Started Apr 23 03:12:45 PM PDT 24
Finished Apr 23 03:13:07 PM PDT 24
Peak memory 248664 kb
Host smart-9017df77-5ad3-4771-9188-6f8aa0826fe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14694
08812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.1469408812
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.3010256178
Short name T487
Test name
Test status
Simulation time 1632780426 ps
CPU time 29.08 seconds
Started Apr 23 03:12:44 PM PDT 24
Finished Apr 23 03:13:14 PM PDT 24
Peak memory 246972 kb
Host smart-1c181b51-08ed-453c-a7a0-ddc987f17799
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30102
56178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.3010256178
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.1070224377
Short name T610
Test name
Test status
Simulation time 31611947 ps
CPU time 3.03 seconds
Started Apr 23 03:12:48 PM PDT 24
Finished Apr 23 03:12:51 PM PDT 24
Peak memory 238744 kb
Host smart-b4f229ed-0ebe-4781-9b7e-a3f0ecd6ce5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10702
24377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.1070224377
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.2208855016
Short name T597
Test name
Test status
Simulation time 2006249727 ps
CPU time 33.75 seconds
Started Apr 23 03:12:45 PM PDT 24
Finished Apr 23 03:13:19 PM PDT 24
Peak memory 255348 kb
Host smart-13a8319d-308f-4d18-a038-da8a16833bcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22088
55016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.2208855016
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.626788357
Short name T390
Test name
Test status
Simulation time 44358429843 ps
CPU time 774.28 seconds
Started Apr 23 03:13:06 PM PDT 24
Finished Apr 23 03:26:01 PM PDT 24
Peak memory 273192 kb
Host smart-8fbbd31a-1ae8-4568-a645-6a9e93ffd3ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626788357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.626788357
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.204482881
Short name T508
Test name
Test status
Simulation time 4770432858 ps
CPU time 288.87 seconds
Started Apr 23 03:13:02 PM PDT 24
Finished Apr 23 03:17:52 PM PDT 24
Peak memory 250732 kb
Host smart-068cf764-c6ba-4f08-ad1a-4e787344175c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20448
2881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.204482881
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.1384746472
Short name T492
Test name
Test status
Simulation time 1235795790 ps
CPU time 81.27 seconds
Started Apr 23 03:13:02 PM PDT 24
Finished Apr 23 03:14:23 PM PDT 24
Peak memory 255664 kb
Host smart-bcc68af9-90f6-4641-9c91-3476b16a94f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13847
46472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.1384746472
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.2202066146
Short name T481
Test name
Test status
Simulation time 17626718598 ps
CPU time 1595.99 seconds
Started Apr 23 03:13:09 PM PDT 24
Finished Apr 23 03:39:46 PM PDT 24
Peak memory 288668 kb
Host smart-0666b073-e3df-466d-ac4b-221ed802a308
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202066146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.2202066146
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.338246621
Short name T405
Test name
Test status
Simulation time 55383677898 ps
CPU time 863.2 seconds
Started Apr 23 03:13:09 PM PDT 24
Finished Apr 23 03:27:32 PM PDT 24
Peak memory 272304 kb
Host smart-7b9fde4f-22b1-4728-815c-6b541e17cea4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338246621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.338246621
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.1347144219
Short name T6
Test name
Test status
Simulation time 10114595959 ps
CPU time 417.43 seconds
Started Apr 23 03:13:10 PM PDT 24
Finished Apr 23 03:20:08 PM PDT 24
Peak memory 247596 kb
Host smart-886bc244-9a8d-4d74-8ddb-e6c1c7840c88
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347144219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.1347144219
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.1039947211
Short name T608
Test name
Test status
Simulation time 357346542 ps
CPU time 20.74 seconds
Started Apr 23 03:12:59 PM PDT 24
Finished Apr 23 03:13:20 PM PDT 24
Peak memory 248636 kb
Host smart-9b53f672-841d-41a2-b3f9-0f05ee5ec1b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10399
47211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.1039947211
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.2806642103
Short name T121
Test name
Test status
Simulation time 892792914 ps
CPU time 30.45 seconds
Started Apr 23 03:13:01 PM PDT 24
Finished Apr 23 03:13:32 PM PDT 24
Peak memory 254328 kb
Host smart-1a8cf9e8-da14-4da3-981f-0efc019ab051
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28066
42103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.2806642103
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.1209254415
Short name T691
Test name
Test status
Simulation time 166738820 ps
CPU time 22.89 seconds
Started Apr 23 03:13:02 PM PDT 24
Finished Apr 23 03:13:26 PM PDT 24
Peak memory 256244 kb
Host smart-b6cbc890-56c0-4ca7-9c1d-f4b43d72a4d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12092
54415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.1209254415
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.4023567090
Short name T360
Test name
Test status
Simulation time 23444981 ps
CPU time 4.34 seconds
Started Apr 23 03:12:58 PM PDT 24
Finished Apr 23 03:13:02 PM PDT 24
Peak memory 240336 kb
Host smart-71ebd2db-6572-4043-be57-205242ba3b1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40235
67090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.4023567090
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.1743501146
Short name T200
Test name
Test status
Simulation time 74705729396 ps
CPU time 2273.48 seconds
Started Apr 23 03:13:15 PM PDT 24
Finished Apr 23 03:51:09 PM PDT 24
Peak memory 298008 kb
Host smart-469347da-47d5-4379-bc04-bf23f71fb87b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743501146 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.1743501146
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.386625908
Short name T686
Test name
Test status
Simulation time 138048502539 ps
CPU time 1431.26 seconds
Started Apr 23 03:13:23 PM PDT 24
Finished Apr 23 03:37:15 PM PDT 24
Peak memory 287648 kb
Host smart-1548fedd-4155-4d37-9033-52b43b1d0a38
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386625908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.386625908
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.1255691827
Short name T449
Test name
Test status
Simulation time 8045023698 ps
CPU time 246.34 seconds
Started Apr 23 03:13:24 PM PDT 24
Finished Apr 23 03:17:30 PM PDT 24
Peak memory 250736 kb
Host smart-9847f31f-5919-450b-bf9f-2cb6f114edf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12556
91827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.1255691827
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.2065057737
Short name T504
Test name
Test status
Simulation time 1246180291 ps
CPU time 48.98 seconds
Started Apr 23 03:13:21 PM PDT 24
Finished Apr 23 03:14:10 PM PDT 24
Peak memory 254616 kb
Host smart-daa28735-f7a6-41d7-8e41-8ca084d1ee78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20650
57737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.2065057737
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.202097802
Short name T311
Test name
Test status
Simulation time 186385620984 ps
CPU time 1310.96 seconds
Started Apr 23 03:13:27 PM PDT 24
Finished Apr 23 03:35:18 PM PDT 24
Peak memory 265032 kb
Host smart-84c1df93-8ead-4c15-9e73-fa5e6d4b4373
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202097802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.202097802
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.1060437642
Short name T123
Test name
Test status
Simulation time 8423954492 ps
CPU time 775.05 seconds
Started Apr 23 03:13:29 PM PDT 24
Finished Apr 23 03:26:24 PM PDT 24
Peak memory 266088 kb
Host smart-3f242407-405f-466c-9ec2-509758cff9e9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060437642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.1060437642
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.3821937822
Short name T292
Test name
Test status
Simulation time 13102870568 ps
CPU time 101.84 seconds
Started Apr 23 03:13:29 PM PDT 24
Finished Apr 23 03:15:11 PM PDT 24
Peak memory 247632 kb
Host smart-9cf03a2a-baf0-49f8-8b0a-82dbf3d509ef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821937822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.3821937822
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.1842243035
Short name T375
Test name
Test status
Simulation time 4550628224 ps
CPU time 68.71 seconds
Started Apr 23 03:13:19 PM PDT 24
Finished Apr 23 03:14:28 PM PDT 24
Peak memory 255728 kb
Host smart-7f6e767c-d544-444c-8fdd-672031cd6f0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18422
43035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.1842243035
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.1534528280
Short name T499
Test name
Test status
Simulation time 63312453 ps
CPU time 7.86 seconds
Started Apr 23 03:13:20 PM PDT 24
Finished Apr 23 03:13:28 PM PDT 24
Peak memory 248276 kb
Host smart-e4da8218-e5f0-4d08-a4e6-b6a6c16b448d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15345
28280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.1534528280
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.1760526281
Short name T677
Test name
Test status
Simulation time 527570419 ps
CPU time 36.65 seconds
Started Apr 23 03:13:23 PM PDT 24
Finished Apr 23 03:14:00 PM PDT 24
Peak memory 248604 kb
Host smart-7dabe4ab-2ace-41c7-8d40-c072241d5c46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17605
26281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.1760526281
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.3515157115
Short name T426
Test name
Test status
Simulation time 4915522723 ps
CPU time 52.05 seconds
Started Apr 23 03:13:15 PM PDT 24
Finished Apr 23 03:14:07 PM PDT 24
Peak memory 248696 kb
Host smart-86c26ec1-64d4-49e5-99cc-199064868418
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35151
57115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.3515157115
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.2525932227
Short name T187
Test name
Test status
Simulation time 82971458251 ps
CPU time 8337.49 seconds
Started Apr 23 03:13:26 PM PDT 24
Finished Apr 23 05:32:25 PM PDT 24
Peak memory 364544 kb
Host smart-e255e87e-4402-4e7f-8870-c999418c0d6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525932227 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.2525932227
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.669124
Short name T124
Test name
Test status
Simulation time 695278228604 ps
CPU time 2282.82 seconds
Started Apr 23 03:13:36 PM PDT 24
Finished Apr 23 03:51:39 PM PDT 24
Peak memory 286940 kb
Host smart-f24248ca-0e9e-4696-b27a-2531610dd30d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.669124
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.2087165098
Short name T46
Test name
Test status
Simulation time 4068477609 ps
CPU time 99.71 seconds
Started Apr 23 03:13:33 PM PDT 24
Finished Apr 23 03:15:13 PM PDT 24
Peak memory 256064 kb
Host smart-6f49fe13-40d6-42d1-9e29-ef53e395af5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20871
65098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.2087165098
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.3622281310
Short name T80
Test name
Test status
Simulation time 145386071640 ps
CPU time 1813.4 seconds
Started Apr 23 03:13:37 PM PDT 24
Finished Apr 23 03:43:51 PM PDT 24
Peak memory 271200 kb
Host smart-80ffdbb7-8f1a-4cd7-85d0-d40afa195164
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622281310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.3622281310
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.2997842818
Short name T501
Test name
Test status
Simulation time 32108653106 ps
CPU time 1924.48 seconds
Started Apr 23 03:13:35 PM PDT 24
Finished Apr 23 03:45:40 PM PDT 24
Peak memory 281436 kb
Host smart-73331096-b70a-452c-b7a3-b8fc6796c07e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997842818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.2997842818
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.1823705456
Short name T660
Test name
Test status
Simulation time 17038349243 ps
CPU time 357.21 seconds
Started Apr 23 03:13:36 PM PDT 24
Finished Apr 23 03:19:34 PM PDT 24
Peak memory 248704 kb
Host smart-60e7f1a1-b8ea-40ac-bfc3-982d5065412c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823705456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.1823705456
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.2045524658
Short name T352
Test name
Test status
Simulation time 1079456568 ps
CPU time 68.81 seconds
Started Apr 23 03:13:27 PM PDT 24
Finished Apr 23 03:14:37 PM PDT 24
Peak memory 248772 kb
Host smart-0b4a06e9-0c54-4e97-999b-3ab1cffcc401
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20455
24658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.2045524658
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.884303016
Short name T265
Test name
Test status
Simulation time 1359063225 ps
CPU time 49.06 seconds
Started Apr 23 03:13:28 PM PDT 24
Finished Apr 23 03:14:17 PM PDT 24
Peak memory 254512 kb
Host smart-3a888b06-7f78-4515-ab8a-dfdc6cc7f706
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88430
3016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.884303016
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.4282845136
Short name T558
Test name
Test status
Simulation time 334985007 ps
CPU time 5.3 seconds
Started Apr 23 03:13:37 PM PDT 24
Finished Apr 23 03:13:42 PM PDT 24
Peak memory 238804 kb
Host smart-521faf55-4c82-48f5-af35-0d1fee73d417
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42828
45136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.4282845136
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.1306516239
Short name T233
Test name
Test status
Simulation time 947119466 ps
CPU time 27.45 seconds
Started Apr 23 03:13:30 PM PDT 24
Finished Apr 23 03:13:58 PM PDT 24
Peak memory 255496 kb
Host smart-34930101-1e02-418e-b57a-ba8e46543c06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13065
16239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.1306516239
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.1143799648
Short name T577
Test name
Test status
Simulation time 37183136430 ps
CPU time 2355.07 seconds
Started Apr 23 03:13:53 PM PDT 24
Finished Apr 23 03:53:08 PM PDT 24
Peak memory 288724 kb
Host smart-89c9f29e-1908-42ab-8276-9ca0d47f8eed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143799648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.1143799648
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.2376848072
Short name T616
Test name
Test status
Simulation time 778291678 ps
CPU time 64.78 seconds
Started Apr 23 03:13:49 PM PDT 24
Finished Apr 23 03:14:54 PM PDT 24
Peak memory 248160 kb
Host smart-47429b51-6a81-4ce0-9694-9697b206822f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23768
48072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.2376848072
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.2690148095
Short name T404
Test name
Test status
Simulation time 2410961899 ps
CPU time 43.85 seconds
Started Apr 23 03:13:47 PM PDT 24
Finished Apr 23 03:14:31 PM PDT 24
Peak memory 249028 kb
Host smart-5a462386-e0b4-487c-a27b-c6c81d20e75a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26901
48095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.2690148095
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.567186473
Short name T308
Test name
Test status
Simulation time 42590624063 ps
CPU time 1219.63 seconds
Started Apr 23 03:13:49 PM PDT 24
Finished Apr 23 03:34:09 PM PDT 24
Peak memory 281440 kb
Host smart-18f9308b-cc56-4808-ba6d-adfcd0f87905
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567186473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.567186473
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.3159139097
Short name T626
Test name
Test status
Simulation time 56225885134 ps
CPU time 767.4 seconds
Started Apr 23 03:13:52 PM PDT 24
Finished Apr 23 03:26:40 PM PDT 24
Peak memory 272440 kb
Host smart-1bd390ad-0678-45c0-bd57-99b513c7c61a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159139097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.3159139097
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.467426092
Short name T284
Test name
Test status
Simulation time 16904192619 ps
CPU time 705.61 seconds
Started Apr 23 03:13:50 PM PDT 24
Finished Apr 23 03:25:36 PM PDT 24
Peak memory 247784 kb
Host smart-1c397d96-65b2-439d-988d-9ac44520b3fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467426092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.467426092
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.3368162655
Short name T488
Test name
Test status
Simulation time 1283678522 ps
CPU time 21.81 seconds
Started Apr 23 03:13:40 PM PDT 24
Finished Apr 23 03:14:02 PM PDT 24
Peak memory 255120 kb
Host smart-ff9354bf-e0b9-45ad-91b6-6a2ad450fec7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33681
62655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.3368162655
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.599389707
Short name T462
Test name
Test status
Simulation time 755487787 ps
CPU time 39.44 seconds
Started Apr 23 03:13:44 PM PDT 24
Finished Apr 23 03:14:24 PM PDT 24
Peak memory 254516 kb
Host smart-59546dca-1e0d-431f-aeab-0328ad4f45e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59938
9707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.599389707
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.2557981833
Short name T26
Test name
Test status
Simulation time 35940828 ps
CPU time 6.27 seconds
Started Apr 23 03:13:45 PM PDT 24
Finished Apr 23 03:13:52 PM PDT 24
Peak memory 238788 kb
Host smart-9a6fea76-c6a3-453a-8592-2b216f74a29c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25579
81833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.2557981833
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.2175654017
Short name T476
Test name
Test status
Simulation time 3403926928 ps
CPU time 56.13 seconds
Started Apr 23 03:13:39 PM PDT 24
Finished Apr 23 03:14:35 PM PDT 24
Peak memory 256028 kb
Host smart-4265f902-b59f-4b16-b499-1043081ee784
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21756
54017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.2175654017
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.1645125629
Short name T191
Test name
Test status
Simulation time 94862297760 ps
CPU time 1249.03 seconds
Started Apr 23 03:13:50 PM PDT 24
Finished Apr 23 03:34:39 PM PDT 24
Peak memory 265068 kb
Host smart-e289dbdc-c652-406d-8d54-bd88c4419a22
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645125629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.1645125629
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.348474637
Short name T217
Test name
Test status
Simulation time 125427908 ps
CPU time 3.11 seconds
Started Apr 23 03:03:50 PM PDT 24
Finished Apr 23 03:03:53 PM PDT 24
Peak memory 248768 kb
Host smart-3c0b5c5c-ea87-4fa1-b09b-35c4997c9046
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=348474637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.348474637
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.1956977200
Short name T416
Test name
Test status
Simulation time 38486454177 ps
CPU time 2153.38 seconds
Started Apr 23 03:03:49 PM PDT 24
Finished Apr 23 03:39:43 PM PDT 24
Peak memory 282204 kb
Host smart-7752e79b-626a-4963-b849-4feeaa983a2a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956977200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.1956977200
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.876708406
Short name T613
Test name
Test status
Simulation time 578582891 ps
CPU time 15.68 seconds
Started Apr 23 03:03:50 PM PDT 24
Finished Apr 23 03:04:06 PM PDT 24
Peak memory 240456 kb
Host smart-974bd1b7-8a08-4ae5-b1d0-8c6605e50bb9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=876708406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.876708406
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.3379962541
Short name T351
Test name
Test status
Simulation time 2341440227 ps
CPU time 44.09 seconds
Started Apr 23 03:03:47 PM PDT 24
Finished Apr 23 03:04:32 PM PDT 24
Peak memory 255976 kb
Host smart-81cdbe63-9f26-440f-8d25-7e6b6bde26e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33799
62541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.3379962541
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.628555945
Short name T538
Test name
Test status
Simulation time 1162348407 ps
CPU time 23.34 seconds
Started Apr 23 03:03:48 PM PDT 24
Finished Apr 23 03:04:12 PM PDT 24
Peak memory 254508 kb
Host smart-4907bb51-1627-45ae-ad4a-999764b6a5ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62855
5945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.628555945
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.3664131938
Short name T327
Test name
Test status
Simulation time 84792594918 ps
CPU time 1351.62 seconds
Started Apr 23 03:03:49 PM PDT 24
Finished Apr 23 03:26:21 PM PDT 24
Peak memory 264828 kb
Host smart-d95b35bb-2f22-4f38-9d4f-0bfe587e867a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664131938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.3664131938
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.424519185
Short name T663
Test name
Test status
Simulation time 16903355738 ps
CPU time 708.97 seconds
Started Apr 23 03:03:49 PM PDT 24
Finished Apr 23 03:15:39 PM PDT 24
Peak memory 266372 kb
Host smart-126883b7-8e59-46a3-b4dc-033cd554fa1a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424519185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.424519185
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.246452412
Short name T533
Test name
Test status
Simulation time 2828038304 ps
CPU time 119.55 seconds
Started Apr 23 03:03:49 PM PDT 24
Finished Apr 23 03:05:50 PM PDT 24
Peak memory 247560 kb
Host smart-837573a1-ecda-45f4-b351-733df1ec0332
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246452412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.246452412
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.3325415380
Short name T229
Test name
Test status
Simulation time 360267882 ps
CPU time 26.73 seconds
Started Apr 23 03:03:25 PM PDT 24
Finished Apr 23 03:03:52 PM PDT 24
Peak memory 248636 kb
Host smart-a868a703-3c0e-4178-b4db-f49b081768a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33254
15380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.3325415380
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.3096376073
Short name T434
Test name
Test status
Simulation time 3117980527 ps
CPU time 42.94 seconds
Started Apr 23 03:03:47 PM PDT 24
Finished Apr 23 03:04:30 PM PDT 24
Peak memory 255220 kb
Host smart-8c7fdb5e-206b-4fa4-97b7-d46765d21ed1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30963
76073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.3096376073
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.2185183618
Short name T483
Test name
Test status
Simulation time 381322243 ps
CPU time 33.66 seconds
Started Apr 23 03:03:33 PM PDT 24
Finished Apr 23 03:04:07 PM PDT 24
Peak memory 255952 kb
Host smart-de19b6c8-34d0-4587-96b0-346b1e5359a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21851
83618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.2185183618
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.2412136129
Short name T531
Test name
Test status
Simulation time 2081469968 ps
CPU time 43 seconds
Started Apr 23 03:03:25 PM PDT 24
Finished Apr 23 03:04:08 PM PDT 24
Peak memory 248604 kb
Host smart-a311eab9-e7cf-4f72-a12c-04a97a727929
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24121
36129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.2412136129
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.756168115
Short name T102
Test name
Test status
Simulation time 185807424 ps
CPU time 4.23 seconds
Started Apr 23 03:03:55 PM PDT 24
Finished Apr 23 03:03:59 PM PDT 24
Peak memory 248728 kb
Host smart-34c9206e-9113-4782-9539-2bda76dc787d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=756168115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.756168115
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.3418457570
Short name T611
Test name
Test status
Simulation time 15301975175 ps
CPU time 1093.19 seconds
Started Apr 23 03:03:48 PM PDT 24
Finished Apr 23 03:22:02 PM PDT 24
Peak memory 265064 kb
Host smart-5625e328-436d-4c2f-90f3-4546dc9d100a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418457570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.3418457570
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.3064045459
Short name T648
Test name
Test status
Simulation time 621424225 ps
CPU time 9.38 seconds
Started Apr 23 03:03:53 PM PDT 24
Finished Apr 23 03:04:02 PM PDT 24
Peak memory 240436 kb
Host smart-f053ed99-c441-47c6-a88a-26067b18665d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3064045459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.3064045459
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.3321886020
Short name T445
Test name
Test status
Simulation time 1463861546 ps
CPU time 54.57 seconds
Started Apr 23 03:03:52 PM PDT 24
Finished Apr 23 03:04:47 PM PDT 24
Peak memory 256288 kb
Host smart-c74bd92a-7a7c-492a-9938-aa71217ff397
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33218
86020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.3321886020
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.1982011851
Short name T407
Test name
Test status
Simulation time 362567454 ps
CPU time 26.37 seconds
Started Apr 23 03:03:51 PM PDT 24
Finished Apr 23 03:04:18 PM PDT 24
Peak memory 254384 kb
Host smart-231a36d1-58c2-42c5-9e8d-e19d3a6e6e2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19820
11851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.1982011851
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.3409068900
Short name T345
Test name
Test status
Simulation time 124051716377 ps
CPU time 1781.99 seconds
Started Apr 23 03:03:53 PM PDT 24
Finished Apr 23 03:33:35 PM PDT 24
Peak memory 273260 kb
Host smart-5a046c84-3790-4fc5-84fc-a5a27084a023
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409068900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.3409068900
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.982623577
Short name T289
Test name
Test status
Simulation time 47557310922 ps
CPU time 368.34 seconds
Started Apr 23 03:03:52 PM PDT 24
Finished Apr 23 03:10:00 PM PDT 24
Peak memory 247648 kb
Host smart-15603338-7483-495a-92a2-fedd7147e2ab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982623577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.982623577
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.3176768181
Short name T71
Test name
Test status
Simulation time 250107637 ps
CPU time 14.39 seconds
Started Apr 23 03:03:52 PM PDT 24
Finished Apr 23 03:04:07 PM PDT 24
Peak memory 248612 kb
Host smart-dd01a6ee-c176-4d82-8346-c6c3aa5f7749
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31767
68181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.3176768181
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.1013529305
Short name T190
Test name
Test status
Simulation time 592726112 ps
CPU time 15.35 seconds
Started Apr 23 03:03:50 PM PDT 24
Finished Apr 23 03:04:06 PM PDT 24
Peak memory 254272 kb
Host smart-0943a253-0e2d-4880-8079-ce4c0c216519
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10135
29305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.1013529305
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.1192069242
Short name T542
Test name
Test status
Simulation time 26126406 ps
CPU time 4.15 seconds
Started Apr 23 03:03:51 PM PDT 24
Finished Apr 23 03:03:55 PM PDT 24
Peak memory 238780 kb
Host smart-8f41ae88-2bfc-4eda-aebd-7d9642b8f98c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11920
69242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.1192069242
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.4246688733
Short name T693
Test name
Test status
Simulation time 2567984466 ps
CPU time 53.87 seconds
Started Apr 23 03:03:52 PM PDT 24
Finished Apr 23 03:04:46 PM PDT 24
Peak memory 248676 kb
Host smart-f0b66711-e23d-4334-9203-f9e8a4e8beee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42466
88733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.4246688733
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.1299721075
Short name T567
Test name
Test status
Simulation time 27588844928 ps
CPU time 1408.72 seconds
Started Apr 23 03:03:51 PM PDT 24
Finished Apr 23 03:27:21 PM PDT 24
Peak memory 285572 kb
Host smart-c5b59862-407e-4ae9-8156-d4623669d249
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299721075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.1299721075
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.360115784
Short name T207
Test name
Test status
Simulation time 79294838 ps
CPU time 4.33 seconds
Started Apr 23 03:03:58 PM PDT 24
Finished Apr 23 03:04:02 PM PDT 24
Peak memory 248788 kb
Host smart-9afeb990-c5c0-4424-a1ab-c4c1f3f8d1f0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=360115784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.360115784
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.2358506479
Short name T399
Test name
Test status
Simulation time 32485442200 ps
CPU time 1870.74 seconds
Started Apr 23 03:03:56 PM PDT 24
Finished Apr 23 03:35:07 PM PDT 24
Peak memory 272472 kb
Host smart-b50a8aa7-dfc1-418f-a17c-d5026720e52d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358506479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.2358506479
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.2392965338
Short name T579
Test name
Test status
Simulation time 759076267 ps
CPU time 10.85 seconds
Started Apr 23 03:03:58 PM PDT 24
Finished Apr 23 03:04:09 PM PDT 24
Peak memory 240420 kb
Host smart-a4dc0316-a65e-4bfd-8c3c-df803b51527e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2392965338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.2392965338
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.1032034324
Short name T497
Test name
Test status
Simulation time 2646801494 ps
CPU time 118.87 seconds
Started Apr 23 03:03:56 PM PDT 24
Finished Apr 23 03:05:55 PM PDT 24
Peak memory 256460 kb
Host smart-503c6cfc-dece-4e9c-b065-f9b8ec331d69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10320
34324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.1032034324
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.1735590466
Short name T389
Test name
Test status
Simulation time 445182379 ps
CPU time 9.35 seconds
Started Apr 23 03:03:54 PM PDT 24
Finished Apr 23 03:04:04 PM PDT 24
Peak memory 250044 kb
Host smart-e8339f51-0ea1-4c06-ae40-bf4f332922f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17355
90466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.1735590466
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.3886720929
Short name T656
Test name
Test status
Simulation time 42675557370 ps
CPU time 804.12 seconds
Started Apr 23 03:03:56 PM PDT 24
Finished Apr 23 03:17:21 PM PDT 24
Peak memory 269144 kb
Host smart-4b11532b-b163-49be-8991-ba4a96c3ecb9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886720929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.3886720929
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.2148512247
Short name T634
Test name
Test status
Simulation time 7988998221 ps
CPU time 899.81 seconds
Started Apr 23 03:03:58 PM PDT 24
Finished Apr 23 03:18:58 PM PDT 24
Peak memory 265064 kb
Host smart-96939595-1575-48ab-9a5d-3c1e9972359b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148512247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.2148512247
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.3400061205
Short name T74
Test name
Test status
Simulation time 3483157920 ps
CPU time 45.61 seconds
Started Apr 23 03:03:49 PM PDT 24
Finished Apr 23 03:04:35 PM PDT 24
Peak memory 248672 kb
Host smart-e075b9bc-caf1-44de-b41d-987fec7e9f22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34000
61205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.3400061205
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.3294868829
Short name T440
Test name
Test status
Simulation time 747413751 ps
CPU time 45.45 seconds
Started Apr 23 03:03:56 PM PDT 24
Finished Apr 23 03:04:41 PM PDT 24
Peak memory 255120 kb
Host smart-5877d3c0-59d5-4f1c-a6e9-0a87e9adc846
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32948
68829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.3294868829
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.3102556884
Short name T97
Test name
Test status
Simulation time 350123310 ps
CPU time 17.1 seconds
Started Apr 23 03:03:49 PM PDT 24
Finished Apr 23 03:04:06 PM PDT 24
Peak memory 254824 kb
Host smart-9ed23a92-985f-4eee-be9b-5823941770b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31025
56884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.3102556884
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.2985912236
Short name T612
Test name
Test status
Simulation time 465071970 ps
CPU time 43.26 seconds
Started Apr 23 03:03:55 PM PDT 24
Finished Apr 23 03:04:38 PM PDT 24
Peak memory 248636 kb
Host smart-33458a0b-9a10-419f-9a35-92255a1ca8d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29859
12236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.2985912236
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.386988976
Short name T79
Test name
Test status
Simulation time 76347708233 ps
CPU time 2155.34 seconds
Started Apr 23 03:03:56 PM PDT 24
Finished Apr 23 03:39:52 PM PDT 24
Peak memory 288984 kb
Host smart-21c705cc-b90e-4e79-b020-cbd47c86fea2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386988976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_hand
ler_stress_all.386988976
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.3680421927
Short name T51
Test name
Test status
Simulation time 66203521145 ps
CPU time 5628.19 seconds
Started Apr 23 03:03:58 PM PDT 24
Finished Apr 23 04:37:47 PM PDT 24
Peak memory 335768 kb
Host smart-ac37452f-0d9a-49b1-8253-dbe5fcdc1d2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680421927 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.3680421927
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.1547177109
Short name T220
Test name
Test status
Simulation time 45378945 ps
CPU time 3.62 seconds
Started Apr 23 03:04:02 PM PDT 24
Finished Apr 23 03:04:06 PM PDT 24
Peak memory 248800 kb
Host smart-804ad3b3-5399-4be2-9abb-6591aba3ccef
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1547177109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.1547177109
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.3303852047
Short name T450
Test name
Test status
Simulation time 41241615603 ps
CPU time 919.93 seconds
Started Apr 23 03:03:59 PM PDT 24
Finished Apr 23 03:19:20 PM PDT 24
Peak memory 271640 kb
Host smart-fcab597b-f4d3-404f-8b4b-aef43addb28b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303852047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.3303852047
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.1725548672
Short name T57
Test name
Test status
Simulation time 355137037 ps
CPU time 13.74 seconds
Started Apr 23 03:04:01 PM PDT 24
Finished Apr 23 03:04:16 PM PDT 24
Peak memory 240416 kb
Host smart-ddaebb36-5ac2-4b23-8600-d5bbdb508cab
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1725548672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.1725548672
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.4124121285
Short name T415
Test name
Test status
Simulation time 11637607080 ps
CPU time 165.1 seconds
Started Apr 23 03:03:56 PM PDT 24
Finished Apr 23 03:06:42 PM PDT 24
Peak memory 256844 kb
Host smart-2a20b836-5bfe-4d8c-9980-5b7c02c49628
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41241
21285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.4124121285
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.1171174550
Short name T527
Test name
Test status
Simulation time 26715617 ps
CPU time 4.32 seconds
Started Apr 23 03:03:55 PM PDT 24
Finished Apr 23 03:04:00 PM PDT 24
Peak memory 238880 kb
Host smart-95178f6f-5cdd-40c0-9d4f-49de96924a86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11711
74550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.1171174550
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.3892374273
Short name T489
Test name
Test status
Simulation time 55968768062 ps
CPU time 1175.86 seconds
Started Apr 23 03:03:59 PM PDT 24
Finished Apr 23 03:23:35 PM PDT 24
Peak memory 288584 kb
Host smart-1e09d688-de89-4510-8d4f-c1c2018c88e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892374273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.3892374273
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.388382945
Short name T460
Test name
Test status
Simulation time 42208021707 ps
CPU time 1044.45 seconds
Started Apr 23 03:03:59 PM PDT 24
Finished Apr 23 03:21:24 PM PDT 24
Peak memory 269488 kb
Host smart-42fac2ab-90ec-4c86-881f-e257469b257c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388382945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.388382945
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.567575069
Short name T299
Test name
Test status
Simulation time 75199370291 ps
CPU time 531.75 seconds
Started Apr 23 03:03:58 PM PDT 24
Finished Apr 23 03:12:50 PM PDT 24
Peak memory 247656 kb
Host smart-2da0fd83-30e9-467c-b995-1abfbfbc1d40
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567575069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.567575069
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.1284123581
Short name T685
Test name
Test status
Simulation time 5952851666 ps
CPU time 78.48 seconds
Started Apr 23 03:03:58 PM PDT 24
Finished Apr 23 03:05:17 PM PDT 24
Peak memory 248692 kb
Host smart-e87d42de-23a1-4a85-b1b1-78df27230bab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12841
23581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.1284123581
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.4245254767
Short name T552
Test name
Test status
Simulation time 1867340319 ps
CPU time 45.48 seconds
Started Apr 23 03:03:58 PM PDT 24
Finished Apr 23 03:04:44 PM PDT 24
Peak memory 246948 kb
Host smart-0766e458-237f-40c5-af2a-e0418cbfd3f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42452
54767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.4245254767
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.3944136026
Short name T413
Test name
Test status
Simulation time 87824883 ps
CPU time 4.16 seconds
Started Apr 23 03:03:57 PM PDT 24
Finished Apr 23 03:04:01 PM PDT 24
Peak memory 238752 kb
Host smart-2d1652ff-486d-405e-9dbd-2d3cc6d69bf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39441
36026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.3944136026
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.3881795278
Short name T427
Test name
Test status
Simulation time 2062806925 ps
CPU time 20.33 seconds
Started Apr 23 03:03:58 PM PDT 24
Finished Apr 23 03:04:19 PM PDT 24
Peak memory 248624 kb
Host smart-21eef524-aca7-444a-9692-28be9212e0ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38817
95278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.3881795278
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.1155572940
Short name T486
Test name
Test status
Simulation time 76201298563 ps
CPU time 1728.09 seconds
Started Apr 23 03:04:02 PM PDT 24
Finished Apr 23 03:32:51 PM PDT 24
Peak memory 297500 kb
Host smart-5145f1cc-93e3-4d0f-b0e9-497499051ec7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155572940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.1155572940
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.2523865278
Short name T213
Test name
Test status
Simulation time 48410078 ps
CPU time 4.8 seconds
Started Apr 23 03:04:27 PM PDT 24
Finished Apr 23 03:04:32 PM PDT 24
Peak memory 248740 kb
Host smart-6fc49c57-78fa-4aa5-b83e-b6692342105e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2523865278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.2523865278
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.512969766
Short name T67
Test name
Test status
Simulation time 149861110695 ps
CPU time 1662.95 seconds
Started Apr 23 03:04:22 PM PDT 24
Finished Apr 23 03:32:06 PM PDT 24
Peak memory 269316 kb
Host smart-9e75a4eb-2b7b-4066-a919-8ca8d4a5480b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512969766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.512969766
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.2242273455
Short name T58
Test name
Test status
Simulation time 644934769 ps
CPU time 10.94 seconds
Started Apr 23 03:04:26 PM PDT 24
Finished Apr 23 03:04:38 PM PDT 24
Peak memory 240400 kb
Host smart-360484bf-f1f9-4e80-b721-dd038fc1cd24
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2242273455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.2242273455
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.3190902616
Short name T526
Test name
Test status
Simulation time 5305994671 ps
CPU time 112.82 seconds
Started Apr 23 03:04:18 PM PDT 24
Finished Apr 23 03:06:11 PM PDT 24
Peak memory 256196 kb
Host smart-e8ae9e8f-aeab-43c5-9227-6089cd8094b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31909
02616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.3190902616
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.3189524941
Short name T653
Test name
Test status
Simulation time 439885209 ps
CPU time 27.59 seconds
Started Apr 23 03:04:16 PM PDT 24
Finished Apr 23 03:04:44 PM PDT 24
Peak memory 253896 kb
Host smart-c7eb5694-cbc2-4beb-9951-bcce52d471a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31895
24941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.3189524941
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.2730845597
Short name T315
Test name
Test status
Simulation time 26684076513 ps
CPU time 1179.65 seconds
Started Apr 23 03:04:24 PM PDT 24
Finished Apr 23 03:24:04 PM PDT 24
Peak memory 288720 kb
Host smart-65e44aae-5265-4e74-8ba4-f2fe31def868
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730845597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.2730845597
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.3566092708
Short name T676
Test name
Test status
Simulation time 22290285639 ps
CPU time 1432.65 seconds
Started Apr 23 03:04:26 PM PDT 24
Finished Apr 23 03:28:20 PM PDT 24
Peak memory 272536 kb
Host smart-8b822dbe-3f5f-42fe-a779-541e9da9ae8e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566092708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.3566092708
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.3113740727
Short name T109
Test name
Test status
Simulation time 3069666636 ps
CPU time 137.6 seconds
Started Apr 23 03:04:21 PM PDT 24
Finished Apr 23 03:06:39 PM PDT 24
Peak memory 247372 kb
Host smart-5d210525-e669-40bc-8550-58e496721408
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113740727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.3113740727
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.3165285207
Short name T506
Test name
Test status
Simulation time 243452027 ps
CPU time 21.48 seconds
Started Apr 23 03:04:17 PM PDT 24
Finished Apr 23 03:04:39 PM PDT 24
Peak memory 248612 kb
Host smart-d963cfde-fcc5-408e-bc10-2160a08803ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31652
85207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.3165285207
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.4042244705
Short name T114
Test name
Test status
Simulation time 375191570 ps
CPU time 32.74 seconds
Started Apr 23 03:04:17 PM PDT 24
Finished Apr 23 03:04:50 PM PDT 24
Peak memory 246668 kb
Host smart-3b48c548-31ed-4387-b2c3-ef0b45bc9aac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40422
44705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.4042244705
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.796080418
Short name T614
Test name
Test status
Simulation time 1688246189 ps
CPU time 35.43 seconds
Started Apr 23 03:04:23 PM PDT 24
Finished Apr 23 03:04:59 PM PDT 24
Peak memory 254280 kb
Host smart-51aff425-f08c-4410-b58a-2c7ade92173b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79608
0418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.796080418
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.488601310
Short name T661
Test name
Test status
Simulation time 1139541176 ps
CPU time 27.1 seconds
Started Apr 23 03:04:12 PM PDT 24
Finished Apr 23 03:04:39 PM PDT 24
Peak memory 248704 kb
Host smart-e5fe9817-23ec-48af-9a43-0c33adb6025a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48860
1310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.488601310
Directory /workspace/9.alert_handler_smoke/latest
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