Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	77258	1			T3	21		T4	4258		T24	4354
class_i[0x1]	64644	1			T3	359		T4	437		T9	4
class_i[0x2]	70108	1			T1	763		T3	552		T4	105
class_i[0x3]	83791	1			T4	848		T5	7		T15	9

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	76595	1			T1	681		T3	69		T4	2016
alert[0x1]	74320	1			T1	30		T3	624		T4	1098
alert[0x2]	70281	1			T1	27		T3	143		T4	1109
alert[0x3]	74605	1			T1	25		T3	96		T4	1425

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

295486

1

T1

763

T3

932

T4

5648

esc_ping_fail

315

1

T5

7

T16

7

T33

1

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	76507	1			T1	681		T3	69		T4	2016
esc_integrity_fail	alert[0x1]	74240	1			T1	30		T3	624		T4	1098
esc_integrity_fail	alert[0x2]	70198	1			T1	27		T3	143		T4	1109
esc_integrity_fail	alert[0x3]	74541	1			T1	25		T3	96		T4	1425
esc_ping_fail	alert[0x0]	88	1			T5	2		T16	1		T212	3
esc_ping_fail	alert[0x1]	80	1			T5	2		T16	4		T212	1
esc_ping_fail	alert[0x2]	83	1			T5	2		T16	2		T33	1
esc_ping_fail	alert[0x3]	64	1			T5	1		T212	1		T76	2

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	77189	1			T3	21		T4	4258		T24	4354
esc_integrity_fail	class_i[0x1]	64559	1			T3	359		T4	437		T9	4
esc_integrity_fail	class_i[0x2]	70020	1			T1	763		T3	552		T4	105
esc_integrity_fail	class_i[0x3]	83718	1			T4	848		T15	9		T24	4511
esc_ping_fail	class_i[0x0]	69	1			T16	7		T33	1		T212	4
esc_ping_fail	class_i[0x1]	85	1			T119	1		T281	3		T287	4
esc_ping_fail	class_i[0x2]	88	1			T76	9		T47	4		T285	10
esc_ping_fail	class_i[0x3]	73	1			T5	7		T212	1		T47	6