Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	704783609	0	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	704783609	0	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	704783609	0	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	704783609	0	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	704783609	0	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	704783609	0	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	704783609	0	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	704783609	0	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	704783609	0	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	704783609	0	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	704783609	0	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	704783609	0	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	704783609	0	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	704783609	0	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	704783609	0	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	704783609	0	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	704783609	0	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	704783609	0	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	704783609	0	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	704783609	0	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	704783609	0	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	704783609	0	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	704783609	0	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	704783609	0	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	704783609	0	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	704783609	0	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	704783609	0	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	704783609	0	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	704783609	0	0	0
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	704783609	0	0	622
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	704783609	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	704783609	704712947	0	0
tb.dut.CheckAccuCntDw	0	0	622	622	0	0
tb.dut.CheckEscCntDw	0	0	622	622	0	0
tb.dut.CheckNAlerts	0	0	622	622	0	0
tb.dut.CheckNClasses	0	0	622	622	0	0
tb.dut.CheckNEscSev	0	0	622	622	0	0
tb.dut.CrashdumpKnownO_A	0	0	704783609	704712947	0	0
tb.dut.EdnKnownO_A	0	0	704783609	704712947	0	0
tb.dut.EscPKnownO_A	0	0	704783609	704712947	0	0
tb.dut.IrqAKnownO_A	0	0	704783609	704712947	0	0
tb.dut.IrqBKnownO_A	0	0	704783609	704712947	0	0
tb.dut.IrqCKnownO_A	0	0	704783609	704712947	0	0
tb.dut.IrqDKnownO_A	0	0	704783609	704712947	0	0
tb.dut.TlAReadyKnownO_A	0	0	704783609	704712947	0	0
tb.dut.TlDValidKnownO_A	0	0	704783609	704712947	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	726655888	3460420	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	726655888	11531	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	726655888	12858	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	726655888	12423	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	726655888	11331	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	726655888	10162	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	726655888	10135	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	726655888	12648	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	726655888	9926	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	726655888	10006	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	726655888	11347	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	726655888	10089	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	726655888	11432	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	726655888	10228	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	726655888	11284	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	726655888	11328	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	726655888	10988	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	726655888	12532	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	726655888	10149	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	726655888	10270	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	726655888	10428	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	726655888	10132	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	726655888	11360	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	726655888	11265	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	726655888	11181	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	726655888	10273	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	726655888	11372	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	726655888	10256	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	726655888	11165	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	726655888	10020	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	726655888	12321	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	726655888	12385	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	726655888	11443	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	726655888	10163	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	726655888	11589	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	726655888	10261	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	726655888	10098	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	726655888	10437	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	726655888	12364	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	726655888	10237	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	726655888	11329	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	726655888	10298	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	726655888	11481	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	726655888	10351	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	726655888	12554	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	726655888	11344	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	726655888	10251	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	726655888	11463	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	726655888	11519	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	726655888	11039	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	726655888	11251	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	726655888	11233	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	726655888	10249	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	726655888	10293	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	726655888	10380	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	726655888	11229	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	726655888	10342	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	726655888	10127	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	726655888	11787	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	726655888	11641	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	726655888	11682	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	726655888	10233	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	726655888	10265	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	726655888	10504	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	726655888	11307	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	726655888	11284	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	726655888	11470	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	726655888	10533	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	726655888	11373	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	726655888	11429	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	726655888	17267	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	726655888	10202	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	726655888	10267	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	726655888	10359	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	726655888	10261	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	726655888	10516	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	726655888	10266	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	726655888	11046	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	726655888	11057	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	704783609	1225	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	704783609	251587	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	704783609	341380742	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	704783609	867	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	704783609	45	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	704783609	425	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	704783609	237215565	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	704783609	960	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	704783609	936	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	704783609	914	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	704783609	890	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	704783609	1326	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	704783609	161440	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	704783609	1204	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	704783609	77	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	704783609	704712947	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	622	622	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	704783609	704712947	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	704783609	7272	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	704783609	186018	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	704783609	410272155	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	704783609	488	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	704783609	33	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	704783609	221	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	704783609	291374426	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	704783609	566	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	704783609	550	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	704783609	536	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	704783609	529	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	704783609	1634	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	704783609	200036	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	704783609	1541	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	704783609	58	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	704783609	704712947	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	622	622	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	704783609	704712947	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	704783609	3688	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	704783609	220944	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	704783609	389920228	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	704783609	494	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	704783609	31	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	704783609	231	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	704783609	296171324	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	704783609	562	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	704783609	552	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	704783609	536	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	704783609	523	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	704783609	1579	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	704783609	211494	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	704783609	1491	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	704783609	55	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	704783609	704712947	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	622	622	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	704783609	704712947	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	704783609	2042	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	704783609	183310	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	704783609	392767792	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	704783609	426	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	704783609	16	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	704783609	156	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	704783609	317884624	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	704783609	496	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	704783609	491	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	704783609	488	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	704783609	481	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	704783609	3005	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	704783609	343685	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	704783609	2927	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	704783609	59	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	704783609	704712947	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	622	622	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	704783609	704712947	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	726655888	135635769	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	726655888	726123000	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	726655888	726123000	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	726655888	191362634	0	0
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