Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.61	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	2	42	95.45

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	2	42	95.45	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	180	1			T1	1		T3	3		T4	3
index[0x1]	142	1			T4	2		T9	2		T16	1
index[0x2]	152	1			T1	1		T3	5		T9	2
index[0x3]	157	1			T3	1		T16	1		T78	1

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	221	1			T1	1		T3	2		T4	2
lens_less_than_1000[1]	126	1			T4	1		T9	3		T16	1
lens_less_than_1000[2]	80	1			T1	1		T4	1		T9	1
lens_less_than_1000[3]	67	1			T3	2		T9	1		T50	1
lens_less_than_1000[4]	46	1			T3	1		T78	1		T112	1
lens_less_than_1000[5]	36	1			T3	1		T4	1		T77	1
lens_less_than_1000[6]	18	1			T3	1		T9	1		T20	1
lens_less_than_1000[7]	21	1			T3	2		T11	1		T78	1
lens_less_than_1000[8]	7	1			T16	1		T186	2		T64	1
lens_less_than_1000[9]	3	1			T46	1		T254	1		T255	1
len_2	6	1			T30	1		T256	1		T257	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	2	42	95.45	2

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x0]]	[lens_less_than_1000[8]]	0	1	1
[index[0x3]]	[lens_less_than_1000[9]]	0	1	1

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	66	1			T1	1		T4	1		T211	1
index[0x0]	lens_less_than_1000[1]	35	1			T4	1		T9	2		T11	3
index[0x0]	lens_less_than_1000[2]	15	1			T4	1		T13	1		T45	1
index[0x0]	lens_less_than_1000[3]	25	1			T50	1		T75	1		T19	1
index[0x0]	lens_less_than_1000[4]	7	1			T112	1		T62	1		T258	1
index[0x0]	lens_less_than_1000[5]	13	1			T49	1		T60	1		T30	1
index[0x0]	lens_less_than_1000[6]	5	1			T3	1		T9	1		T232	1
index[0x0]	lens_less_than_1000[7]	12	1			T3	2		T11	1		T78	1
index[0x0]	lens_less_than_1000[9]	1	1			T46	1		-	-		-	-
index[0x0]	len_2	1	1			T30	1		-	-		-	-
index[0x1]	lens_less_than_1000[0]	46	1			T4	1		T9	1		T74	1
index[0x1]	lens_less_than_1000[1]	27	1			T9	1		T75	1		T19	1
index[0x1]	lens_less_than_1000[2]	23	1			T16	1		T20	1		T55	1
index[0x1]	lens_less_than_1000[3]	16	1			T60	1		T259	1		T103	1
index[0x1]	lens_less_than_1000[4]	12	1			T78	1		T260	1		T261	1
index[0x1]	lens_less_than_1000[5]	11	1			T4	1		T77	1		T103	2
index[0x1]	lens_less_than_1000[6]	2	1			T262	1		T263	1		-	-
index[0x1]	lens_less_than_1000[7]	1	1			T238	1		-	-		-	-
index[0x1]	lens_less_than_1000[8]	2	1			T64	1		T264	1		-	-
index[0x1]	lens_less_than_1000[9]	1	1			T254	1		-	-		-	-
index[0x1]	len_2	1	1			T265	1		-	-		-	-
index[0x2]	lens_less_than_1000[0]	52	1			T3	1		T212	1		T78	1
index[0x2]	lens_less_than_1000[1]	21	1			T43	1		T17	1		T266	1
index[0x2]	lens_less_than_1000[2]	23	1			T1	1		T9	1		T10	1
index[0x2]	lens_less_than_1000[3]	19	1			T3	2		T9	1		T59	1
index[0x2]	lens_less_than_1000[4]	16	1			T3	1		T20	1		T84	1
index[0x2]	lens_less_than_1000[5]	6	1			T3	1		T62	1		T239	1
index[0x2]	lens_less_than_1000[6]	6	1			T20	1		T62	1		T105	1
index[0x2]	lens_less_than_1000[7]	3	1			T40	1		T267	1		T246	1
index[0x2]	lens_less_than_1000[8]	4	1			T16	1		T186	1		T240	1
index[0x2]	lens_less_than_1000[9]	1	1			T255	1		-	-		-	-
index[0x2]	len_2	1	1			T268	1		-	-		-	-
index[0x3]	lens_less_than_1000[0]	57	1			T3	1		T78	1		T48	1
index[0x3]	lens_less_than_1000[1]	43	1			T16	1		T20	1		T45	2
index[0x3]	lens_less_than_1000[2]	19	1			T57	1		T62	1		T269	1
index[0x3]	lens_less_than_1000[3]	7	1			T55	1		T270	1		T30	1
index[0x3]	lens_less_than_1000[4]	11	1			T271	1		T272	1		T120	1
index[0x3]	lens_less_than_1000[5]	6	1			T20	1		T273	2		T274	1
index[0x3]	lens_less_than_1000[6]	5	1			T21	1		T60	1		T275	1
index[0x3]	lens_less_than_1000[7]	5	1			T61	1		T276	1		T30	1
index[0x3]	lens_less_than_1000[8]	1	1			T186	1		-	-		-	-
index[0x3]	len_2	3	1			T256	1		T257	1		T277	1