Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.59	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	4	36	90.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	4	36	90.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	77	1			T3	3		T24	1		T78	1
class_index[0x1]	58	1			T3	2		T78	4		T48	1
class_index[0x2]	55	1			T3	2		T4	2		T19	1
class_index[0x3]	59	1			T3	2		T4	1		T24	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	74	1			T4	2		T24	2		T48	1
intr_timeout_cnt[1]	74	1			T3	2		T78	4		T40	1
intr_timeout_cnt[2]	28	1			T3	3		T55	1		T30	1
intr_timeout_cnt[3]	9	1			T3	2		T109	1		T83	1
intr_timeout_cnt[4]	19	1			T3	1		T4	1		T19	2
intr_timeout_cnt[5]	6	1			T55	1		T30	1		T42	1
intr_timeout_cnt[6]	21	1			T3	1		T55	1		T116	1
intr_timeout_cnt[7]	6	1			T78	1		T55	1		T230	1
intr_timeout_cnt[8]	7	1			T83	1		T231	1		T232	1
intr_timeout_cnt[9]	5	1			T13	1		T233	1		T30	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	4	36	90.00	4

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[9]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[5]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[8]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[7]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	34	1			T24	1		T84	1		T45	1
class_index[0x0]	intr_timeout_cnt[1]	11	1			T62	1		T41	1		T89	1
class_index[0x0]	intr_timeout_cnt[2]	8	1			T3	2		T103	1		T234	1
class_index[0x0]	intr_timeout_cnt[3]	3	1			T3	1		T83	1		T235	1
class_index[0x0]	intr_timeout_cnt[4]	6	1			T236	2		T237	3		T238	1
class_index[0x0]	intr_timeout_cnt[5]	4	1			T55	1		T30	1		T239	1
class_index[0x0]	intr_timeout_cnt[6]	6	1			T123	1		T240	1		T231	1
class_index[0x0]	intr_timeout_cnt[7]	2	1			T78	1		T241	1		-	-
class_index[0x0]	intr_timeout_cnt[8]	3	1			T242	3		-	-		-	-
class_index[0x1]	intr_timeout_cnt[0]	11	1			T48	1		T83	1		T85	1
class_index[0x1]	intr_timeout_cnt[1]	21	1			T3	1		T78	4		T83	2
class_index[0x1]	intr_timeout_cnt[2]	12	1			T3	1		T55	1		T30	1
class_index[0x1]	intr_timeout_cnt[3]	2	1			T243	1		T244	1		-	-
class_index[0x1]	intr_timeout_cnt[4]	3	1			T19	1		T30	1		T245	1
class_index[0x1]	intr_timeout_cnt[6]	6	1			T233	1		T232	1		T246	1
class_index[0x1]	intr_timeout_cnt[7]	2	1			T230	1		T247	1		-	-
class_index[0x1]	intr_timeout_cnt[9]	1	1			T233	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	11	1			T4	1		T59	1		T88	1
class_index[0x2]	intr_timeout_cnt[1]	22	1			T3	1		T60	1		T65	1
class_index[0x2]	intr_timeout_cnt[2]	3	1			T248	1		T249	1		T250	1
class_index[0x2]	intr_timeout_cnt[3]	2	1			T30	1		T243	1		-	-
class_index[0x2]	intr_timeout_cnt[4]	5	1			T3	1		T4	1		T19	1
class_index[0x2]	intr_timeout_cnt[5]	1	1			T42	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[6]	6	1			T26	3		T120	1		T98	1
class_index[0x2]	intr_timeout_cnt[7]	2	1			T55	1		T251	1		-	-
class_index[0x2]	intr_timeout_cnt[8]	2	1			T231	1		T232	1		-	-
class_index[0x2]	intr_timeout_cnt[9]	1	1			T252	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	18	1			T4	1		T24	1		T20	2
class_index[0x3]	intr_timeout_cnt[1]	20	1			T40	1		T215	1		T60	1
class_index[0x3]	intr_timeout_cnt[2]	5	1			T240	2		T42	1		T252	1
class_index[0x3]	intr_timeout_cnt[3]	2	1			T3	1		T109	1		-	-
class_index[0x3]	intr_timeout_cnt[4]	5	1			T26	1		T123	1		T108	1
class_index[0x3]	intr_timeout_cnt[5]	1	1			T242	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[6]	3	1			T3	1		T55	1		T116	1
class_index[0x3]	intr_timeout_cnt[8]	2	1			T83	1		T252	1		-	-
class_index[0x3]	intr_timeout_cnt[9]	3	1			T13	1		T30	1		T253	1