Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	353214	1			T1	20		T3	1476		T4	1876
all_values[1]	353214	1			T1	20		T3	1476		T4	1876
all_values[2]	353214	1			T1	20		T3	1476		T4	1876
all_values[3]	353214	1			T1	20		T3	1476		T4	1876

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

702934

1

T1

47

T3

2864

T4

3650

auto[1]

709922

1

T1

33

T3

3040

T4

3854

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

836121

1

T1

12

T3

3124

T4

3900

auto[1]

576735

1

T1

68

T3

2780

T4

3604

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	99575	1			T1	1		T3	362		T4	450
all_values[0]	auto[0]	auto[1]	76494	1			T1	8		T3	343		T4	446
all_values[0]	auto[1]	auto[0]	100579	1			T1	2		T3	395		T4	487
all_values[0]	auto[1]	auto[1]	76566	1			T1	9		T3	376		T4	493
all_values[1]	auto[0]	auto[0]	106217	1			T1	4		T3	370		T4	489
all_values[1]	auto[0]	auto[1]	69207	1			T1	9		T3	323		T4	467
all_values[1]	auto[1]	auto[0]	107849	1			T1	1		T3	415		T4	471
all_values[1]	auto[1]	auto[1]	69941	1			T1	6		T3	368		T4	449
all_values[2]	auto[0]	auto[0]	105117	1			T1	1		T3	391		T4	457
all_values[2]	auto[0]	auto[1]	70576	1			T1	11		T3	349		T4	442
all_values[2]	auto[1]	auto[0]	106619	1			T3	398		T4	489		T5	43
all_values[2]	auto[1]	auto[1]	70902	1			T1	8		T3	338		T4	488
all_values[3]	auto[0]	auto[0]	104266	1			T1	1		T3	391		T4	514
all_values[3]	auto[0]	auto[1]	71482	1			T1	12		T3	335		T4	385
all_values[3]	auto[1]	auto[0]	105899	1			T1	2		T3	402		T4	543
all_values[3]	auto[1]	auto[1]	71567	1			T1	5		T3	348		T4	434