Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	353214	1			T1	20		T3	1476		T4	1876
all_pins[1]	353214	1			T1	20		T3	1476		T4	1876
all_pins[2]	353214	1			T1	20		T3	1476		T4	1876
all_pins[3]	353214	1			T1	20		T3	1476		T4	1876

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1123880	1			T1	52		T3	4474		T4	5640
values[0x1]	288976	1			T1	28		T3	1430		T4	1864
transitions[0x0=>0x1]	192666	1			T1	18		T3	901		T4	1152
transitions[0x1=>0x0]	192949	1			T1	19		T3	901		T4	1153

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	276648	1			T1	11		T3	1100		T4	1383
all_pins[0]	values[0x1]	76566	1			T1	9		T3	376		T4	493
all_pins[0]	transitions[0x0=>0x1]	75943	1			T1	7		T3	375		T4	488
all_pins[0]	transitions[0x1=>0x0]	71227	1			T1	4		T3	347		T4	430
all_pins[1]	values[0x0]	283273	1			T1	14		T3	1108		T4	1427
all_pins[1]	values[0x1]	69941	1			T1	6		T3	368		T4	449
all_pins[1]	transitions[0x0=>0x1]	38057	1			T1	3		T3	178		T4	216
all_pins[1]	transitions[0x1=>0x0]	44682	1			T1	6		T3	186		T4	260
all_pins[2]	values[0x0]	282312	1			T1	12		T3	1138		T4	1388
all_pins[2]	values[0x1]	70902	1			T1	8		T3	338		T4	488
all_pins[2]	transitions[0x0=>0x1]	39199	1			T1	5		T3	166		T4	248
all_pins[2]	transitions[0x1=>0x0]	38238	1			T1	3		T3	196		T4	209
all_pins[3]	values[0x0]	281647	1			T1	15		T3	1128		T4	1442
all_pins[3]	values[0x1]	71567	1			T1	5		T3	348		T4	434
all_pins[3]	transitions[0x0=>0x1]	39467	1			T1	3		T3	182		T4	200
all_pins[3]	transitions[0x1=>0x0]	38802	1			T1	6		T3	172		T4	254