Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv



Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 24 0 24 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 4 0 4 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 24 0 24 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 278 1 T166 4 T167 7 T168 7
all_values[1] 278 1 T166 4 T167 7 T168 7
all_values[2] 278 1 T166 4 T167 7 T168 7
all_values[3] 278 1 T166 4 T167 7 T168 7



Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 620 1 T166 11 T167 15 T168 16
auto[1] 492 1 T166 5 T167 13 T168 12



Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 441 1 T166 3 T167 8 T168 13
auto[1] 671 1 T166 13 T167 20 T168 15



Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 655 1 T166 8 T167 14 T168 18
auto[1] 457 1 T166 8 T167 14 T168 10



Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 24 0 24 100.00
Automatically Generated Cross Bins 24 0 24 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 63 1 T168 1 T225 1 T321 1
all_values[0] auto[0] auto[0] auto[1] 28 1 T167 2 T168 1 T321 1
all_values[0] auto[0] auto[1] auto[0] 46 1 T167 1 T168 1 T321 2
all_values[0] auto[0] auto[1] auto[1] 23 1 T166 1 T167 1 T322 1
all_values[0] auto[1] auto[0] auto[1] 69 1 T166 2 T168 2 T225 3
all_values[0] auto[1] auto[1] auto[1] 49 1 T166 1 T167 3 T168 2
all_values[1] auto[0] auto[0] auto[0] 54 1 T166 2 T167 1 T168 4
all_values[1] auto[0] auto[0] auto[1] 35 1 T166 1 T167 1 T321 1
all_values[1] auto[0] auto[1] auto[0] 56 1 T167 1 T168 3 T225 3
all_values[1] auto[0] auto[1] auto[1] 20 1 T321 1 T323 1 T324 1
all_values[1] auto[1] auto[0] auto[1] 66 1 T166 1 T167 3 T225 1
all_values[1] auto[1] auto[1] auto[1] 47 1 T167 1 T321 1 T323 2
all_values[2] auto[0] auto[0] auto[0] 57 1 T166 1 T168 2 T225 2
all_values[2] auto[0] auto[0] auto[1] 24 1 T167 2 T168 1 T321 2
all_values[2] auto[0] auto[1] auto[0] 40 1 T167 2 T321 1 T325 2
all_values[2] auto[0] auto[1] auto[1] 40 1 T166 2 T168 1 T323 1
all_values[2] auto[1] auto[0] auto[1] 66 1 T166 1 T167 2 T168 2
all_values[2] auto[1] auto[1] auto[1] 51 1 T167 1 T168 1 T225 1
all_values[3] auto[0] auto[0] auto[0] 73 1 T168 2 T323 1 T325 3
all_values[3] auto[0] auto[0] auto[1] 23 1 T166 1 T225 2 T321 2
all_values[3] auto[0] auto[1] auto[0] 52 1 T167 3 T321 1 T323 1
all_values[3] auto[0] auto[1] auto[1] 21 1 T168 2 T321 2 T323 2
all_values[3] auto[1] auto[0] auto[1] 62 1 T166 2 T167 4 T168 1
all_values[3] auto[1] auto[1] auto[1] 47 1 T166 1 T168 2 T323 2


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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