Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	90687	1			T4	737		T15	584		T24	197
accum_cnt_1000	227881	1			T1	24		T3	1036		T4	3003
accum_cnt_100	25907	1			T3	357		T4	259		T9	145
accum_cnt_50	75939	1			T1	18		T3	373		T4	344
accum_cnt_10	196994	1			T1	39		T3	817		T4	537
accum_cnt_0	375054	1			T1	35		T3	1673		T4	637

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	261152	1			T1	29		T3	1064		T4	1419
class_index[0x1]	261152	1			T1	29		T3	1064		T4	1419
class_index[0x2]	261152	1			T1	29		T3	1064		T4	1419
class_index[0x3]	261152	1			T1	29		T3	1064		T4	1419

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	22072	1			T4	467		T24	197		T40	525
class_index[0x0]	accum_cnt_1000	65073	1			T3	248		T4	653		T9	114
class_index[0x0]	accum_cnt_100	8520	1			T3	132		T4	47		T9	28
class_index[0x0]	accum_cnt_50	19468	1			T3	135		T4	71		T9	45
class_index[0x0]	accum_cnt_10	52908	1			T1	25		T3	73		T4	73
class_index[0x0]	accum_cnt_0	78668	1			T1	4		T3	476		T4	108
class_index[0x1]	accum_cnt_2000	22917	1			T4	24		T39	245		T40	468
class_index[0x1]	accum_cnt_1000	52555	1			T3	437		T4	1037		T9	107
class_index[0x1]	accum_cnt_100	5945	1			T3	32		T4	80		T9	28
class_index[0x1]	accum_cnt_50	20776	1			T3	47		T4	103		T9	40
class_index[0x1]	accum_cnt_10	52328	1			T1	2		T3	278		T4	67
class_index[0x1]	accum_cnt_0	94530	1			T1	27		T3	270		T4	108
class_index[0x2]	accum_cnt_2000	23811	1			T4	246		T15	584		T13	213
class_index[0x2]	accum_cnt_1000	51239	1			T1	24		T3	233		T4	519
class_index[0x2]	accum_cnt_100	5507	1			T3	106		T4	40		T9	34
class_index[0x2]	accum_cnt_50	17154	1			T3	110		T4	87		T9	26
class_index[0x2]	accum_cnt_10	52206	1			T1	1		T3	425		T4	95
class_index[0x2]	accum_cnt_0	96279	1			T1	4		T3	190		T4	273
class_index[0x3]	accum_cnt_2000	21887	1			T13	166		T77	566		T73	244
class_index[0x3]	accum_cnt_1000	59014	1			T3	118		T4	794		T9	51
class_index[0x3]	accum_cnt_100	5935	1			T3	87		T4	92		T9	55
class_index[0x3]	accum_cnt_50	18541	1			T1	18		T3	81		T4	83
class_index[0x3]	accum_cnt_10	39552	1			T1	11		T3	41		T4	302
class_index[0x3]	accum_cnt_0	105577	1			T3	737		T4	148		T5	12