Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	8305	1			T3	33		T5	3		T24	1743
alert[0x1]	7560	1			T13	199		T212	1		T39	236
alert[0x2]	6189	1			T3	2		T4	359		T24	33
alert[0x3]	5670	1			T3	4		T4	194		T16	1
alert[0x4]	19195	1			T4	403		T5	1		T76	2
alert[0x5]	5482	1			T53	1		T13	18		T73	12
alert[0x6]	9687	1			T3	247		T24	800		T16	1
alert[0x7]	7682	1			T53	1		T13	67		T78	7
alert[0x8]	9502	1			T24	6		T33	1		T13	111
alert[0x9]	15032	1			T3	42		T5	1		T40	137
alert[0xa]	6173	1			T16	1		T13	342		T39	27
alert[0xb]	4300	1			T4	7		T24	34		T16	1
alert[0xc]	11613	1			T3	14		T4	5		T18	1
alert[0xd]	8895	1			T4	154		T24	1100		T16	1
alert[0xe]	11889	1			T3	172		T4	887		T16	2
alert[0xf]	7329	1			T4	29		T5	1		T24	21
alert[0x10]	10592	1			T4	10		T24	18		T33	1
alert[0x11]	7864	1			T4	114		T16	1		T76	1
alert[0x12]	10694	1			T24	3900		T13	287		T78	1
alert[0x13]	3177	1			T5	1		T24	34		T16	1
alert[0x14]	4330	1			T4	37		T5	1		T33	1
alert[0x15]	3784	1			T3	144		T37	1		T24	23
alert[0x16]	4665	1			T3	1		T13	17		T40	57
alert[0x17]	6972	1			T4	11		T39	841		T40	105
alert[0x18]	10336	1			T4	21		T24	720		T16	1
alert[0x19]	15314	1			T3	10		T4	5		T24	84
alert[0x1a]	11320	1			T4	78		T13	458		T40	3
alert[0x1b]	6713	1			T4	7		T39	28		T40	231
alert[0x1c]	7871	1			T78	9		T40	116		T113	136
alert[0x1d]	12682	1			T3	16		T4	16		T33	1
alert[0x1e]	6598	1			T13	39		T76	2		T78	19
alert[0x1f]	5659	1			T16	1		T13	1145		T78	58
alert[0x20]	12111	1			T4	28		T5	1		T24	40
alert[0x21]	4407	1			T18	8		T13	92		T212	1
alert[0x22]	11210	1			T3	29		T5	1		T24	1283
alert[0x23]	7196	1			T4	455		T5	1		T24	16
alert[0x24]	9615	1			T4	63		T34	2		T212	1
alert[0x25]	17717	1			T4	53		T24	1465		T34	13
alert[0x26]	3374	1			T3	27		T4	46		T5	1
alert[0x27]	7285	1			T4	23		T13	215		T78	280
alert[0x28]	4456	1			T4	108		T24	37		T16	1
alert[0x29]	4219	1			T4	4		T76	1		T39	269
alert[0x2a]	8453	1			T3	135		T4	319		T13	23
alert[0x2b]	10279	1			T4	5		T24	1738		T13	3
alert[0x2c]	11610	1			T24	34		T28	9		T83	1
alert[0x2d]	15856	1			T4	19		T40	170		T113	1689
alert[0x2e]	5784	1			T3	118		T24	140		T211	1
alert[0x2f]	8589	1			T4	51		T24	5		T13	70
alert[0x30]	4825	1			T3	3		T4	308		T24	1235
alert[0x31]	9939	1			T3	1		T13	202		T28	479
alert[0x32]	8777	1			T3	38		T4	13		T5	1
alert[0x33]	9974	1			T3	7		T13	366		T47	1
alert[0x34]	5867	1			T4	194		T24	47		T16	1
alert[0x35]	10554	1			T4	10		T24	18		T212	1
alert[0x36]	10708	1			T3	69		T16	1		T34	1
alert[0x37]	12052	1			T212	1		T19	1		T73	104
alert[0x38]	12790	1			T13	324		T212	1		T39	1234
alert[0x39]	11844	1			T4	9		T16	1		T76	1
alert[0x3a]	4060	1			T3	1		T16	1		T13	142
alert[0x3b]	14119	1			T24	61		T212	1		T76	1
alert[0x3c]	2598	1			T4	74		T24	717		T16	1
alert[0x3d]	6245	1			T4	21		T76	1		T78	16
alert[0x3e]	14344	1			T4	48		T16	1		T76	1
alert[0x3f]	5766	1			T4	230		T24	426		T13	20
alert[0x40]	5940	1			T4	35		T5	1		T24	50

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	173908	1			T3	372		T24	8907		T18	3
class_i[0x1]	77612	1			T3	352		T5	13		T18	5
class_i[0x2]	160217	1			T3	377		T4	4453		T15	4
class_i[0x3]	153900	1			T3	12		T5	1		T37	1

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

564904

1

T3

1113

T4

4453

T15

4

alert_ping_fail

733

1

T5

14

T37

1

T53

2

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	8295	1			T3	33		T24	1743		T18	2
alert_integrity_fail	alert[0x1]	7546	1			T13	199		T39	236		T113	33
alert_integrity_fail	alert[0x2]	6183	1			T3	2		T4	359		T24	33
alert_integrity_fail	alert[0x3]	5661	1			T3	4		T4	194		T78	9
alert_integrity_fail	alert[0x4]	19181	1			T4	403		T40	17		T20	12
alert_integrity_fail	alert[0x5]	5469	1			T13	18		T73	12		T62	1770
alert_integrity_fail	alert[0x6]	9679	1			T3	247		T24	800		T40	100
alert_integrity_fail	alert[0x7]	7669	1			T13	67		T78	7		T20	76
alert_integrity_fail	alert[0x8]	9486	1			T24	6		T13	111		T64	167
alert_integrity_fail	alert[0x9]	15016	1			T3	42		T40	137		T73	69
alert_integrity_fail	alert[0xa]	6161	1			T13	342		T39	27		T40	24
alert_integrity_fail	alert[0xb]	4289	1			T4	7		T24	34		T13	45
alert_integrity_fail	alert[0xc]	11598	1			T3	14		T4	5		T18	1
alert_integrity_fail	alert[0xd]	8883	1			T4	154		T24	1100		T13	468
alert_integrity_fail	alert[0xe]	11877	1			T3	172		T4	887		T78	3
alert_integrity_fail	alert[0xf]	7316	1			T4	29		T24	21		T13	31
alert_integrity_fail	alert[0x10]	10578	1			T4	10		T24	18		T39	46
alert_integrity_fail	alert[0x11]	7852	1			T4	114		T78	2		T39	36
alert_integrity_fail	alert[0x12]	10686	1			T24	3900		T13	287		T78	1
alert_integrity_fail	alert[0x13]	3158	1			T24	34		T78	2		T39	106
alert_integrity_fail	alert[0x14]	4315	1			T4	37		T13	56		T78	746
alert_integrity_fail	alert[0x15]	3774	1			T3	144		T24	23		T78	5
alert_integrity_fail	alert[0x16]	4651	1			T3	1		T13	17		T40	57
alert_integrity_fail	alert[0x17]	6965	1			T4	11		T39	841		T40	105
alert_integrity_fail	alert[0x18]	10327	1			T4	21		T24	720		T34	1
alert_integrity_fail	alert[0x19]	15303	1			T3	10		T4	5		T24	84
alert_integrity_fail	alert[0x1a]	11313	1			T4	78		T13	458		T40	3
alert_integrity_fail	alert[0x1b]	6706	1			T4	7		T39	28		T40	231
alert_integrity_fail	alert[0x1c]	7863	1			T78	9		T40	116		T113	136
alert_integrity_fail	alert[0x1d]	12673	1			T3	16		T4	16		T13	623
alert_integrity_fail	alert[0x1e]	6591	1			T13	39		T78	19		T28	32
alert_integrity_fail	alert[0x1f]	5646	1			T13	1145		T78	58		T73	56
alert_integrity_fail	alert[0x20]	12100	1			T4	28		T24	40		T39	37
alert_integrity_fail	alert[0x21]	4390	1			T18	8		T13	92		T78	13
alert_integrity_fail	alert[0x22]	11188	1			T3	29		T24	1283		T13	13
alert_integrity_fail	alert[0x23]	7189	1			T4	455		T24	16		T13	10
alert_integrity_fail	alert[0x24]	9604	1			T4	63		T34	2		T39	234
alert_integrity_fail	alert[0x25]	17706	1			T4	53		T24	1465		T34	13
alert_integrity_fail	alert[0x26]	3364	1			T3	27		T4	46		T13	11
alert_integrity_fail	alert[0x27]	7275	1			T4	23		T13	215		T78	280
alert_integrity_fail	alert[0x28]	4443	1			T4	108		T24	37		T40	769
alert_integrity_fail	alert[0x29]	4209	1			T4	4		T39	269		T113	145
alert_integrity_fail	alert[0x2a]	8444	1			T3	135		T4	319		T13	23
alert_integrity_fail	alert[0x2b]	10267	1			T4	5		T24	1738		T13	3
alert_integrity_fail	alert[0x2c]	11590	1			T24	34		T28	9		T83	1
alert_integrity_fail	alert[0x2d]	15836	1			T4	19		T40	170		T113	1689
alert_integrity_fail	alert[0x2e]	5770	1			T3	118		T24	140		T13	14
alert_integrity_fail	alert[0x2f]	8574	1			T4	51		T24	5		T13	70
alert_integrity_fail	alert[0x30]	4812	1			T3	3		T4	308		T24	1235
alert_integrity_fail	alert[0x31]	9931	1			T3	1		T13	202		T28	479
alert_integrity_fail	alert[0x32]	8766	1			T3	38		T4	13		T15	4
alert_integrity_fail	alert[0x33]	9966	1			T3	7		T13	366		T59	55
alert_integrity_fail	alert[0x34]	5860	1			T4	194		T24	47		T13	253
alert_integrity_fail	alert[0x35]	10545	1			T4	10		T24	18		T39	198
alert_integrity_fail	alert[0x36]	10701	1			T3	69		T34	1		T78	22
alert_integrity_fail	alert[0x37]	12038	1			T19	1		T73	104		T22	295
alert_integrity_fail	alert[0x38]	12774	1			T13	324		T39	1234		T40	383
alert_integrity_fail	alert[0x39]	11833	1			T4	9		T39	57		T83	8
alert_integrity_fail	alert[0x3a]	4051	1			T3	1		T13	142		T78	2
alert_integrity_fail	alert[0x3b]	14111	1			T24	61		T78	146		T39	28
alert_integrity_fail	alert[0x3c]	2590	1			T4	74		T24	717		T78	45
alert_integrity_fail	alert[0x3d]	6240	1			T4	21		T78	16		T19	1
alert_integrity_fail	alert[0x3e]	14335	1			T4	48		T78	18		T40	1694
alert_integrity_fail	alert[0x3f]	5757	1			T4	230		T24	426		T13	20
alert_integrity_fail	alert[0x40]	5935	1			T4	35		T24	50		T13	7
alert_ping_fail	alert[0x0]	10	1			T5	3		T119	2		T281	1
alert_ping_fail	alert[0x1]	14	1			T212	1		T47	1		T281	2
alert_ping_fail	alert[0x2]	6	1			T47	1		T282	1		T283	1
alert_ping_fail	alert[0x3]	9	1			T16	1		T76	1		T284	1
alert_ping_fail	alert[0x4]	14	1			T5	1		T76	2		T119	1
alert_ping_fail	alert[0x5]	13	1			T53	1		T282	1		T217	1
alert_ping_fail	alert[0x6]	8	1			T16	1		T285	1		T286	1
alert_ping_fail	alert[0x7]	13	1			T53	1		T110	1		T287	1
alert_ping_fail	alert[0x8]	16	1			T33	1		T76	2		T279	1
alert_ping_fail	alert[0x9]	16	1			T5	1		T285	1		T119	1
alert_ping_fail	alert[0xa]	12	1			T16	1		T285	1		T281	1
alert_ping_fail	alert[0xb]	11	1			T16	1		T76	1		T47	1
alert_ping_fail	alert[0xc]	15	1			T284	1		T283	1		T288	2
alert_ping_fail	alert[0xd]	12	1			T16	1		T33	1		T285	1
alert_ping_fail	alert[0xe]	12	1			T16	2		T47	1		T289	1
alert_ping_fail	alert[0xf]	13	1			T5	1		T285	1		T284	1
alert_ping_fail	alert[0x10]	14	1			T33	1		T285	2		T289	1
alert_ping_fail	alert[0x11]	12	1			T16	1		T76	1		T286	1
alert_ping_fail	alert[0x12]	8	1			T286	2		T287	1		T288	1
alert_ping_fail	alert[0x13]	19	1			T5	1		T16	1		T17	1
alert_ping_fail	alert[0x14]	15	1			T5	1		T33	1		T212	1
alert_ping_fail	alert[0x15]	10	1			T37	1		T285	1		T121	1
alert_ping_fail	alert[0x16]	14	1			T278	1		T279	1		T47	1
alert_ping_fail	alert[0x17]	7	1			T47	1		T217	1		T290	1
alert_ping_fail	alert[0x18]	9	1			T16	1		T76	1		T281	1
alert_ping_fail	alert[0x19]	11	1			T47	1		T291	1		T284	1
alert_ping_fail	alert[0x1a]	7	1			T292	1		T293	1		T294	1
alert_ping_fail	alert[0x1b]	7	1			T285	1		T269	1		T295	1
alert_ping_fail	alert[0x1c]	8	1			T291	1		T261	1		T121	2
alert_ping_fail	alert[0x1d]	9	1			T33	1		T261	1		T289	1
alert_ping_fail	alert[0x1e]	7	1			T76	2		T285	1		T217	1
alert_ping_fail	alert[0x1f]	13	1			T16	1		T289	1		T282	1
alert_ping_fail	alert[0x20]	11	1			T5	1		T269	1		T293	1
alert_ping_fail	alert[0x21]	17	1			T212	1		T47	2		T296	1
alert_ping_fail	alert[0x22]	22	1			T5	1		T76	1		T47	1
alert_ping_fail	alert[0x23]	7	1			T5	1		T289	1		T217	1
alert_ping_fail	alert[0x24]	11	1			T212	1		T76	1		T295	1
alert_ping_fail	alert[0x25]	11	1			T212	1		T47	1		T291	1
alert_ping_fail	alert[0x26]	10	1			T5	1		T212	1		T47	1
alert_ping_fail	alert[0x27]	10	1			T119	1		T284	2		T288	1
alert_ping_fail	alert[0x28]	13	1			T16	1		T297	1		T289	1
alert_ping_fail	alert[0x29]	10	1			T76	1		T287	1		T284	1
alert_ping_fail	alert[0x2a]	9	1			T47	1		T298	1		T281	1
alert_ping_fail	alert[0x2b]	12	1			T76	1		T285	1		T291	1
alert_ping_fail	alert[0x2c]	20	1			T298	2		T119	1		T287	1
alert_ping_fail	alert[0x2d]	20	1			T285	1		T119	1		T286	1
alert_ping_fail	alert[0x2e]	14	1			T211	1		T76	1		T217	1
alert_ping_fail	alert[0x2f]	15	1			T47	1		T119	1		T281	1
alert_ping_fail	alert[0x30]	13	1			T212	1		T76	1		T280	2
alert_ping_fail	alert[0x31]	8	1			T284	1		T217	1		T288	1
alert_ping_fail	alert[0x32]	11	1			T5	1		T289	1		T288	2
alert_ping_fail	alert[0x33]	8	1			T47	1		T284	1		T283	1
alert_ping_fail	alert[0x34]	7	1			T16	1		T289	1		T299	1
alert_ping_fail	alert[0x35]	9	1			T212	1		T285	1		T287	1
alert_ping_fail	alert[0x36]	7	1			T16	1		T300	1		T292	1
alert_ping_fail	alert[0x37]	14	1			T212	1		T285	1		T289	1
alert_ping_fail	alert[0x38]	16	1			T212	1		T285	1		T286	1
alert_ping_fail	alert[0x39]	11	1			T16	1		T76	1		T119	1
alert_ping_fail	alert[0x3a]	9	1			T16	1		T285	1		T286	1
alert_ping_fail	alert[0x3b]	8	1			T212	1		T76	1		T119	1
alert_ping_fail	alert[0x3c]	8	1			T16	1		T33	1		T285	1
alert_ping_fail	alert[0x3d]	5	1			T76	1		T47	1		T289	1
alert_ping_fail	alert[0x3e]	9	1			T16	1		T76	1		T291	1
alert_ping_fail	alert[0x3f]	9	1			T286	1		T287	1		T283	1
alert_ping_fail	alert[0x40]	5	1			T5	1		T289	1		T284	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	173711	1			T3	372		T24	8907		T18	3
alert_integrity_fail	class_i[0x1]	77444	1			T3	352		T18	5		T13	6225
alert_integrity_fail	class_i[0x2]	160058	1			T3	377		T4	4453		T15	4
alert_integrity_fail	class_i[0x3]	153691	1			T3	12		T24	7180		T18	1
alert_ping_fail	class_i[0x0]	197	1			T211	1		T212	1		T76	1
alert_ping_fail	class_i[0x1]	168	1			T5	13		T33	5		T212	6
alert_ping_fail	class_i[0x2]	159	1			T53	2		T16	18		T212	1
alert_ping_fail	class_i[0x3]	209	1			T5	1		T37	1		T33	1