Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.70 99.86 98.50 90.17 91.94 99.81 97.13 99.48


Total test records in report: 827
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T771 /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.4075950200 Apr 25 12:58:40 PM PDT 24 Apr 25 12:58:52 PM PDT 24 299027163 ps
T772 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.3541473436 Apr 25 12:59:19 PM PDT 24 Apr 25 12:59:22 PM PDT 24 24529463 ps
T773 /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.4222564449 Apr 25 12:58:41 PM PDT 24 Apr 25 01:02:41 PM PDT 24 12289172302 ps
T144 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.2160550354 Apr 25 12:58:45 PM PDT 24 Apr 25 01:04:00 PM PDT 24 5463696167 ps
T774 /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.2104895158 Apr 25 12:59:04 PM PDT 24 Apr 25 12:59:19 PM PDT 24 385770609 ps
T775 /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.452941274 Apr 25 12:58:58 PM PDT 24 Apr 25 12:59:13 PM PDT 24 179923848 ps
T776 /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.1738796204 Apr 25 12:58:55 PM PDT 24 Apr 25 12:58:59 PM PDT 24 9213604 ps
T777 /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.764701036 Apr 25 12:58:52 PM PDT 24 Apr 25 12:58:58 PM PDT 24 64788141 ps
T778 /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.1545050914 Apr 25 12:58:43 PM PDT 24 Apr 25 12:58:50 PM PDT 24 259781270 ps
T779 /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.1613049304 Apr 25 12:58:47 PM PDT 24 Apr 25 12:58:57 PM PDT 24 188653218 ps
T780 /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.483324704 Apr 25 12:58:57 PM PDT 24 Apr 25 12:59:16 PM PDT 24 244886027 ps
T781 /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.2472320841 Apr 25 12:58:46 PM PDT 24 Apr 25 01:04:42 PM PDT 24 23759289124 ps
T782 /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.3352484768 Apr 25 12:58:54 PM PDT 24 Apr 25 12:58:59 PM PDT 24 10873345 ps
T783 /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.3985025134 Apr 25 12:58:37 PM PDT 24 Apr 25 12:58:40 PM PDT 24 9984899 ps
T170 /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.621971029 Apr 25 12:58:49 PM PDT 24 Apr 25 12:58:57 PM PDT 24 132724517 ps
T784 /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.1619924844 Apr 25 12:59:08 PM PDT 24 Apr 25 12:59:19 PM PDT 24 964820522 ps
T153 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.2798029595 Apr 25 12:58:46 PM PDT 24 Apr 25 01:06:17 PM PDT 24 8822624112 ps
T785 /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.1233495744 Apr 25 12:59:10 PM PDT 24 Apr 25 12:59:13 PM PDT 24 7419267 ps
T149 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3526300212 Apr 25 12:58:56 PM PDT 24 Apr 25 01:14:42 PM PDT 24 54522271108 ps
T786 /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3836984982 Apr 25 12:58:55 PM PDT 24 Apr 25 12:59:03 PM PDT 24 127222054 ps
T176 /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.2843742252 Apr 25 12:58:47 PM PDT 24 Apr 25 12:59:28 PM PDT 24 611704046 ps
T180 /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.3111173575 Apr 25 12:58:48 PM PDT 24 Apr 25 12:59:12 PM PDT 24 318534982 ps
T151 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.1800345050 Apr 25 12:58:40 PM PDT 24 Apr 25 01:04:39 PM PDT 24 34655261246 ps
T787 /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.3162923512 Apr 25 12:58:53 PM PDT 24 Apr 25 12:58:57 PM PDT 24 22814695 ps
T788 /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.1198414681 Apr 25 12:58:48 PM PDT 24 Apr 25 12:59:23 PM PDT 24 2004171985 ps
T789 /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.772221594 Apr 25 12:58:48 PM PDT 24 Apr 25 12:58:56 PM PDT 24 54512204 ps
T790 /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.847455795 Apr 25 12:58:48 PM PDT 24 Apr 25 12:58:52 PM PDT 24 10349277 ps
T791 /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.2423268382 Apr 25 12:58:51 PM PDT 24 Apr 25 12:58:55 PM PDT 24 8103752 ps
T177 /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.1667758962 Apr 25 12:58:56 PM PDT 24 Apr 25 12:59:33 PM PDT 24 1833896345 ps
T792 /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.3939516965 Apr 25 12:58:42 PM PDT 24 Apr 25 12:58:48 PM PDT 24 92234667 ps
T184 /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.672516749 Apr 25 12:59:01 PM PDT 24 Apr 25 12:59:47 PM PDT 24 1201581637 ps
T793 /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.2248102505 Apr 25 12:59:01 PM PDT 24 Apr 25 12:59:21 PM PDT 24 1095480592 ps
T794 /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.430043078 Apr 25 12:59:05 PM PDT 24 Apr 25 12:59:08 PM PDT 24 9244391 ps
T795 /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.1629166979 Apr 25 12:58:58 PM PDT 24 Apr 25 12:59:04 PM PDT 24 20579498 ps
T796 /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.3188547278 Apr 25 12:58:40 PM PDT 24 Apr 25 12:58:48 PM PDT 24 55259274 ps
T172 /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.2881018393 Apr 25 12:58:55 PM PDT 24 Apr 25 12:59:01 PM PDT 24 23233975 ps
T173 /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.3178174351 Apr 25 12:58:54 PM PDT 24 Apr 25 12:59:34 PM PDT 24 598480684 ps
T797 /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.1875839201 Apr 25 12:58:48 PM PDT 24 Apr 25 12:58:54 PM PDT 24 34032085 ps
T798 /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.4064414639 Apr 25 12:58:56 PM PDT 24 Apr 25 12:59:01 PM PDT 24 20522925 ps
T799 /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.1359182587 Apr 25 12:58:46 PM PDT 24 Apr 25 01:07:27 PM PDT 24 37175226724 ps
T800 /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.678352133 Apr 25 12:59:00 PM PDT 24 Apr 25 12:59:07 PM PDT 24 96010398 ps
T801 /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1885555136 Apr 25 12:58:50 PM PDT 24 Apr 25 12:59:13 PM PDT 24 181184876 ps
T802 /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.4010828755 Apr 25 12:59:06 PM PDT 24 Apr 25 12:59:21 PM PDT 24 206579837 ps
T803 /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.513245153 Apr 25 12:58:47 PM PDT 24 Apr 25 12:58:58 PM PDT 24 122870702 ps
T804 /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.2663091220 Apr 25 12:58:58 PM PDT 24 Apr 25 12:59:03 PM PDT 24 9863509 ps
T154 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.571677975 Apr 25 12:58:46 PM PDT 24 Apr 25 01:03:43 PM PDT 24 4271875722 ps
T805 /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.3758776802 Apr 25 12:59:05 PM PDT 24 Apr 25 12:59:08 PM PDT 24 8664513 ps
T806 /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.1076190026 Apr 25 12:58:53 PM PDT 24 Apr 25 12:59:02 PM PDT 24 62805654 ps
T807 /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.967572837 Apr 25 12:59:10 PM PDT 24 Apr 25 12:59:30 PM PDT 24 263358040 ps
T808 /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.342743703 Apr 25 12:59:13 PM PDT 24 Apr 25 12:59:25 PM PDT 24 519169933 ps
T158 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.3097604404 Apr 25 12:58:35 PM PDT 24 Apr 25 01:01:31 PM PDT 24 11077227256 ps
T809 /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.2145803771 Apr 25 12:59:04 PM PDT 24 Apr 25 12:59:23 PM PDT 24 990119576 ps
T159 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.565992254 Apr 25 12:58:25 PM PDT 24 Apr 25 01:03:21 PM PDT 24 17961891768 ps
T810 /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.2869947832 Apr 25 12:58:52 PM PDT 24 Apr 25 12:59:13 PM PDT 24 2361704792 ps
T811 /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.1228472443 Apr 25 12:58:53 PM PDT 24 Apr 25 12:58:57 PM PDT 24 46648540 ps
T812 /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.1745379332 Apr 25 12:59:00 PM PDT 24 Apr 25 12:59:22 PM PDT 24 156548721 ps
T813 /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.2225919938 Apr 25 12:58:53 PM PDT 24 Apr 25 12:59:05 PM PDT 24 358039338 ps
T814 /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.1441024721 Apr 25 12:59:17 PM PDT 24 Apr 25 12:59:54 PM PDT 24 1922184109 ps
T815 /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.455526108 Apr 25 12:58:47 PM PDT 24 Apr 25 12:59:00 PM PDT 24 569174502 ps
T816 /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.3360906319 Apr 25 12:58:55 PM PDT 24 Apr 25 12:59:43 PM PDT 24 703268083 ps
T817 /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.2819968655 Apr 25 12:58:54 PM PDT 24 Apr 25 12:58:59 PM PDT 24 10067705 ps
T155 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.2761996027 Apr 25 12:59:01 PM PDT 24 Apr 25 01:15:11 PM PDT 24 51455571869 ps
T818 /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.3433301922 Apr 25 12:58:47 PM PDT 24 Apr 25 01:03:41 PM PDT 24 14986101012 ps
T819 /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2993951802 Apr 25 12:58:38 PM PDT 24 Apr 25 12:58:46 PM PDT 24 151270414 ps
T820 /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.4271013989 Apr 25 12:58:44 PM PDT 24 Apr 25 12:58:52 PM PDT 24 44279541 ps
T161 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.1766309764 Apr 25 12:58:52 PM PDT 24 Apr 25 01:00:44 PM PDT 24 1110333132 ps
T821 /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.2504582311 Apr 25 12:59:08 PM PDT 24 Apr 25 12:59:11 PM PDT 24 8334518 ps
T157 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.165250817 Apr 25 12:59:05 PM PDT 24 Apr 25 01:02:34 PM PDT 24 1696565600 ps
T160 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.927890937 Apr 25 12:58:41 PM PDT 24 Apr 25 01:01:57 PM PDT 24 3162335146 ps
T822 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.128667510 Apr 25 12:59:14 PM PDT 24 Apr 25 01:02:30 PM PDT 24 2019093807 ps
T823 /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.1545946836 Apr 25 12:58:54 PM PDT 24 Apr 25 12:59:02 PM PDT 24 54216474 ps
T162 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.2580874672 Apr 25 12:59:00 PM PDT 24 Apr 25 01:06:23 PM PDT 24 12071343739 ps
T824 /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.3542041453 Apr 25 12:58:52 PM PDT 24 Apr 25 12:58:56 PM PDT 24 11204613 ps
T825 /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.3928389158 Apr 25 12:58:48 PM PDT 24 Apr 25 12:58:52 PM PDT 24 13877219 ps
T826 /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.2635156214 Apr 25 12:58:41 PM PDT 24 Apr 25 12:58:49 PM PDT 24 323983371 ps
T827 /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.360190689 Apr 25 12:59:09 PM PDT 24 Apr 25 12:59:19 PM PDT 24 209617849 ps
T183 /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.242822407 Apr 25 12:58:44 PM PDT 24 Apr 25 12:59:08 PM PDT 24 630318665 ps

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.878395927
Short name T3
Test name
Test status
Simulation time 113100450483 ps
CPU time 3397.22 seconds
Started Apr 25 01:53:10 PM PDT 24
Finished Apr 25 02:49:48 PM PDT 24
Peak memory 305492 kb
Host smart-69a4ceb1-abc6-4419-b9f9-2125c10e2e76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878395927 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.878395927
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.721544869
Short name T40
Test name
Test status
Simulation time 38363386272 ps
CPU time 2104.44 seconds
Started Apr 25 01:55:04 PM PDT 24
Finished Apr 25 02:30:09 PM PDT 24
Peak memory 281584 kb
Host smart-44e8d3b4-fdb2-4534-ad4c-05c91a65f4c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721544869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.721544869
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.538294690
Short name T163
Test name
Test status
Simulation time 979740220 ps
CPU time 31.37 seconds
Started Apr 25 12:58:41 PM PDT 24
Finished Apr 25 12:59:15 PM PDT 24
Peak memory 240636 kb
Host smart-6d8335b7-ae4c-4f36-8637-a17732b7f033
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=538294690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.538294690
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.2775262559
Short name T45
Test name
Test status
Simulation time 31439769732 ps
CPU time 1671.38 seconds
Started Apr 25 01:53:29 PM PDT 24
Finished Apr 25 02:21:21 PM PDT 24
Peak memory 273300 kb
Host smart-e399f38d-53e9-45e2-8720-2eae93d4ff77
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775262559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.2775262559
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.2203566780
Short name T2
Test name
Test status
Simulation time 5797122290 ps
CPU time 44.52 seconds
Started Apr 25 01:53:41 PM PDT 24
Finished Apr 25 01:54:26 PM PDT 24
Peak memory 248760 kb
Host smart-20da66f3-2730-4239-9470-cd627d6a52cc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2203566780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.2203566780
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.574922844
Short name T46
Test name
Test status
Simulation time 27490373234 ps
CPU time 649.9 seconds
Started Apr 25 01:54:38 PM PDT 24
Finished Apr 25 02:05:28 PM PDT 24
Peak memory 272684 kb
Host smart-b6c1b6a5-ffdd-4ea2-ad9a-4a74875b15fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574922844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.574922844
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.199644981
Short name T93
Test name
Test status
Simulation time 50789007840 ps
CPU time 4561.43 seconds
Started Apr 25 01:54:55 PM PDT 24
Finished Apr 25 03:10:57 PM PDT 24
Peak memory 338760 kb
Host smart-07b9476d-762d-4b60-9995-eba1bbdd5579
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199644981 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.199644981
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.1449381493
Short name T124
Test name
Test status
Simulation time 4551087813 ps
CPU time 556.71 seconds
Started Apr 25 12:58:55 PM PDT 24
Finished Apr 25 01:08:15 PM PDT 24
Peak memory 265580 kb
Host smart-c42c93c5-1bb5-42e7-80e3-0695510baf7a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449381493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.1449381493
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.2624467851
Short name T53
Test name
Test status
Simulation time 52491668302 ps
CPU time 1578.55 seconds
Started Apr 25 01:53:13 PM PDT 24
Finished Apr 25 02:19:33 PM PDT 24
Peak memory 273400 kb
Host smart-97baadf2-abb4-4a8f-b319-7dc114f47c2d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624467851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.2624467851
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.886074683
Short name T137
Test name
Test status
Simulation time 5387950741 ps
CPU time 276.2 seconds
Started Apr 25 12:58:56 PM PDT 24
Finished Apr 25 01:03:40 PM PDT 24
Peak memory 265680 kb
Host smart-a32881c1-f359-4a71-8581-0320c828b4b7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=886074683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_error
s.886074683
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.3846938302
Short name T64
Test name
Test status
Simulation time 280786747061 ps
CPU time 1538.54 seconds
Started Apr 25 01:53:23 PM PDT 24
Finished Apr 25 02:19:02 PM PDT 24
Peak memory 298268 kb
Host smart-316ee966-ffb3-4cbb-9419-02b8fe521824
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846938302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.3846938302
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.563715948
Short name T141
Test name
Test status
Simulation time 5261895639 ps
CPU time 611.51 seconds
Started Apr 25 12:58:47 PM PDT 24
Finished Apr 25 01:09:01 PM PDT 24
Peak memory 265908 kb
Host smart-f5026ff8-d9cc-42bc-a5ca-ee4d77beafbb
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563715948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.563715948
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.4052568156
Short name T4
Test name
Test status
Simulation time 125315490690 ps
CPU time 2939.07 seconds
Started Apr 25 01:56:11 PM PDT 24
Finished Apr 25 02:45:11 PM PDT 24
Peak memory 306276 kb
Host smart-2a7c4061-3ef0-42f0-8604-9f4e0cf29c9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052568156 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.4052568156
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.927890937
Short name T160
Test name
Test status
Simulation time 3162335146 ps
CPU time 193.57 seconds
Started Apr 25 12:58:41 PM PDT 24
Finished Apr 25 01:01:57 PM PDT 24
Peak memory 265724 kb
Host smart-0378ba9e-8426-4e14-af45-26ff17b79a9f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=927890937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_error
s.927890937
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.1616855687
Short name T296
Test name
Test status
Simulation time 59955269316 ps
CPU time 3416.67 seconds
Started Apr 25 01:53:23 PM PDT 24
Finished Apr 25 02:50:21 PM PDT 24
Peak memory 288972 kb
Host smart-d71eb29f-b986-467c-9f3e-7d1839e5504f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616855687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.1616855687
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.1207900909
Short name T285
Test name
Test status
Simulation time 26210682169 ps
CPU time 529.18 seconds
Started Apr 25 01:52:56 PM PDT 24
Finished Apr 25 02:01:46 PM PDT 24
Peak memory 248208 kb
Host smart-6e381e3b-855c-459d-b096-775fd21731ab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207900909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.1207900909
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.1095819148
Short name T130
Test name
Test status
Simulation time 4425080042 ps
CPU time 603.26 seconds
Started Apr 25 12:58:44 PM PDT 24
Finished Apr 25 01:08:49 PM PDT 24
Peak memory 265572 kb
Host smart-bb7063c4-3de0-479a-aac3-c1be252887f9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095819148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.1095819148
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.28786344
Short name T321
Test name
Test status
Simulation time 12786818 ps
CPU time 1.72 seconds
Started Apr 25 12:58:58 PM PDT 24
Finished Apr 25 12:59:07 PM PDT 24
Peak memory 237268 kb
Host smart-1eb504d4-7426-40e5-960d-30a6f912a80b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=28786344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.28786344
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.2726202859
Short name T175
Test name
Test status
Simulation time 615271521 ps
CPU time 47.5 seconds
Started Apr 25 12:59:04 PM PDT 24
Finished Apr 25 12:59:54 PM PDT 24
Peak memory 240776 kb
Host smart-362f7df3-9ea9-4207-b13a-0717a9b9e593
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2726202859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.2726202859
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.2801767541
Short name T30
Test name
Test status
Simulation time 168116855926 ps
CPU time 6954.15 seconds
Started Apr 25 01:53:42 PM PDT 24
Finished Apr 25 03:49:37 PM PDT 24
Peak memory 334292 kb
Host smart-37d439d9-ba63-4cc1-b983-c97669168f55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801767541 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.2801767541
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.693427550
Short name T261
Test name
Test status
Simulation time 121952630070 ps
CPU time 1530.38 seconds
Started Apr 25 01:54:59 PM PDT 24
Finished Apr 25 02:20:30 PM PDT 24
Peak memory 268208 kb
Host smart-eba08c65-fae4-4192-a1be-f3d2060c047d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693427550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.693427550
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.2761996027
Short name T155
Test name
Test status
Simulation time 51455571869 ps
CPU time 967.77 seconds
Started Apr 25 12:59:01 PM PDT 24
Finished Apr 25 01:15:11 PM PDT 24
Peak memory 273732 kb
Host smart-e11cbdd1-96ef-4b1c-bc15-97ba0abff694
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761996027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.2761996027
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.1872771869
Short name T47
Test name
Test status
Simulation time 10531490676 ps
CPU time 437.66 seconds
Started Apr 25 01:55:22 PM PDT 24
Finished Apr 25 02:02:40 PM PDT 24
Peak memory 247876 kb
Host smart-c30e4ade-00b3-4bf3-9eef-734e9e7d992d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872771869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.1872771869
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.1455092848
Short name T305
Test name
Test status
Simulation time 40331004521 ps
CPU time 2329.22 seconds
Started Apr 25 01:55:13 PM PDT 24
Finished Apr 25 02:34:03 PM PDT 24
Peak memory 281528 kb
Host smart-c13f6644-ad73-4d9e-92c9-0cad026c55a4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455092848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.1455092848
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.1833477274
Short name T133
Test name
Test status
Simulation time 6734024338 ps
CPU time 176.93 seconds
Started Apr 25 12:59:00 PM PDT 24
Finished Apr 25 01:01:59 PM PDT 24
Peak memory 265696 kb
Host smart-5c64e64d-ae00-433a-a260-9df3d350ec19
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1833477274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.1833477274
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.1842865944
Short name T76
Test name
Test status
Simulation time 65549674402 ps
CPU time 628.66 seconds
Started Apr 25 01:54:12 PM PDT 24
Finished Apr 25 02:04:42 PM PDT 24
Peak memory 248296 kb
Host smart-4a6a0260-5813-4c39-97bc-f7ce8ba8c79a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842865944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.1842865944
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.2574071441
Short name T62
Test name
Test status
Simulation time 52102508328 ps
CPU time 1521.59 seconds
Started Apr 25 01:54:13 PM PDT 24
Finished Apr 25 02:19:35 PM PDT 24
Peak memory 289340 kb
Host smart-36b6806e-b4e2-46f6-8dec-7b73c812af96
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574071441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.2574071441
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.3322756561
Short name T22
Test name
Test status
Simulation time 59181462077 ps
CPU time 1212.99 seconds
Started Apr 25 01:57:43 PM PDT 24
Finished Apr 25 02:17:56 PM PDT 24
Peak memory 289704 kb
Host smart-e003da93-28f0-4eb5-8d02-818d64eef1f0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322756561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.3322756561
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3526300212
Short name T149
Test name
Test status
Simulation time 54522271108 ps
CPU time 943.21 seconds
Started Apr 25 12:58:56 PM PDT 24
Finished Apr 25 01:14:42 PM PDT 24
Peak memory 265572 kb
Host smart-2ac601e2-8830-4e86-9f49-88a1067ec5c0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526300212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.3526300212
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.1866018361
Short name T317
Test name
Test status
Simulation time 33431839793 ps
CPU time 1847.97 seconds
Started Apr 25 01:56:11 PM PDT 24
Finished Apr 25 02:27:00 PM PDT 24
Peak memory 286344 kb
Host smart-a2e93a09-c846-4be5-ab00-c8b9b5ef0424
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866018361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.1866018361
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.267245981
Short name T139
Test name
Test status
Simulation time 4239744184 ps
CPU time 159.91 seconds
Started Apr 25 12:58:53 PM PDT 24
Finished Apr 25 01:01:36 PM PDT 24
Peak memory 265724 kb
Host smart-501b84dc-98f3-47e6-a618-0e86fe47e890
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=267245981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_error
s.267245981
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.2892232961
Short name T284
Test name
Test status
Simulation time 28594011526 ps
CPU time 570.5 seconds
Started Apr 25 01:52:16 PM PDT 24
Finished Apr 25 02:01:47 PM PDT 24
Peak memory 248044 kb
Host smart-9cf8e6c8-34b2-4c73-90be-22f8d6e92fff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892232961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.2892232961
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.255697976
Short name T20
Test name
Test status
Simulation time 42497231527 ps
CPU time 2684.53 seconds
Started Apr 25 01:56:22 PM PDT 24
Finished Apr 25 02:41:08 PM PDT 24
Peak memory 300332 kb
Host smart-969febea-2dc9-4320-97db-a057234abce6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255697976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_han
dler_stress_all.255697976
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.4160865578
Short name T168
Test name
Test status
Simulation time 8525057 ps
CPU time 1.59 seconds
Started Apr 25 12:58:51 PM PDT 24
Finished Apr 25 12:58:54 PM PDT 24
Peak memory 237188 kb
Host smart-cef8eae8-95f5-4eab-a31e-3a40ecce4830
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4160865578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.4160865578
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.3059926226
Short name T242
Test name
Test status
Simulation time 831817154 ps
CPU time 36.53 seconds
Started Apr 25 01:53:34 PM PDT 24
Finished Apr 25 01:54:11 PM PDT 24
Peak memory 255424 kb
Host smart-9d1d54d3-e5ba-4b6a-98a4-3b9aa2d2bfe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30599
26226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.3059926226
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.3099730113
Short name T110
Test name
Test status
Simulation time 11580350573 ps
CPU time 802.85 seconds
Started Apr 25 01:52:38 PM PDT 24
Finished Apr 25 02:06:01 PM PDT 24
Peak memory 266232 kb
Host smart-4f0cb1e6-abc5-4f52-90e4-f6ddb6995dd1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099730113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.3099730113
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.2769682694
Short name T289
Test name
Test status
Simulation time 10048635229 ps
CPU time 419.96 seconds
Started Apr 25 01:52:49 PM PDT 24
Finished Apr 25 01:59:50 PM PDT 24
Peak memory 247884 kb
Host smart-0f755077-4783-4d08-9c7c-461142a516e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769682694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.2769682694
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.1753174206
Short name T78
Test name
Test status
Simulation time 156357310416 ps
CPU time 2277.61 seconds
Started Apr 25 01:57:30 PM PDT 24
Finished Apr 25 02:35:28 PM PDT 24
Peak memory 289876 kb
Host smart-ddd1f253-52e6-4592-b0a5-669950cdd467
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753174206 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.1753174206
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.2029750503
Short name T138
Test name
Test status
Simulation time 2489366742 ps
CPU time 321.57 seconds
Started Apr 25 12:59:08 PM PDT 24
Finished Apr 25 01:04:32 PM PDT 24
Peak memory 269420 kb
Host smart-23a90425-fc53-4c05-bb79-0f4eac6301da
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029750503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.2029750503
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.2160550354
Short name T144
Test name
Test status
Simulation time 5463696167 ps
CPU time 312.59 seconds
Started Apr 25 12:58:45 PM PDT 24
Finished Apr 25 01:04:00 PM PDT 24
Peak memory 265556 kb
Host smart-a487dd8b-f02c-4311-85b0-5f91a70b43ff
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2160550354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.2160550354
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.3382227004
Short name T108
Test name
Test status
Simulation time 261668415 ps
CPU time 12.42 seconds
Started Apr 25 01:52:23 PM PDT 24
Finished Apr 25 01:52:35 PM PDT 24
Peak memory 254616 kb
Host smart-2f5b3897-3d5c-455b-8073-c99c79d1fe33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33822
27004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.3382227004
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.2223593320
Short name T42
Test name
Test status
Simulation time 171656892906 ps
CPU time 4021.89 seconds
Started Apr 25 01:55:01 PM PDT 24
Finished Apr 25 03:02:04 PM PDT 24
Peak memory 338300 kb
Host smart-5f77a494-1fd1-4ff1-8473-4d47e785ca86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223593320 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.2223593320
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.641198858
Short name T287
Test name
Test status
Simulation time 24684307165 ps
CPU time 401.41 seconds
Started Apr 25 01:55:12 PM PDT 24
Finished Apr 25 02:01:54 PM PDT 24
Peak memory 247940 kb
Host smart-ead2e520-6ed1-4068-bbf9-7c629cf05468
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641198858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.641198858
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.4054412785
Short name T169
Test name
Test status
Simulation time 58485745 ps
CPU time 3.92 seconds
Started Apr 25 12:58:54 PM PDT 24
Finished Apr 25 12:59:01 PM PDT 24
Peak memory 236292 kb
Host smart-edf3416a-3a37-4c18-8f35-3cc97fae3ebf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4054412785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.4054412785
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.86491446
Short name T135
Test name
Test status
Simulation time 6772458203 ps
CPU time 487.56 seconds
Started Apr 25 12:58:34 PM PDT 24
Finished Apr 25 01:06:44 PM PDT 24
Peak memory 265744 kb
Host smart-f0916132-34c7-4ded-b759-a937d571420e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86491446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.86491446
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.3501938417
Short name T199
Test name
Test status
Simulation time 52344891 ps
CPU time 2.95 seconds
Started Apr 25 01:52:21 PM PDT 24
Finished Apr 25 01:52:25 PM PDT 24
Peak memory 248880 kb
Host smart-e66e7733-631e-40c9-a90c-a109d79176a6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3501938417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.3501938417
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.2501007303
Short name T202
Test name
Test status
Simulation time 122790540 ps
CPU time 2.85 seconds
Started Apr 25 01:52:29 PM PDT 24
Finished Apr 25 01:52:32 PM PDT 24
Peak memory 248880 kb
Host smart-464ed0c1-202c-4d3f-9b63-4200c6a73d58
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2501007303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.2501007303
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.884578126
Short name T205
Test name
Test status
Simulation time 44388517 ps
CPU time 3.58 seconds
Started Apr 25 01:53:40 PM PDT 24
Finished Apr 25 01:53:44 PM PDT 24
Peak memory 248880 kb
Host smart-ca9a42bb-f649-4459-b7fe-a088a3f751e3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=884578126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.884578126
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.2802249118
Short name T203
Test name
Test status
Simulation time 104762937 ps
CPU time 2.84 seconds
Started Apr 25 01:53:48 PM PDT 24
Finished Apr 25 01:53:51 PM PDT 24
Peak memory 248856 kb
Host smart-a5f37c9d-08bb-4251-83fe-613795b84bd5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2802249118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.2802249118
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.551972254
Short name T60
Test name
Test status
Simulation time 31055281614 ps
CPU time 1891.95 seconds
Started Apr 25 01:52:31 PM PDT 24
Finished Apr 25 02:24:04 PM PDT 24
Peak memory 289624 kb
Host smart-ae11ad9a-4646-442a-a460-d3ce149ee8d0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551972254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_hand
ler_stress_all.551972254
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.2541069660
Short name T240
Test name
Test status
Simulation time 366235919 ps
CPU time 21.68 seconds
Started Apr 25 01:53:50 PM PDT 24
Finished Apr 25 01:54:12 PM PDT 24
Peak memory 255808 kb
Host smart-86f3334d-2654-465f-922a-4c283e2a7d85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25410
69660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.2541069660
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.963943468
Short name T298
Test name
Test status
Simulation time 321508400611 ps
CPU time 2665 seconds
Started Apr 25 01:54:23 PM PDT 24
Finished Apr 25 02:38:49 PM PDT 24
Peak memory 288964 kb
Host smart-900fb7d6-bdbf-46a4-a38d-dac499b67432
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963943468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.963943468
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.876901698
Short name T39
Test name
Test status
Simulation time 17585482796 ps
CPU time 1377.47 seconds
Started Apr 25 01:55:24 PM PDT 24
Finished Apr 25 02:18:22 PM PDT 24
Peak memory 289060 kb
Host smart-c61af113-ce3f-41e0-b05e-af307ab66aeb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876901698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.876901698
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.1080801649
Short name T292
Test name
Test status
Simulation time 104471249312 ps
CPU time 346.37 seconds
Started Apr 25 01:55:52 PM PDT 24
Finished Apr 25 02:01:39 PM PDT 24
Peak memory 247804 kb
Host smart-542a5d84-e5de-4b2b-96b3-ea46e6f20bab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080801649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.1080801649
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.3721570271
Short name T238
Test name
Test status
Simulation time 148811479422 ps
CPU time 5137.61 seconds
Started Apr 25 01:53:10 PM PDT 24
Finished Apr 25 03:18:49 PM PDT 24
Peak memory 305496 kb
Host smart-064dcf7d-4c16-4a80-994e-96c98669fb06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721570271 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.3721570271
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.2754307765
Short name T252
Test name
Test status
Simulation time 687730091773 ps
CPU time 3257.46 seconds
Started Apr 25 01:53:15 PM PDT 24
Finished Apr 25 02:47:33 PM PDT 24
Peak memory 289820 kb
Host smart-53a53f9a-a331-42d0-9ac7-52ffebd4d13f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754307765 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.2754307765
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.2028732301
Short name T94
Test name
Test status
Simulation time 17536783918 ps
CPU time 179.61 seconds
Started Apr 25 01:52:27 PM PDT 24
Finished Apr 25 01:55:27 PM PDT 24
Peak memory 254672 kb
Host smart-98b35829-8243-4530-a90b-2f432e79e072
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028732301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.2028732301
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.2555219732
Short name T8
Test name
Test status
Simulation time 236084205475 ps
CPU time 3428.08 seconds
Started Apr 25 01:56:10 PM PDT 24
Finished Apr 25 02:53:19 PM PDT 24
Peak memory 289696 kb
Host smart-7e904ea6-4e48-4d77-b0c9-daf78e964ab7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555219732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.2555219732
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.2602413836
Short name T131
Test name
Test status
Simulation time 4363770539 ps
CPU time 300.51 seconds
Started Apr 25 12:58:46 PM PDT 24
Finished Apr 25 01:03:49 PM PDT 24
Peak memory 267612 kb
Host smart-95ae6d63-76c2-446c-a588-182cfea46198
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602413836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.2602413836
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.3952077991
Short name T150
Test name
Test status
Simulation time 4591042649 ps
CPU time 642.99 seconds
Started Apr 25 12:58:53 PM PDT 24
Finished Apr 25 01:09:39 PM PDT 24
Peak memory 273760 kb
Host smart-d1cf5edb-3857-494f-b16b-b86d57b7b44f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952077991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.3952077991
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.2081621301
Short name T322
Test name
Test status
Simulation time 8159163 ps
CPU time 1.43 seconds
Started Apr 25 12:59:14 PM PDT 24
Finished Apr 25 12:59:18 PM PDT 24
Peak memory 237216 kb
Host smart-95841425-eaf9-472c-93d2-b63795318d39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2081621301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.2081621301
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.2400519864
Short name T256
Test name
Test status
Simulation time 104589950337 ps
CPU time 3219.21 seconds
Started Apr 25 01:53:48 PM PDT 24
Finished Apr 25 02:47:28 PM PDT 24
Peak memory 289340 kb
Host smart-150926cc-f741-4ba0-abc1-771850028742
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400519864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.2400519864
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.2877750465
Short name T320
Test name
Test status
Simulation time 79642140014 ps
CPU time 1284.1 seconds
Started Apr 25 01:53:53 PM PDT 24
Finished Apr 25 02:15:17 PM PDT 24
Peak memory 273336 kb
Host smart-d01ae0c4-21cc-43ce-a03e-10478b3ed7ab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877750465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.2877750465
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.473243486
Short name T244
Test name
Test status
Simulation time 3795445654 ps
CPU time 51.36 seconds
Started Apr 25 01:54:06 PM PDT 24
Finished Apr 25 01:54:58 PM PDT 24
Peak memory 256964 kb
Host smart-811cb044-2a7a-4f00-a70a-4a08ff0285d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47324
3486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.473243486
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.2290453725
Short name T251
Test name
Test status
Simulation time 195042632608 ps
CPU time 1390.95 seconds
Started Apr 25 01:54:05 PM PDT 24
Finished Apr 25 02:17:17 PM PDT 24
Peak memory 289168 kb
Host smart-57962429-eaa3-481e-82dc-de90e562c195
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290453725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.2290453725
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.2672848021
Short name T569
Test name
Test status
Simulation time 52613701925 ps
CPU time 1347.94 seconds
Started Apr 25 01:54:22 PM PDT 24
Finished Apr 25 02:16:51 PM PDT 24
Peak memory 289720 kb
Host smart-923d096a-2f7c-4019-92ad-097cdcc326c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672848021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.2672848021
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.3485086490
Short name T308
Test name
Test status
Simulation time 39864460568 ps
CPU time 1956.24 seconds
Started Apr 25 01:54:28 PM PDT 24
Finished Apr 25 02:27:05 PM PDT 24
Peak memory 283036 kb
Host smart-412412c5-d110-4f77-b3d6-c8749424ef23
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485086490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.3485086490
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.3716132175
Short name T262
Test name
Test status
Simulation time 277228316 ps
CPU time 18.38 seconds
Started Apr 25 01:54:37 PM PDT 24
Finished Apr 25 01:54:56 PM PDT 24
Peak memory 254988 kb
Host smart-381882ab-786c-4740-a256-001134746391
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37161
32175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.3716132175
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.1192686675
Short name T250
Test name
Test status
Simulation time 1480152563 ps
CPU time 44.86 seconds
Started Apr 25 01:55:01 PM PDT 24
Finished Apr 25 01:55:46 PM PDT 24
Peak memory 248720 kb
Host smart-951c90cc-dcaa-448d-ab11-93deebebbe05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11926
86675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.1192686675
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.1835098473
Short name T230
Test name
Test status
Simulation time 231638227 ps
CPU time 20.81 seconds
Started Apr 25 01:55:18 PM PDT 24
Finished Apr 25 01:55:39 PM PDT 24
Peak memory 247580 kb
Host smart-5dc1bbcf-1233-4ba7-9692-859dd89fc66e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18350
98473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.1835098473
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.2237220134
Short name T254
Test name
Test status
Simulation time 31191864412 ps
CPU time 637.42 seconds
Started Apr 25 01:55:22 PM PDT 24
Finished Apr 25 02:06:00 PM PDT 24
Peak memory 271712 kb
Host smart-472fa98e-bf63-43ff-bb72-3ea3e359a2c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237220134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.2237220134
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.3721196173
Short name T255
Test name
Test status
Simulation time 5009201396 ps
CPU time 64.93 seconds
Started Apr 25 01:55:59 PM PDT 24
Finished Apr 25 01:57:05 PM PDT 24
Peak memory 248776 kb
Host smart-623b96d3-8672-45eb-9fa8-143a2f828573
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37211
96173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.3721196173
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.1005903754
Short name T232
Test name
Test status
Simulation time 40144945378 ps
CPU time 2502.32 seconds
Started Apr 25 01:56:03 PM PDT 24
Finished Apr 25 02:37:46 PM PDT 24
Peak memory 289520 kb
Host smart-8dde4f4c-39a8-467f-8354-de9f6476f839
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005903754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.1005903754
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.4228698182
Short name T233
Test name
Test status
Simulation time 721209301 ps
CPU time 13.82 seconds
Started Apr 25 01:56:29 PM PDT 24
Finished Apr 25 01:56:43 PM PDT 24
Peak memory 254252 kb
Host smart-974859d9-a68c-455b-8cd3-42d7fbe61e33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42286
98182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.4228698182
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.529765746
Short name T268
Test name
Test status
Simulation time 14246137980 ps
CPU time 672.99 seconds
Started Apr 25 01:56:34 PM PDT 24
Finished Apr 25 02:07:47 PM PDT 24
Peak memory 273316 kb
Host smart-dce975b2-e298-4431-87ad-a515b7ce0581
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529765746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.529765746
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.4166679616
Short name T265
Test name
Test status
Simulation time 881541445 ps
CPU time 33.16 seconds
Started Apr 25 01:57:06 PM PDT 24
Finished Apr 25 01:57:40 PM PDT 24
Peak memory 248716 kb
Host smart-73a79219-31c6-4d30-ad8d-0fb66f94fb9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41666
79616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.4166679616
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.433084799
Short name T186
Test name
Test status
Simulation time 39496107201 ps
CPU time 1324.61 seconds
Started Apr 25 01:57:16 PM PDT 24
Finished Apr 25 02:19:22 PM PDT 24
Peak memory 285600 kb
Host smart-9eec53df-9dff-4560-bac5-70ff5307aa3d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433084799 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.433084799
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.1341575534
Short name T7
Test name
Test status
Simulation time 185790213142 ps
CPU time 2450.51 seconds
Started Apr 25 01:54:41 PM PDT 24
Finished Apr 25 02:35:32 PM PDT 24
Peak memory 281528 kb
Host smart-736ffb99-af2b-4285-93f6-9152b5e77ddc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341575534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.1341575534
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.2084233558
Short name T6
Test name
Test status
Simulation time 108385655584 ps
CPU time 1094.48 seconds
Started Apr 25 01:55:44 PM PDT 24
Finished Apr 25 02:13:59 PM PDT 24
Peak memory 289428 kb
Host smart-d88593eb-b9d9-4eb2-bd7c-452340e2e3d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084233558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.2084233558
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.2260565129
Short name T156
Test name
Test status
Simulation time 1492303005 ps
CPU time 128.48 seconds
Started Apr 25 12:59:01 PM PDT 24
Finished Apr 25 01:01:12 PM PDT 24
Peak memory 257356 kb
Host smart-eaec6712-2f69-4b59-af8d-f6bf03aa840b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2260565129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.2260565129
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.2153314845
Short name T171
Test name
Test status
Simulation time 159171074 ps
CPU time 3.06 seconds
Started Apr 25 12:58:58 PM PDT 24
Finished Apr 25 12:59:04 PM PDT 24
Peak memory 236284 kb
Host smart-8b45590b-fb69-4eb4-acc4-425c1549472f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2153314845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.2153314845
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.2881018393
Short name T172
Test name
Test status
Simulation time 23233975 ps
CPU time 2.4 seconds
Started Apr 25 12:58:55 PM PDT 24
Finished Apr 25 12:59:01 PM PDT 24
Peak memory 236264 kb
Host smart-b68dcb25-f33f-4ba6-9c6c-5b3916bf3dd4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2881018393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.2881018393
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.2843742252
Short name T176
Test name
Test status
Simulation time 611704046 ps
CPU time 39.15 seconds
Started Apr 25 12:58:47 PM PDT 24
Finished Apr 25 12:59:28 PM PDT 24
Peak memory 240116 kb
Host smart-fdd4a391-2fcb-4c79-8486-acb1d008826d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2843742252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.2843742252
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.2358858365
Short name T132
Test name
Test status
Simulation time 3211785898 ps
CPU time 96.08 seconds
Started Apr 25 12:58:47 PM PDT 24
Finished Apr 25 01:00:25 PM PDT 24
Peak memory 266168 kb
Host smart-3077d193-b4aa-4d36-b344-d7d3a0d51f9d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2358858365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.2358858365
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.128667510
Short name T822
Test name
Test status
Simulation time 2019093807 ps
CPU time 194.17 seconds
Started Apr 25 12:59:14 PM PDT 24
Finished Apr 25 01:02:30 PM PDT 24
Peak memory 265564 kb
Host smart-985e02db-be38-4e47-adaf-6eeb562aaad5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=128667510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_erro
rs.128667510
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.621971029
Short name T170
Test name
Test status
Simulation time 132724517 ps
CPU time 5.52 seconds
Started Apr 25 12:58:49 PM PDT 24
Finished Apr 25 12:58:57 PM PDT 24
Peak memory 237232 kb
Host smart-ae4a3e73-e5c2-4e35-ad9d-6d1772c82d84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=621971029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.621971029
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.851806484
Short name T165
Test name
Test status
Simulation time 173132487 ps
CPU time 3 seconds
Started Apr 25 12:58:46 PM PDT 24
Finished Apr 25 12:58:52 PM PDT 24
Peak memory 236324 kb
Host smart-3357743f-f5f8-4ff0-8139-983f78cbf76a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=851806484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.851806484
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.1280789169
Short name T174
Test name
Test status
Simulation time 2407829617 ps
CPU time 39.57 seconds
Started Apr 25 12:59:10 PM PDT 24
Finished Apr 25 12:59:51 PM PDT 24
Peak memory 245704 kb
Host smart-e3274f5d-70b5-4ce9-8761-78ea8692c98b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1280789169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.1280789169
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.242822407
Short name T183
Test name
Test status
Simulation time 630318665 ps
CPU time 22.32 seconds
Started Apr 25 12:58:44 PM PDT 24
Finished Apr 25 12:59:08 PM PDT 24
Peak memory 240024 kb
Host smart-3970c488-92cf-4af1-8b1e-8d5db823db24
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=242822407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.242822407
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3663673835
Short name T178
Test name
Test status
Simulation time 2020190204 ps
CPU time 30.83 seconds
Started Apr 25 12:58:46 PM PDT 24
Finished Apr 25 12:59:19 PM PDT 24
Peak memory 240212 kb
Host smart-15a7faa7-cd7d-49e7-a03f-4e5a8b479222
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3663673835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.3663673835
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.3111173575
Short name T180
Test name
Test status
Simulation time 318534982 ps
CPU time 21.28 seconds
Started Apr 25 12:58:48 PM PDT 24
Finished Apr 25 12:59:12 PM PDT 24
Peak memory 237336 kb
Host smart-167c18f0-9990-4b10-beba-1ff632d08514
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3111173575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.3111173575
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.3178174351
Short name T173
Test name
Test status
Simulation time 598480684 ps
CPU time 36.8 seconds
Started Apr 25 12:58:54 PM PDT 24
Finished Apr 25 12:59:34 PM PDT 24
Peak memory 239984 kb
Host smart-5642b107-ed0c-4a98-8c4e-82844e28aa54
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3178174351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.3178174351
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.672516749
Short name T184
Test name
Test status
Simulation time 1201581637 ps
CPU time 43.38 seconds
Started Apr 25 12:59:01 PM PDT 24
Finished Apr 25 12:59:47 PM PDT 24
Peak memory 239976 kb
Host smart-2c214875-3687-41df-bfe5-0ba992f82ccd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=672516749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.672516749
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.459121798
Short name T185
Test name
Test status
Simulation time 1236855097 ps
CPU time 37.57 seconds
Started Apr 25 12:58:40 PM PDT 24
Finished Apr 25 12:59:21 PM PDT 24
Peak memory 249000 kb
Host smart-90b1d97a-e34d-4035-8e80-af53797e4d54
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=459121798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.459121798
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.1667758962
Short name T177
Test name
Test status
Simulation time 1833896345 ps
CPU time 34.14 seconds
Started Apr 25 12:58:56 PM PDT 24
Finished Apr 25 12:59:33 PM PDT 24
Peak memory 245584 kb
Host smart-b78cf43f-2761-4bb4-ad10-116603e36fb1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1667758962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.1667758962
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.561226526
Short name T41
Test name
Test status
Simulation time 809978603 ps
CPU time 46.13 seconds
Started Apr 25 01:54:11 PM PDT 24
Finished Apr 25 01:54:58 PM PDT 24
Peak memory 248844 kb
Host smart-32684be0-187e-4992-960a-ab67ab904e81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56122
6526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.561226526
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.3664100758
Short name T760
Test name
Test status
Simulation time 15123153537 ps
CPU time 159.56 seconds
Started Apr 25 12:58:38 PM PDT 24
Finished Apr 25 01:01:20 PM PDT 24
Peak memory 240780 kb
Host smart-4e581b9c-60e2-4373-a1ba-601aa8a95ded
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3664100758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.3664100758
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.2797422488
Short name T190
Test name
Test status
Simulation time 855623968 ps
CPU time 101.52 seconds
Started Apr 25 12:58:46 PM PDT 24
Finished Apr 25 01:00:34 PM PDT 24
Peak memory 240656 kb
Host smart-1d90cb76-824d-4009-973b-b26edb6ac5bd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2797422488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.2797422488
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2842226102
Short name T706
Test name
Test status
Simulation time 139028580 ps
CPU time 5.65 seconds
Started Apr 25 12:58:34 PM PDT 24
Finished Apr 25 12:58:47 PM PDT 24
Peak memory 240580 kb
Host smart-adaf1c3f-28ef-4b2a-990c-f3d9e0553f93
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2842226102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.2842226102
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.1136492846
Short name T734
Test name
Test status
Simulation time 232928361 ps
CPU time 10.22 seconds
Started Apr 25 12:58:41 PM PDT 24
Finished Apr 25 12:58:54 PM PDT 24
Peak memory 256472 kb
Host smart-ee49bef2-775d-4a70-832e-5a544eee0f9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136492846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.1136492846
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.2979628574
Short name T192
Test name
Test status
Simulation time 138284074 ps
CPU time 4.7 seconds
Started Apr 25 12:58:49 PM PDT 24
Finished Apr 25 12:58:56 PM PDT 24
Peak memory 236236 kb
Host smart-762d49be-26ca-4d86-97fd-90dfb41b7d5c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2979628574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.2979628574
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.2423268382
Short name T791
Test name
Test status
Simulation time 8103752 ps
CPU time 1.57 seconds
Started Apr 25 12:58:51 PM PDT 24
Finished Apr 25 12:58:55 PM PDT 24
Peak memory 237208 kb
Host smart-c7a1b22f-1570-49fb-8898-54d0c0c61e86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2423268382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.2423268382
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.157339019
Short name T182
Test name
Test status
Simulation time 89233941 ps
CPU time 10.18 seconds
Started Apr 25 12:58:50 PM PDT 24
Finished Apr 25 12:59:02 PM PDT 24
Peak memory 244460 kb
Host smart-546f37fc-c86e-41b9-b6f5-d41ba1e39300
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=157339019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_outs
tanding.157339019
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.422080944
Short name T143
Test name
Test status
Simulation time 3937063705 ps
CPU time 143.76 seconds
Started Apr 25 12:58:46 PM PDT 24
Finished Apr 25 01:01:18 PM PDT 24
Peak memory 257484 kb
Host smart-c6aae8a5-5477-4505-b639-901c16496a75
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=422080944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_error
s.422080944
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.2393691718
Short name T721
Test name
Test status
Simulation time 333533514 ps
CPU time 10.47 seconds
Started Apr 25 12:58:17 PM PDT 24
Finished Apr 25 12:58:31 PM PDT 24
Peak memory 249268 kb
Host smart-6265a13e-31b5-435f-9012-c103b5f2bdda
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2393691718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.2393691718
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.3939516965
Short name T792
Test name
Test status
Simulation time 92234667 ps
CPU time 3.7 seconds
Started Apr 25 12:58:42 PM PDT 24
Finished Apr 25 12:58:48 PM PDT 24
Peak memory 237240 kb
Host smart-dcbe8fd8-6196-4f60-8ed7-f07061dbb7ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3939516965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.3939516965
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.4222564449
Short name T773
Test name
Test status
Simulation time 12289172302 ps
CPU time 237.63 seconds
Started Apr 25 12:58:41 PM PDT 24
Finished Apr 25 01:02:41 PM PDT 24
Peak memory 241016 kb
Host smart-aaee2d9c-0acb-4f34-873f-6a129852dc07
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4222564449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.4222564449
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.1943642146
Short name T723
Test name
Test status
Simulation time 8837387897 ps
CPU time 492.57 seconds
Started Apr 25 12:58:47 PM PDT 24
Finished Apr 25 01:07:02 PM PDT 24
Peak memory 239972 kb
Host smart-b0f508c0-2ffa-48c8-b444-960c634ab67b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1943642146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.1943642146
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.3188547278
Short name T796
Test name
Test status
Simulation time 55259274 ps
CPU time 4.91 seconds
Started Apr 25 12:58:40 PM PDT 24
Finished Apr 25 12:58:48 PM PDT 24
Peak memory 240640 kb
Host smart-2ed22fe9-a6ae-469f-89f6-59e8a97c7792
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3188547278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.3188547278
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.1361398887
Short name T727
Test name
Test status
Simulation time 62364741 ps
CPU time 7.63 seconds
Started Apr 25 12:58:39 PM PDT 24
Finished Apr 25 12:58:50 PM PDT 24
Peak memory 251192 kb
Host smart-923c461d-c45f-4298-b702-aba962b53791
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361398887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.1361398887
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.3641554726
Short name T189
Test name
Test status
Simulation time 304024135 ps
CPU time 3.42 seconds
Started Apr 25 12:58:40 PM PDT 24
Finished Apr 25 12:58:46 PM PDT 24
Peak memory 237128 kb
Host smart-1aa712de-913e-4174-91aa-efbd83ca55c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3641554726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.3641554726
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.3985025134
Short name T783
Test name
Test status
Simulation time 9984899 ps
CPU time 1.25 seconds
Started Apr 25 12:58:37 PM PDT 24
Finished Apr 25 12:58:40 PM PDT 24
Peak memory 236388 kb
Host smart-01150842-92e3-43ff-8098-c3f5603675a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3985025134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.3985025134
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.3145722267
Short name T718
Test name
Test status
Simulation time 679395864 ps
CPU time 23.7 seconds
Started Apr 25 12:58:43 PM PDT 24
Finished Apr 25 12:59:09 PM PDT 24
Peak memory 249028 kb
Host smart-4507b11d-9b4a-4dc4-8e0f-deba24866d2a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3145722267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.3145722267
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.768674245
Short name T152
Test name
Test status
Simulation time 2208533487 ps
CPU time 280.95 seconds
Started Apr 25 12:58:40 PM PDT 24
Finished Apr 25 01:03:24 PM PDT 24
Peak memory 268724 kb
Host smart-19888424-5c98-4ca2-a518-7a91051be9f4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768674245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.768674245
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.2861367980
Short name T228
Test name
Test status
Simulation time 597181878 ps
CPU time 10.16 seconds
Started Apr 25 12:58:40 PM PDT 24
Finished Apr 25 12:58:53 PM PDT 24
Peak memory 248852 kb
Host smart-ef77b20a-0e50-4be2-82c5-d323071773f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2861367980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.2861367980
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.2308314909
Short name T754
Test name
Test status
Simulation time 2182899675 ps
CPU time 8.26 seconds
Started Apr 25 12:58:36 PM PDT 24
Finished Apr 25 12:58:46 PM PDT 24
Peak memory 240896 kb
Host smart-0a6f69bc-dc4d-4485-b78c-24228744fb04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308314909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.2308314909
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.1613049304
Short name T779
Test name
Test status
Simulation time 188653218 ps
CPU time 7.61 seconds
Started Apr 25 12:58:47 PM PDT 24
Finished Apr 25 12:58:57 PM PDT 24
Peak memory 236304 kb
Host smart-5b5b5e59-bced-4183-a751-ace800cdac60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1613049304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.1613049304
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.483562870
Short name T700
Test name
Test status
Simulation time 9815808 ps
CPU time 1.34 seconds
Started Apr 25 12:58:38 PM PDT 24
Finished Apr 25 12:58:41 PM PDT 24
Peak memory 237264 kb
Host smart-f107d922-fe7b-41e4-bee4-4c34d8573a68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=483562870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.483562870
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.3360906319
Short name T816
Test name
Test status
Simulation time 703268083 ps
CPU time 45.19 seconds
Started Apr 25 12:58:55 PM PDT 24
Finished Apr 25 12:59:43 PM PDT 24
Peak memory 245372 kb
Host smart-d15e4b30-d779-43a0-88d3-d8648b0f8183
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3360906319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.3360906319
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.455526108
Short name T815
Test name
Test status
Simulation time 569174502 ps
CPU time 10.59 seconds
Started Apr 25 12:58:47 PM PDT 24
Finished Apr 25 12:59:00 PM PDT 24
Peak memory 248332 kb
Host smart-141b9041-8b3d-48d5-b27c-43ab676b74b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=455526108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.455526108
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.1745379332
Short name T812
Test name
Test status
Simulation time 156548721 ps
CPU time 19.58 seconds
Started Apr 25 12:59:00 PM PDT 24
Finished Apr 25 12:59:22 PM PDT 24
Peak memory 240792 kb
Host smart-29248097-024b-4e99-9efc-41bb10f0fe4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1745379332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.1745379332
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2993951802
Short name T819
Test name
Test status
Simulation time 151270414 ps
CPU time 6 seconds
Started Apr 25 12:58:38 PM PDT 24
Finished Apr 25 12:58:46 PM PDT 24
Peak memory 240860 kb
Host smart-6a15fdb7-5a7b-4266-b553-12adc1f70b9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993951802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.2993951802
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.1629965904
Short name T714
Test name
Test status
Simulation time 114245319 ps
CPU time 4.61 seconds
Started Apr 25 12:58:37 PM PDT 24
Finished Apr 25 12:58:43 PM PDT 24
Peak memory 236168 kb
Host smart-5993a34d-22f4-4456-8df8-7ab92ae2ec7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1629965904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.1629965904
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.346930593
Short name T750
Test name
Test status
Simulation time 4035624640 ps
CPU time 19.98 seconds
Started Apr 25 12:58:36 PM PDT 24
Finished Apr 25 12:58:58 PM PDT 24
Peak memory 244536 kb
Host smart-a99eb6c9-ffa2-4ab2-8433-1c5d8485a41d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=346930593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_out
standing.346930593
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.3160659397
Short name T134
Test name
Test status
Simulation time 14458898186 ps
CPU time 592.03 seconds
Started Apr 25 12:58:54 PM PDT 24
Finished Apr 25 01:08:49 PM PDT 24
Peak memory 265600 kb
Host smart-f29bde89-3dbf-43ad-8133-36ee5d95b293
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160659397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.3160659397
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.1503691192
Short name T741
Test name
Test status
Simulation time 162403252 ps
CPU time 11.46 seconds
Started Apr 25 12:58:46 PM PDT 24
Finished Apr 25 12:59:00 PM PDT 24
Peak memory 249060 kb
Host smart-08117f9c-8bac-4831-a932-05dd51f7b085
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1503691192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.1503691192
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.1545946836
Short name T823
Test name
Test status
Simulation time 54216474 ps
CPU time 4.55 seconds
Started Apr 25 12:58:54 PM PDT 24
Finished Apr 25 12:59:02 PM PDT 24
Peak memory 239364 kb
Host smart-a9a035a5-62b7-4f6c-a8f4-719d6bc034e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545946836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.1545946836
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.1156032117
Short name T704
Test name
Test status
Simulation time 90120360 ps
CPU time 5.71 seconds
Started Apr 25 12:58:49 PM PDT 24
Finished Apr 25 12:58:57 PM PDT 24
Peak memory 237164 kb
Host smart-dd3a59bf-285e-4aa7-b631-b9afd77cf0b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1156032117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.1156032117
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.3928389158
Short name T825
Test name
Test status
Simulation time 13877219 ps
CPU time 1.26 seconds
Started Apr 25 12:58:48 PM PDT 24
Finished Apr 25 12:58:52 PM PDT 24
Peak memory 237248 kb
Host smart-589b2e00-2944-4b80-8629-e870d7dc0b0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3928389158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.3928389158
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.1441024721
Short name T814
Test name
Test status
Simulation time 1922184109 ps
CPU time 35.45 seconds
Started Apr 25 12:59:17 PM PDT 24
Finished Apr 25 12:59:54 PM PDT 24
Peak memory 248952 kb
Host smart-b219d83b-a5e3-4ade-8414-0901df3e06ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1441024721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.1441024721
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.1460976465
Short name T127
Test name
Test status
Simulation time 35106896967 ps
CPU time 502.31 seconds
Started Apr 25 12:58:47 PM PDT 24
Finished Apr 25 01:07:12 PM PDT 24
Peak memory 269872 kb
Host smart-da9c8f86-4717-4196-aa62-f0c2b9dcf4ef
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460976465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.1460976465
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.483324704
Short name T780
Test name
Test status
Simulation time 244886027 ps
CPU time 16.21 seconds
Started Apr 25 12:58:57 PM PDT 24
Finished Apr 25 12:59:16 PM PDT 24
Peak memory 252336 kb
Host smart-66211622-84de-4d66-adc4-e17ff0ebe7fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=483324704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.483324704
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.360190689
Short name T827
Test name
Test status
Simulation time 209617849 ps
CPU time 7.71 seconds
Started Apr 25 12:59:09 PM PDT 24
Finished Apr 25 12:59:19 PM PDT 24
Peak memory 240048 kb
Host smart-cc1207e7-cda9-48fa-a1a5-5c706c69b831
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360190689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.alert_handler_csr_mem_rw_with_rand_reset.360190689
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.678352133
Short name T800
Test name
Test status
Simulation time 96010398 ps
CPU time 4.58 seconds
Started Apr 25 12:59:00 PM PDT 24
Finished Apr 25 12:59:07 PM PDT 24
Peak memory 239948 kb
Host smart-70b2686d-746c-45ee-9b8d-1bbe602cca09
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=678352133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.678352133
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.3012972605
Short name T744
Test name
Test status
Simulation time 533825496 ps
CPU time 37.03 seconds
Started Apr 25 12:59:17 PM PDT 24
Finished Apr 25 12:59:55 PM PDT 24
Peak memory 245436 kb
Host smart-729e361c-43d7-48e1-91e1-0d784ee69139
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3012972605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.3012972605
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.1766309764
Short name T161
Test name
Test status
Simulation time 1110333132 ps
CPU time 110.04 seconds
Started Apr 25 12:58:52 PM PDT 24
Finished Apr 25 01:00:44 PM PDT 24
Peak memory 266668 kb
Host smart-2b1e793e-05ef-4156-9163-bcaeec4ab20d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1766309764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.1766309764
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.239771316
Short name T733
Test name
Test status
Simulation time 301321842 ps
CPU time 18.45 seconds
Started Apr 25 12:59:16 PM PDT 24
Finished Apr 25 12:59:36 PM PDT 24
Peak memory 248812 kb
Host smart-d90602ec-7804-4b62-ac6b-7c135a5bfa46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=239771316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.239771316
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.1369775100
Short name T327
Test name
Test status
Simulation time 189323400 ps
CPU time 8.04 seconds
Started Apr 25 12:58:58 PM PDT 24
Finished Apr 25 12:59:09 PM PDT 24
Peak memory 237904 kb
Host smart-55e7ce77-9c26-4460-a4b8-2685cfb3b132
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369775100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.1369775100
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.697213695
Short name T736
Test name
Test status
Simulation time 22074115 ps
CPU time 3.34 seconds
Started Apr 25 12:58:44 PM PDT 24
Finished Apr 25 12:58:49 PM PDT 24
Peak memory 236228 kb
Host smart-3e17e50f-8f2f-4cad-a529-1046f6a76a3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=697213695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.697213695
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.360843720
Short name T225
Test name
Test status
Simulation time 12963521 ps
CPU time 1.63 seconds
Started Apr 25 12:58:54 PM PDT 24
Finished Apr 25 12:58:59 PM PDT 24
Peak memory 237248 kb
Host smart-9f5e450c-d5ab-4cab-a208-72cc1429d1e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=360843720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.360843720
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.527204931
Short name T767
Test name
Test status
Simulation time 256543445 ps
CPU time 17.5 seconds
Started Apr 25 12:58:52 PM PDT 24
Finished Apr 25 12:59:13 PM PDT 24
Peak memory 244448 kb
Host smart-909b0d0f-47bc-4418-98b1-bc33f531a0a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=527204931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_out
standing.527204931
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.2145803771
Short name T809
Test name
Test status
Simulation time 990119576 ps
CPU time 16.96 seconds
Started Apr 25 12:59:04 PM PDT 24
Finished Apr 25 12:59:23 PM PDT 24
Peak memory 254116 kb
Host smart-7620be25-7951-4255-8240-a8a83a3db4bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2145803771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.2145803771
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.1545050914
Short name T778
Test name
Test status
Simulation time 259781270 ps
CPU time 5.07 seconds
Started Apr 25 12:58:43 PM PDT 24
Finished Apr 25 12:58:50 PM PDT 24
Peak memory 240860 kb
Host smart-349001e6-08f4-40a0-8138-90dd1fda1a4a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545050914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.1545050914
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.764701036
Short name T777
Test name
Test status
Simulation time 64788141 ps
CPU time 3.57 seconds
Started Apr 25 12:58:52 PM PDT 24
Finished Apr 25 12:58:58 PM PDT 24
Peak memory 237188 kb
Host smart-97c89ee0-3d97-41c8-b2b4-c951a6cac88f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=764701036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.764701036
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.2673319327
Short name T323
Test name
Test status
Simulation time 26270000 ps
CPU time 1.4 seconds
Started Apr 25 12:58:55 PM PDT 24
Finished Apr 25 12:58:59 PM PDT 24
Peak memory 236344 kb
Host smart-b7b75d64-0f41-4640-9f15-9d602531609e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2673319327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.2673319327
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.452941274
Short name T775
Test name
Test status
Simulation time 179923848 ps
CPU time 11.96 seconds
Started Apr 25 12:58:58 PM PDT 24
Finished Apr 25 12:59:13 PM PDT 24
Peak memory 245408 kb
Host smart-beb49f2e-0d98-4102-b899-faa2b14ec479
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=452941274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_out
standing.452941274
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.3610089576
Short name T145
Test name
Test status
Simulation time 6569880008 ps
CPU time 133.65 seconds
Started Apr 25 12:58:43 PM PDT 24
Finished Apr 25 01:00:59 PM PDT 24
Peak memory 257508 kb
Host smart-de737961-6c87-467f-b7b3-00603cbacd24
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3610089576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.3610089576
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.1719107160
Short name T146
Test name
Test status
Simulation time 15769597218 ps
CPU time 287.85 seconds
Started Apr 25 12:58:59 PM PDT 24
Finished Apr 25 01:03:50 PM PDT 24
Peak memory 265640 kb
Host smart-3c05dfc0-dc22-44ef-a09e-4e5ea8aa063a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719107160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.1719107160
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.513245153
Short name T803
Test name
Test status
Simulation time 122870702 ps
CPU time 8.59 seconds
Started Apr 25 12:58:47 PM PDT 24
Finished Apr 25 12:58:58 PM PDT 24
Peak memory 254260 kb
Host smart-485e0a72-24f4-4368-a2c6-8be66f87d148
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=513245153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.513245153
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.3350808177
Short name T722
Test name
Test status
Simulation time 124772711 ps
CPU time 5.18 seconds
Started Apr 25 12:58:52 PM PDT 24
Finished Apr 25 12:58:59 PM PDT 24
Peak memory 256936 kb
Host smart-d997b24c-6eab-442d-acb2-367929592de8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350808177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.3350808177
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.1076190026
Short name T806
Test name
Test status
Simulation time 62805654 ps
CPU time 5.26 seconds
Started Apr 25 12:58:53 PM PDT 24
Finished Apr 25 12:59:02 PM PDT 24
Peak memory 237124 kb
Host smart-53875bc8-0ac3-490b-833d-1c661ecdddcd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1076190026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.1076190026
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.1049873971
Short name T770
Test name
Test status
Simulation time 7677713 ps
CPU time 1.3 seconds
Started Apr 25 12:58:58 PM PDT 24
Finished Apr 25 12:59:02 PM PDT 24
Peak memory 236336 kb
Host smart-0492536c-431e-4725-b92a-a34327a50a01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1049873971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.1049873971
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.1924512596
Short name T748
Test name
Test status
Simulation time 1277960896 ps
CPU time 43 seconds
Started Apr 25 12:58:59 PM PDT 24
Finished Apr 25 12:59:45 PM PDT 24
Peak memory 245436 kb
Host smart-0f3b4499-f2bf-4bb5-bf89-df2b8a60313d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1924512596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.1924512596
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.2474141285
Short name T136
Test name
Test status
Simulation time 2441535736 ps
CPU time 159.04 seconds
Started Apr 25 12:58:55 PM PDT 24
Finished Apr 25 01:01:37 PM PDT 24
Peak memory 266128 kb
Host smart-946ed58a-b806-4dee-b7cc-3113c89ea000
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2474141285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.2474141285
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.1513572151
Short name T755
Test name
Test status
Simulation time 322009372 ps
CPU time 9.59 seconds
Started Apr 25 12:59:14 PM PDT 24
Finished Apr 25 12:59:26 PM PDT 24
Peak memory 254500 kb
Host smart-4937b4a4-ac80-43e6-a339-a1602af879a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1513572151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.1513572151
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.2225919938
Short name T813
Test name
Test status
Simulation time 358039338 ps
CPU time 8.68 seconds
Started Apr 25 12:58:53 PM PDT 24
Finished Apr 25 12:59:05 PM PDT 24
Peak memory 257076 kb
Host smart-617dfd82-5d58-411c-a35a-256d79c1af0c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225919938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.2225919938
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.2085644835
Short name T737
Test name
Test status
Simulation time 126707010 ps
CPU time 4.48 seconds
Started Apr 25 12:58:47 PM PDT 24
Finished Apr 25 12:58:54 PM PDT 24
Peak memory 240696 kb
Host smart-77efde53-1488-4d59-a589-8e241165aa09
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2085644835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.2085644835
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.2650163740
Short name T711
Test name
Test status
Simulation time 70830352 ps
CPU time 1.48 seconds
Started Apr 25 12:59:13 PM PDT 24
Finished Apr 25 12:59:17 PM PDT 24
Peak memory 237260 kb
Host smart-e1e448a3-ed80-42d2-8cc3-6e5daec5b64f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2650163740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.2650163740
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.4210788816
Short name T191
Test name
Test status
Simulation time 171261770 ps
CPU time 22.28 seconds
Started Apr 25 12:58:53 PM PDT 24
Finished Apr 25 12:59:19 PM PDT 24
Peak memory 245432 kb
Host smart-1962eba8-c967-4f6b-bb74-6b46687d0b8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4210788816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.4210788816
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.2248102505
Short name T793
Test name
Test status
Simulation time 1095480592 ps
CPU time 17.82 seconds
Started Apr 25 12:59:01 PM PDT 24
Finished Apr 25 12:59:21 PM PDT 24
Peak memory 249048 kb
Host smart-d86d5d5c-ceb5-4ed8-ac07-1bfcc327eac8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2248102505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.2248102505
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.772221594
Short name T789
Test name
Test status
Simulation time 54512204 ps
CPU time 6.14 seconds
Started Apr 25 12:58:48 PM PDT 24
Finished Apr 25 12:58:56 PM PDT 24
Peak memory 241924 kb
Host smart-fee5274d-150a-4b19-90c4-26f3f2966ad8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772221594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.alert_handler_csr_mem_rw_with_rand_reset.772221594
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.342743703
Short name T808
Test name
Test status
Simulation time 519169933 ps
CPU time 8.97 seconds
Started Apr 25 12:59:13 PM PDT 24
Finished Apr 25 12:59:25 PM PDT 24
Peak memory 240712 kb
Host smart-0e4953c2-5233-416a-af46-749f66850c23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=342743703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.342743703
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.3352484768
Short name T782
Test name
Test status
Simulation time 10873345 ps
CPU time 1.3 seconds
Started Apr 25 12:58:54 PM PDT 24
Finished Apr 25 12:58:59 PM PDT 24
Peak memory 237244 kb
Host smart-79df8a81-1d66-404b-9fe5-0845987bd93c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3352484768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.3352484768
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.553740724
Short name T761
Test name
Test status
Simulation time 353074879 ps
CPU time 11.53 seconds
Started Apr 25 12:59:01 PM PDT 24
Finished Apr 25 12:59:15 PM PDT 24
Peak memory 245452 kb
Host smart-af0ea899-85e5-429f-a964-d8476cacf6d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=553740724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_out
standing.553740724
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.165250817
Short name T157
Test name
Test status
Simulation time 1696565600 ps
CPU time 206.61 seconds
Started Apr 25 12:59:05 PM PDT 24
Finished Apr 25 01:02:34 PM PDT 24
Peak memory 265624 kb
Host smart-f8b4708a-9811-4649-860f-226f07a52671
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=165250817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_erro
rs.165250817
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.3580160145
Short name T148
Test name
Test status
Simulation time 16969223609 ps
CPU time 588.3 seconds
Started Apr 25 12:58:56 PM PDT 24
Finished Apr 25 01:08:47 PM PDT 24
Peak memory 265724 kb
Host smart-22ee5967-d9e8-4106-a75f-c02745861c96
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580160145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.3580160145
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.3747861799
Short name T708
Test name
Test status
Simulation time 794102604 ps
CPU time 7.52 seconds
Started Apr 25 12:59:20 PM PDT 24
Finished Apr 25 12:59:28 PM PDT 24
Peak memory 247968 kb
Host smart-e36834a3-19ac-4a16-9117-670927f67b8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3747861799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.3747861799
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.4286796819
Short name T738
Test name
Test status
Simulation time 235822232 ps
CPU time 26.14 seconds
Started Apr 25 12:58:52 PM PDT 24
Finished Apr 25 12:59:21 PM PDT 24
Peak memory 240776 kb
Host smart-590e1c19-5652-4be2-8710-9adb42837417
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4286796819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.4286796819
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.1587029903
Short name T728
Test name
Test status
Simulation time 321021863 ps
CPU time 7.56 seconds
Started Apr 25 12:59:10 PM PDT 24
Finished Apr 25 12:59:20 PM PDT 24
Peak memory 241312 kb
Host smart-cee9a7aa-387e-437c-ad7f-1ed74f494632
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587029903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.1587029903
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.3939219438
Short name T769
Test name
Test status
Simulation time 52436250 ps
CPU time 3.57 seconds
Started Apr 25 12:58:58 PM PDT 24
Finished Apr 25 12:59:04 PM PDT 24
Peak memory 237180 kb
Host smart-5a907569-6586-4894-8ba3-4dc0ff0d86e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3939219438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.3939219438
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.2819968655
Short name T817
Test name
Test status
Simulation time 10067705 ps
CPU time 1.56 seconds
Started Apr 25 12:58:54 PM PDT 24
Finished Apr 25 12:58:59 PM PDT 24
Peak memory 237292 kb
Host smart-a3cdfed2-b83d-4a2f-bd18-3343b8a0e483
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2819968655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.2819968655
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.967572837
Short name T807
Test name
Test status
Simulation time 263358040 ps
CPU time 17.67 seconds
Started Apr 25 12:59:10 PM PDT 24
Finished Apr 25 12:59:30 PM PDT 24
Peak memory 245448 kb
Host smart-bd45bae0-f0a5-4b61-87a3-b2ace8840940
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=967572837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_out
standing.967572837
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.795173101
Short name T142
Test name
Test status
Simulation time 6578806226 ps
CPU time 350.78 seconds
Started Apr 25 12:59:02 PM PDT 24
Finished Apr 25 01:04:55 PM PDT 24
Peak memory 265752 kb
Host smart-3667bc35-d905-4679-901e-d57572ec9e81
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=795173101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_erro
rs.795173101
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.4010828755
Short name T802
Test name
Test status
Simulation time 206579837 ps
CPU time 13.55 seconds
Started Apr 25 12:59:06 PM PDT 24
Finished Apr 25 12:59:21 PM PDT 24
Peak memory 248980 kb
Host smart-49d09fae-d1fb-4058-a9f8-5f445e36f95b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4010828755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.4010828755
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.38244063
Short name T181
Test name
Test status
Simulation time 4501647859 ps
CPU time 138.86 seconds
Started Apr 25 12:58:49 PM PDT 24
Finished Apr 25 01:01:10 PM PDT 24
Peak memory 240804 kb
Host smart-a8287399-82c7-402a-bdce-f32587016e13
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=38244063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.38244063
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.1359182587
Short name T799
Test name
Test status
Simulation time 37175226724 ps
CPU time 518.8 seconds
Started Apr 25 12:58:46 PM PDT 24
Finished Apr 25 01:07:27 PM PDT 24
Peak memory 240704 kb
Host smart-86bff955-4cc5-4ce8-bb67-3c114d247518
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1359182587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.1359182587
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.2105269452
Short name T731
Test name
Test status
Simulation time 22396468 ps
CPU time 3.72 seconds
Started Apr 25 12:58:34 PM PDT 24
Finished Apr 25 12:58:40 PM PDT 24
Peak memory 240652 kb
Host smart-514a9dca-9d14-4680-9e85-1ffd0dbb2e5c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2105269452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.2105269452
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.3772025099
Short name T739
Test name
Test status
Simulation time 360308559 ps
CPU time 6.72 seconds
Started Apr 25 12:58:38 PM PDT 24
Finished Apr 25 12:58:46 PM PDT 24
Peak memory 240880 kb
Host smart-2f8696ca-3caf-487d-a8a0-f2adbe1cdbce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772025099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.3772025099
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.1875839201
Short name T797
Test name
Test status
Simulation time 34032085 ps
CPU time 3.14 seconds
Started Apr 25 12:58:48 PM PDT 24
Finished Apr 25 12:58:54 PM PDT 24
Peak memory 237164 kb
Host smart-35723806-54e4-40f3-80c3-4be41dbd133b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1875839201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.1875839201
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.3082202162
Short name T757
Test name
Test status
Simulation time 7919955 ps
CPU time 1.5 seconds
Started Apr 25 12:58:32 PM PDT 24
Finished Apr 25 12:58:36 PM PDT 24
Peak memory 236276 kb
Host smart-f6f4d872-aeac-45fe-a5d1-6a87d878830c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3082202162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.3082202162
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.1198414681
Short name T788
Test name
Test status
Simulation time 2004171985 ps
CPU time 33.29 seconds
Started Apr 25 12:58:48 PM PDT 24
Finished Apr 25 12:59:23 PM PDT 24
Peak memory 240812 kb
Host smart-a8339b91-638b-41b6-80a8-18412b1ddbe7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1198414681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.1198414681
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.3929846263
Short name T147
Test name
Test status
Simulation time 3286696322 ps
CPU time 95.33 seconds
Started Apr 25 12:58:38 PM PDT 24
Finished Apr 25 01:00:16 PM PDT 24
Peak memory 257488 kb
Host smart-5061a62e-9cb7-4a8d-a8be-3b1cd582813c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3929846263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.3929846263
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.622065702
Short name T229
Test name
Test status
Simulation time 1972090964 ps
CPU time 15.6 seconds
Started Apr 25 12:58:46 PM PDT 24
Finished Apr 25 12:59:05 PM PDT 24
Peak memory 249056 kb
Host smart-6c6dfae2-57dd-437c-968d-cfef25976fe0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=622065702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.622065702
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.2466255074
Short name T768
Test name
Test status
Simulation time 12588900 ps
CPU time 1.45 seconds
Started Apr 25 12:59:07 PM PDT 24
Finished Apr 25 12:59:10 PM PDT 24
Peak memory 237260 kb
Host smart-a3990d0c-bd3a-43e0-a928-93f7c858f4a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2466255074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.2466255074
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.2872287622
Short name T749
Test name
Test status
Simulation time 10310807 ps
CPU time 1.25 seconds
Started Apr 25 12:58:45 PM PDT 24
Finished Apr 25 12:58:48 PM PDT 24
Peak memory 236340 kb
Host smart-df9b0f0a-05ca-4df6-8488-eb5be5c43c72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2872287622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.2872287622
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.1298323325
Short name T764
Test name
Test status
Simulation time 14141756 ps
CPU time 1.68 seconds
Started Apr 25 12:59:09 PM PDT 24
Finished Apr 25 12:59:12 PM PDT 24
Peak memory 235312 kb
Host smart-3225f27a-1c20-49b0-b175-ba3f9b127184
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1298323325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.1298323325
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.586720033
Short name T324
Test name
Test status
Simulation time 21445275 ps
CPU time 2.06 seconds
Started Apr 25 12:58:52 PM PDT 24
Finished Apr 25 12:58:57 PM PDT 24
Peak memory 237252 kb
Host smart-cc8125aa-3f9f-45e4-a4ae-84fef8f49605
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=586720033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.586720033
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.4288209721
Short name T743
Test name
Test status
Simulation time 24576125 ps
CPU time 1.53 seconds
Started Apr 25 12:58:58 PM PDT 24
Finished Apr 25 12:59:03 PM PDT 24
Peak memory 237212 kb
Host smart-c77e0780-b4e0-43da-9c3e-24f257db7a43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4288209721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.4288209721
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.3820424302
Short name T712
Test name
Test status
Simulation time 11091273 ps
CPU time 1.56 seconds
Started Apr 25 12:59:02 PM PDT 24
Finished Apr 25 12:59:06 PM PDT 24
Peak memory 237268 kb
Host smart-7ceec135-c6ae-4d4e-b1c7-0821315fe6ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3820424302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.3820424302
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.430043078
Short name T794
Test name
Test status
Simulation time 9244391 ps
CPU time 1.41 seconds
Started Apr 25 12:59:05 PM PDT 24
Finished Apr 25 12:59:08 PM PDT 24
Peak memory 237256 kb
Host smart-6ca95dc7-fdb4-42ad-9965-b26e56800ca6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=430043078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.430043078
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.3911906513
Short name T735
Test name
Test status
Simulation time 86966937 ps
CPU time 1.4 seconds
Started Apr 25 12:59:16 PM PDT 24
Finished Apr 25 12:59:19 PM PDT 24
Peak memory 236212 kb
Host smart-7f7af58a-1fc6-4ccf-ad96-463be99c69cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3911906513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.3911906513
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.2504582311
Short name T821
Test name
Test status
Simulation time 8334518 ps
CPU time 1.5 seconds
Started Apr 25 12:59:08 PM PDT 24
Finished Apr 25 12:59:11 PM PDT 24
Peak memory 237272 kb
Host smart-fe40e30f-4f20-412c-bb84-ca91c4ecab34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2504582311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.2504582311
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.3444641599
Short name T742
Test name
Test status
Simulation time 4778820507 ps
CPU time 156.88 seconds
Started Apr 25 12:58:47 PM PDT 24
Finished Apr 25 01:01:27 PM PDT 24
Peak memory 240804 kb
Host smart-c5b7b3f5-3613-4993-bedc-171bef422656
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3444641599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.3444641599
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.2136929884
Short name T710
Test name
Test status
Simulation time 5714488660 ps
CPU time 169.37 seconds
Started Apr 25 12:58:38 PM PDT 24
Finished Apr 25 01:01:29 PM PDT 24
Peak memory 240732 kb
Host smart-2038fe10-1cd2-43ef-87c8-dd96841aeaf1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2136929884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.2136929884
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.675926533
Short name T717
Test name
Test status
Simulation time 335492731 ps
CPU time 4.98 seconds
Started Apr 25 12:58:40 PM PDT 24
Finished Apr 25 12:58:47 PM PDT 24
Peak memory 240720 kb
Host smart-82582927-9360-410d-bede-d93907ff86ba
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=675926533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.675926533
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.1592410146
Short name T716
Test name
Test status
Simulation time 943716213 ps
CPU time 7.28 seconds
Started Apr 25 12:58:50 PM PDT 24
Finished Apr 25 12:58:59 PM PDT 24
Peak memory 239220 kb
Host smart-46fac5d3-d705-4728-87f4-7ccf2f7d5652
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592410146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.1592410146
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.2079610025
Short name T724
Test name
Test status
Simulation time 990627833 ps
CPU time 5.09 seconds
Started Apr 25 12:58:44 PM PDT 24
Finished Apr 25 12:58:51 PM PDT 24
Peak memory 240032 kb
Host smart-77ea250c-e3ae-46d8-8811-8a64969af4ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2079610025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.2079610025
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.2357539871
Short name T762
Test name
Test status
Simulation time 19707421 ps
CPU time 1.19 seconds
Started Apr 25 12:58:32 PM PDT 24
Finished Apr 25 12:58:36 PM PDT 24
Peak memory 237148 kb
Host smart-411bc104-e653-4ef0-a297-48422572bcb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2357539871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.2357539871
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.634493274
Short name T705
Test name
Test status
Simulation time 865471198 ps
CPU time 12.38 seconds
Started Apr 25 12:58:44 PM PDT 24
Finished Apr 25 12:58:59 PM PDT 24
Peak memory 248988 kb
Host smart-f94b2f36-6834-460e-8e9b-99c8b22c8bf0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=634493274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_outs
tanding.634493274
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.1800345050
Short name T151
Test name
Test status
Simulation time 34655261246 ps
CPU time 356.64 seconds
Started Apr 25 12:58:40 PM PDT 24
Finished Apr 25 01:04:39 PM PDT 24
Peak memory 265712 kb
Host smart-6f6b197a-a9cd-4bf0-9749-4ae64c6ff2d2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1800345050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.1800345050
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.283455367
Short name T140
Test name
Test status
Simulation time 8080653823 ps
CPU time 493.42 seconds
Started Apr 25 12:58:33 PM PDT 24
Finished Apr 25 01:06:49 PM PDT 24
Peak memory 265704 kb
Host smart-bc4571ae-a514-4d9f-93b7-1f811f3bde28
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283455367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.283455367
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.2104895158
Short name T774
Test name
Test status
Simulation time 385770609 ps
CPU time 12.69 seconds
Started Apr 25 12:59:04 PM PDT 24
Finished Apr 25 12:59:19 PM PDT 24
Peak memory 249016 kb
Host smart-8ce6d6bb-510a-489a-9ee0-9ac0cefec830
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2104895158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.2104895158
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.1419981339
Short name T740
Test name
Test status
Simulation time 15392083 ps
CPU time 1.55 seconds
Started Apr 25 12:59:10 PM PDT 24
Finished Apr 25 12:59:14 PM PDT 24
Peak memory 237280 kb
Host smart-c7329835-e433-41a8-aed5-4ca96a469dd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1419981339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.1419981339
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.513730542
Short name T726
Test name
Test status
Simulation time 9626223 ps
CPU time 1.24 seconds
Started Apr 25 12:58:47 PM PDT 24
Finished Apr 25 12:58:51 PM PDT 24
Peak memory 235252 kb
Host smart-f986f108-6f82-4948-a489-9fcad84e9abc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=513730542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.513730542
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.1759289317
Short name T166
Test name
Test status
Simulation time 12674986 ps
CPU time 1.69 seconds
Started Apr 25 12:59:09 PM PDT 24
Finished Apr 25 12:59:12 PM PDT 24
Peak memory 235288 kb
Host smart-c3837b8e-047a-4f33-b8ee-465861743527
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1759289317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.1759289317
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.1228472443
Short name T811
Test name
Test status
Simulation time 46648540 ps
CPU time 1.34 seconds
Started Apr 25 12:58:53 PM PDT 24
Finished Apr 25 12:58:57 PM PDT 24
Peak memory 235144 kb
Host smart-eb58d9db-fbc1-4009-833b-c44c2738a06b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1228472443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.1228472443
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.3542041453
Short name T824
Test name
Test status
Simulation time 11204613 ps
CPU time 1.47 seconds
Started Apr 25 12:58:52 PM PDT 24
Finished Apr 25 12:58:56 PM PDT 24
Peak memory 235292 kb
Host smart-4896305b-3d7d-438c-9ff8-5362c4f6aabc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3542041453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.3542041453
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.1454275515
Short name T747
Test name
Test status
Simulation time 12866745 ps
CPU time 1.53 seconds
Started Apr 25 12:58:50 PM PDT 24
Finished Apr 25 12:58:53 PM PDT 24
Peak memory 236192 kb
Host smart-ca58f777-50e0-46ff-8f02-8544db07abe9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1454275515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.1454275515
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.824291523
Short name T325
Test name
Test status
Simulation time 9602122 ps
CPU time 1.52 seconds
Started Apr 25 12:59:17 PM PDT 24
Finished Apr 25 12:59:20 PM PDT 24
Peak memory 237264 kb
Host smart-bc7e7802-a0b7-4d7f-ba12-bb3f7cfad14e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=824291523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.824291523
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.560367908
Short name T709
Test name
Test status
Simulation time 17717898 ps
CPU time 1.36 seconds
Started Apr 25 12:59:00 PM PDT 24
Finished Apr 25 12:59:04 PM PDT 24
Peak memory 235324 kb
Host smart-b5a658c6-5fc1-4d40-9fe7-fe398262d419
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=560367908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.560367908
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.4268571929
Short name T167
Test name
Test status
Simulation time 10834778 ps
CPU time 1.56 seconds
Started Apr 25 12:59:01 PM PDT 24
Finished Apr 25 12:59:05 PM PDT 24
Peak memory 237308 kb
Host smart-5873d09f-4709-44d3-b721-99bfcd972ca8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4268571929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.4268571929
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.4064414639
Short name T798
Test name
Test status
Simulation time 20522925 ps
CPU time 1.54 seconds
Started Apr 25 12:58:56 PM PDT 24
Finished Apr 25 12:59:01 PM PDT 24
Peak memory 236348 kb
Host smart-a0450ea8-42ae-4e38-91dd-3795b39df66a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4064414639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.4064414639
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.3433301922
Short name T818
Test name
Test status
Simulation time 14986101012 ps
CPU time 291.96 seconds
Started Apr 25 12:58:47 PM PDT 24
Finished Apr 25 01:03:41 PM PDT 24
Peak memory 240720 kb
Host smart-aa4c18f6-e3d1-4538-b4fa-a2534bed0500
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3433301922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.3433301922
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.2472320841
Short name T781
Test name
Test status
Simulation time 23759289124 ps
CPU time 353.31 seconds
Started Apr 25 12:58:46 PM PDT 24
Finished Apr 25 01:04:42 PM PDT 24
Peak memory 236288 kb
Host smart-e3c08765-ffcf-44c6-a633-91155c6cd782
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2472320841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.2472320841
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.3562922493
Short name T715
Test name
Test status
Simulation time 442348170 ps
CPU time 8.25 seconds
Started Apr 25 12:58:53 PM PDT 24
Finished Apr 25 12:59:05 PM PDT 24
Peak memory 240728 kb
Host smart-d063277e-8ecf-4075-9769-1adaac543f99
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3562922493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.3562922493
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.2649522844
Short name T729
Test name
Test status
Simulation time 187318765 ps
CPU time 7.23 seconds
Started Apr 25 12:58:46 PM PDT 24
Finished Apr 25 12:58:56 PM PDT 24
Peak memory 240764 kb
Host smart-15ad7774-942b-4247-9b0b-890ab2bdb955
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649522844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.2649522844
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.4120226867
Short name T732
Test name
Test status
Simulation time 69642532 ps
CPU time 5.38 seconds
Started Apr 25 12:58:38 PM PDT 24
Finished Apr 25 12:58:45 PM PDT 24
Peak memory 237184 kb
Host smart-95b2535c-fd39-45c9-92e8-4ce42e3b4713
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4120226867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.4120226867
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.1507840905
Short name T756
Test name
Test status
Simulation time 8188427 ps
CPU time 1.45 seconds
Started Apr 25 12:58:32 PM PDT 24
Finished Apr 25 12:58:36 PM PDT 24
Peak memory 236336 kb
Host smart-06437798-9f42-4b08-b5a2-5e6376367589
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1507840905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.1507840905
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.3958261798
Short name T707
Test name
Test status
Simulation time 1062028291 ps
CPU time 36.13 seconds
Started Apr 25 12:58:46 PM PDT 24
Finished Apr 25 12:59:25 PM PDT 24
Peak memory 245704 kb
Host smart-bfdb11a6-743b-4f8f-979f-f17fa65d8a2a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3958261798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.3958261798
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.3530027079
Short name T128
Test name
Test status
Simulation time 1103062578 ps
CPU time 107.3 seconds
Started Apr 25 12:58:38 PM PDT 24
Finished Apr 25 01:00:27 PM PDT 24
Peak memory 265656 kb
Host smart-9384ceb8-c938-42a4-9cd3-72d1d2307176
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3530027079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.3530027079
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.3211917835
Short name T701
Test name
Test status
Simulation time 130453051 ps
CPU time 4.83 seconds
Started Apr 25 12:58:42 PM PDT 24
Finished Apr 25 12:58:49 PM PDT 24
Peak memory 247540 kb
Host smart-964f6824-1ad6-4c11-89ad-7b4ffe1f5820
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3211917835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.3211917835
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.3758776802
Short name T805
Test name
Test status
Simulation time 8664513 ps
CPU time 1.52 seconds
Started Apr 25 12:59:05 PM PDT 24
Finished Apr 25 12:59:08 PM PDT 24
Peak memory 236316 kb
Host smart-31f98c45-bd7b-43be-9345-73b4aac7a70d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3758776802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.3758776802
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.568265328
Short name T746
Test name
Test status
Simulation time 25056586 ps
CPU time 1.44 seconds
Started Apr 25 12:59:00 PM PDT 24
Finished Apr 25 12:59:04 PM PDT 24
Peak memory 237200 kb
Host smart-953e859a-0301-4c13-9674-e87ae75a9c14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=568265328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.568265328
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.1233495744
Short name T785
Test name
Test status
Simulation time 7419267 ps
CPU time 1.3 seconds
Started Apr 25 12:59:10 PM PDT 24
Finished Apr 25 12:59:13 PM PDT 24
Peak memory 237256 kb
Host smart-1eb2ee79-5624-4609-a185-ea900ed1e92a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1233495744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.1233495744
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.3162923512
Short name T787
Test name
Test status
Simulation time 22814695 ps
CPU time 1.34 seconds
Started Apr 25 12:58:53 PM PDT 24
Finished Apr 25 12:58:57 PM PDT 24
Peak memory 237276 kb
Host smart-7f5de360-605d-4bf2-98bd-0c111a0434dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3162923512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.3162923512
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.3448921115
Short name T703
Test name
Test status
Simulation time 8871700 ps
CPU time 1.34 seconds
Started Apr 25 12:59:01 PM PDT 24
Finished Apr 25 12:59:04 PM PDT 24
Peak memory 235368 kb
Host smart-939ea81d-0a75-4d9f-a241-de7565403520
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3448921115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.3448921115
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.1738796204
Short name T776
Test name
Test status
Simulation time 9213604 ps
CPU time 1.28 seconds
Started Apr 25 12:58:55 PM PDT 24
Finished Apr 25 12:58:59 PM PDT 24
Peak memory 235200 kb
Host smart-de0a9d89-1423-4354-9c1e-cf661dfc13a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1738796204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.1738796204
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.480733360
Short name T719
Test name
Test status
Simulation time 9063044 ps
CPU time 1.51 seconds
Started Apr 25 12:58:56 PM PDT 24
Finished Apr 25 12:59:01 PM PDT 24
Peak memory 236280 kb
Host smart-2bd4c794-8578-4f4a-aea1-6f00366f6997
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=480733360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.480733360
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.2663091220
Short name T804
Test name
Test status
Simulation time 9863509 ps
CPU time 1.45 seconds
Started Apr 25 12:58:58 PM PDT 24
Finished Apr 25 12:59:03 PM PDT 24
Peak memory 236336 kb
Host smart-de97dd45-03c6-4098-b811-207937653de6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2663091220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.2663091220
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.2718674737
Short name T730
Test name
Test status
Simulation time 14726852 ps
CPU time 1.52 seconds
Started Apr 25 12:59:01 PM PDT 24
Finished Apr 25 12:59:05 PM PDT 24
Peak memory 237240 kb
Host smart-3d56bbbe-3502-4397-93e6-8e0aa4fd9b5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2718674737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.2718674737
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.2362224814
Short name T713
Test name
Test status
Simulation time 14788095 ps
CPU time 1.31 seconds
Started Apr 25 12:59:04 PM PDT 24
Finished Apr 25 12:59:07 PM PDT 24
Peak memory 236256 kb
Host smart-e483172b-3003-4ad9-8d66-b2c2d9b5e602
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2362224814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.2362224814
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.1619924844
Short name T784
Test name
Test status
Simulation time 964820522 ps
CPU time 9.76 seconds
Started Apr 25 12:59:08 PM PDT 24
Finished Apr 25 12:59:19 PM PDT 24
Peak memory 242932 kb
Host smart-25902cfd-bde1-4a3e-ba6e-ae82c3d8c498
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619924844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.1619924844
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.3479626241
Short name T745
Test name
Test status
Simulation time 96229113 ps
CPU time 8.6 seconds
Started Apr 25 12:58:46 PM PDT 24
Finished Apr 25 12:58:57 PM PDT 24
Peak memory 237188 kb
Host smart-f04c61be-9769-419d-8528-f7b1cc1fab38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3479626241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.3479626241
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.3679888726
Short name T699
Test name
Test status
Simulation time 14524036 ps
CPU time 1.28 seconds
Started Apr 25 12:58:37 PM PDT 24
Finished Apr 25 12:58:40 PM PDT 24
Peak memory 236272 kb
Host smart-50092245-d271-4e6b-946c-df745dbfd74d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3679888726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.3679888726
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.352859215
Short name T753
Test name
Test status
Simulation time 493900440 ps
CPU time 36.46 seconds
Started Apr 25 12:58:43 PM PDT 24
Finished Apr 25 12:59:21 PM PDT 24
Peak memory 248988 kb
Host smart-f3ebacaa-4831-4465-a44b-3c234ff8641a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=352859215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_outs
tanding.352859215
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.565992254
Short name T159
Test name
Test status
Simulation time 17961891768 ps
CPU time 293.54 seconds
Started Apr 25 12:58:25 PM PDT 24
Finished Apr 25 01:03:21 PM PDT 24
Peak memory 265604 kb
Host smart-6e2a795d-b062-4440-8a7f-1ae4788e66db
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=565992254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_error
s.565992254
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.571677975
Short name T154
Test name
Test status
Simulation time 4271875722 ps
CPU time 294.32 seconds
Started Apr 25 12:58:46 PM PDT 24
Finished Apr 25 01:03:43 PM PDT 24
Peak memory 265672 kb
Host smart-153b942c-cf8d-4502-98ef-4de56e13fbea
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571677975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.571677975
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.2869947832
Short name T810
Test name
Test status
Simulation time 2361704792 ps
CPU time 17.88 seconds
Started Apr 25 12:58:52 PM PDT 24
Finished Apr 25 12:59:13 PM PDT 24
Peak memory 253520 kb
Host smart-6bf48e2d-b487-4b7e-adc8-f00835e72dbf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2869947832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.2869947832
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.1269096044
Short name T765
Test name
Test status
Simulation time 234055572 ps
CPU time 8.51 seconds
Started Apr 25 12:58:45 PM PDT 24
Finished Apr 25 12:58:56 PM PDT 24
Peak memory 238552 kb
Host smart-41c0dd07-f837-4e4c-a24a-a082d16e6e48
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269096044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.1269096044
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.1101755643
Short name T188
Test name
Test status
Simulation time 65055999 ps
CPU time 5.37 seconds
Started Apr 25 12:58:48 PM PDT 24
Finished Apr 25 12:58:56 PM PDT 24
Peak memory 237176 kb
Host smart-17754299-a820-4754-8edf-f914bef0c134
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1101755643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.1101755643
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.3558098995
Short name T702
Test name
Test status
Simulation time 30710531 ps
CPU time 1.44 seconds
Started Apr 25 12:58:53 PM PDT 24
Finished Apr 25 12:58:58 PM PDT 24
Peak memory 236336 kb
Host smart-1180feea-8395-43eb-9821-7162f4c2f0d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3558098995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.3558098995
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.1292498285
Short name T763
Test name
Test status
Simulation time 191997190 ps
CPU time 13.41 seconds
Started Apr 25 12:58:46 PM PDT 24
Finished Apr 25 12:59:02 PM PDT 24
Peak memory 249012 kb
Host smart-e9ac00a6-6d4f-4d42-b62e-89ed39d55ba1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1292498285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.1292498285
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.3097604404
Short name T158
Test name
Test status
Simulation time 11077227256 ps
CPU time 173.6 seconds
Started Apr 25 12:58:35 PM PDT 24
Finished Apr 25 01:01:31 PM PDT 24
Peak memory 265676 kb
Host smart-5a1d4607-7248-4a48-bcf0-095e40c04a5c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3097604404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.3097604404
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.2798029595
Short name T153
Test name
Test status
Simulation time 8822624112 ps
CPU time 447.72 seconds
Started Apr 25 12:58:46 PM PDT 24
Finished Apr 25 01:06:17 PM PDT 24
Peak memory 265668 kb
Host smart-c46087c5-4ae6-4033-ab26-d0b583b7a468
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798029595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.2798029595
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.176690158
Short name T720
Test name
Test status
Simulation time 238126488 ps
CPU time 17.51 seconds
Started Apr 25 12:58:38 PM PDT 24
Finished Apr 25 12:58:57 PM PDT 24
Peak memory 253736 kb
Host smart-a5d9a13d-72b5-487c-9c49-d367daec18b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=176690158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.176690158
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.2343529926
Short name T179
Test name
Test status
Simulation time 64903435 ps
CPU time 4.95 seconds
Started Apr 25 12:58:37 PM PDT 24
Finished Apr 25 12:58:44 PM PDT 24
Peak memory 239404 kb
Host smart-db8ff358-dd44-4c30-b4f4-1d83bdf0e822
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343529926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.2343529926
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.1710795105
Short name T752
Test name
Test status
Simulation time 116845313 ps
CPU time 5.12 seconds
Started Apr 25 12:58:44 PM PDT 24
Finished Apr 25 12:58:51 PM PDT 24
Peak memory 237176 kb
Host smart-7ee2b218-149d-4969-b308-5501fbf48d4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1710795105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.1710795105
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.1899392495
Short name T766
Test name
Test status
Simulation time 11597002 ps
CPU time 1.42 seconds
Started Apr 25 12:59:02 PM PDT 24
Finished Apr 25 12:59:05 PM PDT 24
Peak memory 236244 kb
Host smart-484e8746-82a6-4f8f-bb99-f9c9fb247e45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1899392495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.1899392495
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.1306242395
Short name T725
Test name
Test status
Simulation time 309808384 ps
CPU time 19.02 seconds
Started Apr 25 12:58:57 PM PDT 24
Finished Apr 25 12:59:19 PM PDT 24
Peak memory 244440 kb
Host smart-5fcaf428-7dc7-48fe-8047-8337fd727bd2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1306242395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.1306242395
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.3740659041
Short name T125
Test name
Test status
Simulation time 34045136268 ps
CPU time 584.77 seconds
Started Apr 25 12:58:44 PM PDT 24
Finished Apr 25 01:08:31 PM PDT 24
Peak memory 265696 kb
Host smart-fbeca5b7-1657-485d-9b1d-c1c4d336e3b2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740659041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.3740659041
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.4271013989
Short name T820
Test name
Test status
Simulation time 44279541 ps
CPU time 5.84 seconds
Started Apr 25 12:58:44 PM PDT 24
Finished Apr 25 12:58:52 PM PDT 24
Peak memory 253692 kb
Host smart-17d44d71-4c9e-4d38-ae6e-78b153b4f433
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4271013989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.4271013989
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3836984982
Short name T786
Test name
Test status
Simulation time 127222054 ps
CPU time 5.43 seconds
Started Apr 25 12:58:55 PM PDT 24
Finished Apr 25 12:59:03 PM PDT 24
Peak memory 238464 kb
Host smart-879bc2a5-a325-4865-be31-0f019acf1618
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836984982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.3836984982
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.3444613169
Short name T759
Test name
Test status
Simulation time 22646655 ps
CPU time 3.47 seconds
Started Apr 25 12:58:46 PM PDT 24
Finished Apr 25 12:58:52 PM PDT 24
Peak memory 237180 kb
Host smart-403ce845-259d-406b-b8d8-aeba22c66a64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3444613169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.3444613169
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.847455795
Short name T790
Test name
Test status
Simulation time 10349277 ps
CPU time 1.51 seconds
Started Apr 25 12:58:48 PM PDT 24
Finished Apr 25 12:58:52 PM PDT 24
Peak memory 237256 kb
Host smart-598e25bb-c302-43c0-bcfa-2fb5f25559cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=847455795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.847455795
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.299490665
Short name T758
Test name
Test status
Simulation time 672604095 ps
CPU time 42.17 seconds
Started Apr 25 12:58:53 PM PDT 24
Finished Apr 25 12:59:39 PM PDT 24
Peak memory 245436 kb
Host smart-4c0903d1-1fbe-42ee-9225-81e758c0d087
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=299490665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_outs
tanding.299490665
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.2580874672
Short name T162
Test name
Test status
Simulation time 12071343739 ps
CPU time 440.42 seconds
Started Apr 25 12:59:00 PM PDT 24
Finished Apr 25 01:06:23 PM PDT 24
Peak memory 265736 kb
Host smart-6eb553ab-2b08-4839-90ab-792f7023b709
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580874672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.2580874672
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.4075950200
Short name T771
Test name
Test status
Simulation time 299027163 ps
CPU time 9.1 seconds
Started Apr 25 12:58:40 PM PDT 24
Finished Apr 25 12:58:52 PM PDT 24
Peak memory 248272 kb
Host smart-0470b969-e87e-40d4-a550-adacb1a28116
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4075950200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.4075950200
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.2635156214
Short name T826
Test name
Test status
Simulation time 323983371 ps
CPU time 5.61 seconds
Started Apr 25 12:58:41 PM PDT 24
Finished Apr 25 12:58:49 PM PDT 24
Peak memory 257224 kb
Host smart-d0c661e0-1993-4f09-82d9-681c18a1eb53
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635156214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.2635156214
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.1629166979
Short name T795
Test name
Test status
Simulation time 20579498 ps
CPU time 3.45 seconds
Started Apr 25 12:58:58 PM PDT 24
Finished Apr 25 12:59:04 PM PDT 24
Peak memory 237104 kb
Host smart-642cabbb-5df2-445d-902e-6a212c2bae43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1629166979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.1629166979
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.3541473436
Short name T772
Test name
Test status
Simulation time 24529463 ps
CPU time 1.43 seconds
Started Apr 25 12:59:19 PM PDT 24
Finished Apr 25 12:59:22 PM PDT 24
Peak memory 237272 kb
Host smart-9a3511c1-ed90-40f9-9bc7-cf0cc0d07489
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3541473436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.3541473436
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1885555136
Short name T801
Test name
Test status
Simulation time 181184876 ps
CPU time 20.31 seconds
Started Apr 25 12:58:50 PM PDT 24
Finished Apr 25 12:59:13 PM PDT 24
Peak memory 244512 kb
Host smart-9f7bee8e-1018-4614-af59-db1142de2b9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1885555136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.1885555136
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.2609440383
Short name T126
Test name
Test status
Simulation time 10956764984 ps
CPU time 153.27 seconds
Started Apr 25 12:58:32 PM PDT 24
Finished Apr 25 01:01:07 PM PDT 24
Peak memory 265716 kb
Host smart-ac035b98-ddfa-4264-9cde-e75e1c266112
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2609440383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.2609440383
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.2081343285
Short name T129
Test name
Test status
Simulation time 2753501196 ps
CPU time 318.34 seconds
Started Apr 25 12:59:03 PM PDT 24
Finished Apr 25 01:04:24 PM PDT 24
Peak memory 265748 kb
Host smart-c4951608-5490-45f6-8327-51f2f5c754ef
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081343285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.2081343285
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.4075568601
Short name T751
Test name
Test status
Simulation time 456500770 ps
CPU time 27.56 seconds
Started Apr 25 12:58:51 PM PDT 24
Finished Apr 25 12:59:20 PM PDT 24
Peak memory 249236 kb
Host smart-46018954-0e66-443c-982a-18e89bea60ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4075568601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.4075568601
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.3911875097
Short name T164
Test name
Test status
Simulation time 1335364855 ps
CPU time 81.48 seconds
Started Apr 25 12:58:49 PM PDT 24
Finished Apr 25 01:00:13 PM PDT 24
Peak memory 237448 kb
Host smart-e0c270c8-708b-463e-b4b0-6d1eb6706195
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3911875097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.3911875097
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.1182294080
Short name T104
Test name
Test status
Simulation time 147389628494 ps
CPU time 2363.1 seconds
Started Apr 25 01:52:19 PM PDT 24
Finished Apr 25 02:31:43 PM PDT 24
Peak memory 289112 kb
Host smart-40871054-7bea-47ad-96b2-40e18d9764d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182294080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.1182294080
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.2293077239
Short name T492
Test name
Test status
Simulation time 2523728415 ps
CPU time 17.34 seconds
Started Apr 25 01:52:31 PM PDT 24
Finished Apr 25 01:52:49 PM PDT 24
Peak memory 240548 kb
Host smart-a4f61038-ff77-4824-8156-d1a1906aad65
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2293077239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.2293077239
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.3687095494
Short name T375
Test name
Test status
Simulation time 20806633368 ps
CPU time 277.65 seconds
Started Apr 25 01:52:16 PM PDT 24
Finished Apr 25 01:56:55 PM PDT 24
Peak memory 250968 kb
Host smart-b0c45ca7-4a75-46e8-9c25-be4c66c545b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36870
95494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.3687095494
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.2923809514
Short name T595
Test name
Test status
Simulation time 704871948 ps
CPU time 31.87 seconds
Started Apr 25 01:52:17 PM PDT 24
Finished Apr 25 01:52:50 PM PDT 24
Peak memory 248720 kb
Host smart-2585c603-169c-48f8-b560-abd6554cfc23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29238
09514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.2923809514
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.3240580573
Short name T313
Test name
Test status
Simulation time 14371347270 ps
CPU time 1142.24 seconds
Started Apr 25 01:52:17 PM PDT 24
Finished Apr 25 02:11:20 PM PDT 24
Peak memory 284116 kb
Host smart-9477b2c3-a47d-47a2-8e98-78316fa9deab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240580573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.3240580573
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.49756313
Short name T676
Test name
Test status
Simulation time 182558203633 ps
CPU time 2900.37 seconds
Started Apr 25 01:52:19 PM PDT 24
Finished Apr 25 02:40:40 PM PDT 24
Peak memory 289584 kb
Host smart-32b1ad56-37dd-4925-8875-7d9393b1b5fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49756313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.49756313
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.213885223
Short name T56
Test name
Test status
Simulation time 125098522 ps
CPU time 13.12 seconds
Started Apr 25 01:52:17 PM PDT 24
Finished Apr 25 01:52:31 PM PDT 24
Peak memory 248680 kb
Host smart-a924affe-c946-45fe-994e-3085be35fa96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21388
5223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.213885223
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.401675197
Short name T591
Test name
Test status
Simulation time 3478957111 ps
CPU time 54.73 seconds
Started Apr 25 01:52:20 PM PDT 24
Finished Apr 25 01:53:15 PM PDT 24
Peak memory 255400 kb
Host smart-c86d9905-d168-49e1-87e8-627ea0e78cdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40167
5197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.401675197
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.535890352
Short name T682
Test name
Test status
Simulation time 118004571 ps
CPU time 13.05 seconds
Started Apr 25 01:52:17 PM PDT 24
Finished Apr 25 01:52:30 PM PDT 24
Peak memory 248716 kb
Host smart-12ebd6f0-8f4b-4c48-b171-c13ca1af684b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53589
0352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.535890352
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.1270354949
Short name T512
Test name
Test status
Simulation time 520741193 ps
CPU time 28.64 seconds
Started Apr 25 01:52:18 PM PDT 24
Finished Apr 25 01:52:47 PM PDT 24
Peak memory 248720 kb
Host smart-aa7513f6-3ca1-490c-a0ca-3eba68a40c69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12703
54949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.1270354949
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.865573774
Short name T23
Test name
Test status
Simulation time 9383812759 ps
CPU time 940.31 seconds
Started Apr 25 01:52:20 PM PDT 24
Finished Apr 25 02:08:01 PM PDT 24
Peak memory 289316 kb
Host smart-df86ef42-bcf2-44e0-865f-7175c03ad3ee
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865573774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_hand
ler_stress_all.865573774
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.2424732066
Short name T445
Test name
Test status
Simulation time 44853753127 ps
CPU time 2515.7 seconds
Started Apr 25 01:52:30 PM PDT 24
Finished Apr 25 02:34:27 PM PDT 24
Peak memory 284760 kb
Host smart-f9d13990-a50e-4aa8-a508-a9a17d00869d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424732066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.2424732066
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.3424039324
Short name T659
Test name
Test status
Simulation time 225737253 ps
CPU time 7.08 seconds
Started Apr 25 01:52:32 PM PDT 24
Finished Apr 25 01:52:39 PM PDT 24
Peak memory 240424 kb
Host smart-a32a80c1-5b21-426d-af0d-ce7cf40de626
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3424039324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.3424039324
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.142701973
Short name T587
Test name
Test status
Simulation time 22393775704 ps
CPU time 303.56 seconds
Started Apr 25 01:52:21 PM PDT 24
Finished Apr 25 01:57:25 PM PDT 24
Peak memory 256888 kb
Host smart-a0498a3d-9174-4efb-a385-1058b32409a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14270
1973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.142701973
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.664179809
Short name T27
Test name
Test status
Simulation time 91725885 ps
CPU time 9.65 seconds
Started Apr 25 01:52:31 PM PDT 24
Finished Apr 25 01:52:41 PM PDT 24
Peak memory 248760 kb
Host smart-82c47cf5-075d-4660-80b1-bc6b74df4a25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66417
9809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.664179809
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.3893318966
Short name T38
Test name
Test status
Simulation time 15988764571 ps
CPU time 1388.02 seconds
Started Apr 25 01:52:23 PM PDT 24
Finished Apr 25 02:15:32 PM PDT 24
Peak memory 288996 kb
Host smart-13c81088-1e92-463a-a0c1-a4f61b0c81f3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893318966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.3893318966
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.3862710188
Short name T77
Test name
Test status
Simulation time 20648482961 ps
CPU time 1426.62 seconds
Started Apr 25 01:52:22 PM PDT 24
Finished Apr 25 02:16:09 PM PDT 24
Peak memory 289252 kb
Host smart-5f10ff25-c641-4028-be9f-c9e03a06deb2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862710188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.3862710188
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.1767717473
Short name T493
Test name
Test status
Simulation time 174932761 ps
CPU time 16.76 seconds
Started Apr 25 01:52:23 PM PDT 24
Finished Apr 25 01:52:41 PM PDT 24
Peak memory 248716 kb
Host smart-587c09f9-c115-44ba-a212-194c8f964a2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17677
17473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.1767717473
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.4168316112
Short name T454
Test name
Test status
Simulation time 88642259 ps
CPU time 6.7 seconds
Started Apr 25 01:52:22 PM PDT 24
Finished Apr 25 01:52:29 PM PDT 24
Peak memory 248712 kb
Host smart-648f85f9-4886-44b0-8e78-ab998b24027c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41683
16112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.4168316112
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.1169468412
Short name T338
Test name
Test status
Simulation time 152381286 ps
CPU time 3.99 seconds
Started Apr 25 01:52:29 PM PDT 24
Finished Apr 25 01:52:33 PM PDT 24
Peak memory 240488 kb
Host smart-4cb10581-0817-4611-91b8-8966e9a870d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11694
68412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.1169468412
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.1302824752
Short name T95
Test name
Test status
Simulation time 67164667066 ps
CPU time 2257.27 seconds
Started Apr 25 01:52:32 PM PDT 24
Finished Apr 25 02:30:10 PM PDT 24
Peak memory 289028 kb
Host smart-d50e19e0-a9d3-44f5-879c-c2d3595cfa14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302824752 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.1302824752
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.3569485337
Short name T204
Test name
Test status
Simulation time 28906964 ps
CPU time 2.62 seconds
Started Apr 25 01:53:18 PM PDT 24
Finished Apr 25 01:53:21 PM PDT 24
Peak memory 248792 kb
Host smart-905bff85-056a-407d-bc80-5bc7693ee31c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3569485337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.3569485337
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.4069198055
Short name T457
Test name
Test status
Simulation time 29362669288 ps
CPU time 681.1 seconds
Started Apr 25 01:53:13 PM PDT 24
Finished Apr 25 02:04:34 PM PDT 24
Peak memory 265180 kb
Host smart-93b42d78-cda5-43d3-a027-7740d521a61e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069198055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.4069198055
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.1445124999
Short name T114
Test name
Test status
Simulation time 4527679107 ps
CPU time 41.23 seconds
Started Apr 25 01:53:16 PM PDT 24
Finished Apr 25 01:53:58 PM PDT 24
Peak memory 240568 kb
Host smart-b311a03f-3224-44e6-a2a8-5dda05105aea
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1445124999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.1445124999
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.994253516
Short name T272
Test name
Test status
Simulation time 782475079 ps
CPU time 45.55 seconds
Started Apr 25 01:53:13 PM PDT 24
Finished Apr 25 01:53:59 PM PDT 24
Peak memory 249016 kb
Host smart-40b61ae3-c440-4f7d-83f9-874da3071dec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99425
3516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.994253516
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.3556458818
Short name T382
Test name
Test status
Simulation time 4568922366 ps
CPU time 69.66 seconds
Started Apr 25 01:53:12 PM PDT 24
Finished Apr 25 01:54:23 PM PDT 24
Peak memory 248848 kb
Host smart-11a27a08-d13e-4b83-bcd9-b0022d36fef6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35564
58818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.3556458818
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.1220447102
Short name T119
Test name
Test status
Simulation time 29525213660 ps
CPU time 314.65 seconds
Started Apr 25 01:53:11 PM PDT 24
Finished Apr 25 01:58:27 PM PDT 24
Peak memory 248272 kb
Host smart-54623b3f-ab31-41ef-ac97-198317cdde74
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220447102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.1220447102
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.2413266431
Short name T10
Test name
Test status
Simulation time 357729198 ps
CPU time 17.76 seconds
Started Apr 25 01:53:15 PM PDT 24
Finished Apr 25 01:53:33 PM PDT 24
Peak memory 248640 kb
Host smart-aa87b3c8-a06f-4627-a4c7-5659a300c055
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24132
66431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.2413266431
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.4134929861
Short name T61
Test name
Test status
Simulation time 745032997 ps
CPU time 42.11 seconds
Started Apr 25 01:53:14 PM PDT 24
Finished Apr 25 01:53:57 PM PDT 24
Peak memory 255372 kb
Host smart-d112e8a2-7562-4b3f-9690-1879a453c480
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41349
29861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.4134929861
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.3617692736
Short name T647
Test name
Test status
Simulation time 154400487 ps
CPU time 6.32 seconds
Started Apr 25 01:53:14 PM PDT 24
Finished Apr 25 01:53:21 PM PDT 24
Peak memory 240452 kb
Host smart-96069ce6-428e-4895-ba97-4ce690988a00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36176
92736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.3617692736
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.1514135052
Short name T542
Test name
Test status
Simulation time 657328071 ps
CPU time 25.67 seconds
Started Apr 25 01:53:14 PM PDT 24
Finished Apr 25 01:53:40 PM PDT 24
Peak memory 248680 kb
Host smart-aebe4666-fc98-4a78-9181-13ad30d59e91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15141
35052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.1514135052
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.3486099030
Short name T236
Test name
Test status
Simulation time 1935603414 ps
CPU time 88.41 seconds
Started Apr 25 01:53:20 PM PDT 24
Finished Apr 25 01:54:49 PM PDT 24
Peak memory 250676 kb
Host smart-6a0264fd-9cea-4f2b-98cb-0b2ff22eebe2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486099030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.3486099030
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.1705393879
Short name T197
Test name
Test status
Simulation time 80235936 ps
CPU time 2.97 seconds
Started Apr 25 01:53:22 PM PDT 24
Finished Apr 25 01:53:26 PM PDT 24
Peak memory 248872 kb
Host smart-12798d3f-4cab-4449-8d57-70cea3d0db73
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1705393879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.1705393879
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.4007500161
Short name T641
Test name
Test status
Simulation time 27224330270 ps
CPU time 944.38 seconds
Started Apr 25 01:53:15 PM PDT 24
Finished Apr 25 02:09:00 PM PDT 24
Peak memory 282904 kb
Host smart-010cfcba-a7d1-41dc-b3c0-9870ec391ea6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007500161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.4007500161
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.270887143
Short name T393
Test name
Test status
Simulation time 1609445738 ps
CPU time 65.14 seconds
Started Apr 25 01:53:22 PM PDT 24
Finished Apr 25 01:54:28 PM PDT 24
Peak memory 248696 kb
Host smart-35e54bc7-0c56-4a06-b888-1b636b94a5af
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=270887143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.270887143
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.1557449642
Short name T348
Test name
Test status
Simulation time 2131897922 ps
CPU time 79.83 seconds
Started Apr 25 01:53:17 PM PDT 24
Finished Apr 25 01:54:37 PM PDT 24
Peak memory 256768 kb
Host smart-20ed4c2e-963e-4d5f-a5e8-45058bf3fc03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15574
49642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.1557449642
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.3170323711
Short name T25
Test name
Test status
Simulation time 2169312697 ps
CPU time 60.59 seconds
Started Apr 25 01:53:16 PM PDT 24
Finished Apr 25 01:54:17 PM PDT 24
Peak memory 256916 kb
Host smart-1ba13de3-d968-4f77-bdd8-98ecf853ac23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31703
23711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.3170323711
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.2948121967
Short name T508
Test name
Test status
Simulation time 48527165227 ps
CPU time 674.54 seconds
Started Apr 25 01:53:23 PM PDT 24
Finished Apr 25 02:04:38 PM PDT 24
Peak memory 272692 kb
Host smart-4f698d49-8641-418c-8535-766815526ce7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948121967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.2948121967
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.410525062
Short name T281
Test name
Test status
Simulation time 7201081558 ps
CPU time 285.43 seconds
Started Apr 25 01:53:16 PM PDT 24
Finished Apr 25 01:58:03 PM PDT 24
Peak memory 248176 kb
Host smart-e49a7f7c-f4bb-4303-a0a8-6a41c9ca3877
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410525062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.410525062
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.1053865695
Short name T472
Test name
Test status
Simulation time 1321354666 ps
CPU time 18.31 seconds
Started Apr 25 01:53:18 PM PDT 24
Finished Apr 25 01:53:37 PM PDT 24
Peak memory 248636 kb
Host smart-9245be50-e461-4eca-93fe-7df647cea37f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10538
65695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.1053865695
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.2057835892
Short name T371
Test name
Test status
Simulation time 224702610 ps
CPU time 20.53 seconds
Started Apr 25 01:53:17 PM PDT 24
Finished Apr 25 01:53:38 PM PDT 24
Peak memory 248748 kb
Host smart-68b88123-1876-4f2d-bc18-bc9eb33566ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20578
35892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.2057835892
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.3328002145
Short name T684
Test name
Test status
Simulation time 697667246 ps
CPU time 39.46 seconds
Started Apr 25 01:53:21 PM PDT 24
Finished Apr 25 01:54:01 PM PDT 24
Peak memory 255672 kb
Host smart-9f4929b4-7bfc-4c0a-8dd6-2386462fca5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33280
02145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.3328002145
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.2472011529
Short name T503
Test name
Test status
Simulation time 699900591 ps
CPU time 49.2 seconds
Started Apr 25 01:53:31 PM PDT 24
Finished Apr 25 01:54:20 PM PDT 24
Peak memory 248688 kb
Host smart-bc2a800b-6e2a-4ae2-b020-36959153e555
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24720
11529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.2472011529
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.1314280315
Short name T68
Test name
Test status
Simulation time 47721832517 ps
CPU time 4111.1 seconds
Started Apr 25 01:53:24 PM PDT 24
Finished Apr 25 03:01:56 PM PDT 24
Peak memory 330780 kb
Host smart-74deeb73-b13f-4285-b10c-66aa7b4a0a91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314280315 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.1314280315
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.2453063055
Short name T207
Test name
Test status
Simulation time 57178502 ps
CPU time 4.35 seconds
Started Apr 25 01:53:30 PM PDT 24
Finished Apr 25 01:53:34 PM PDT 24
Peak memory 248908 kb
Host smart-c93b37c2-06f8-4313-8bbf-b13c0dc3162a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2453063055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.2453063055
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.174275728
Short name T481
Test name
Test status
Simulation time 45678406078 ps
CPU time 1168.58 seconds
Started Apr 25 01:53:30 PM PDT 24
Finished Apr 25 02:12:59 PM PDT 24
Peak memory 273340 kb
Host smart-c5ce4f6b-a2c5-414f-9db7-c0dac258aeea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174275728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.174275728
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.1220414261
Short name T372
Test name
Test status
Simulation time 6146315871 ps
CPU time 22.68 seconds
Started Apr 25 01:53:30 PM PDT 24
Finished Apr 25 01:53:53 PM PDT 24
Peak memory 248824 kb
Host smart-dbc7893c-6309-4530-af2b-c0c40ce072ff
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1220414261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.1220414261
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.3959769785
Short name T528
Test name
Test status
Simulation time 1219678500 ps
CPU time 58.02 seconds
Started Apr 25 01:53:23 PM PDT 24
Finished Apr 25 01:54:22 PM PDT 24
Peak memory 256628 kb
Host smart-385e7afe-2cd8-4d34-ba98-9752bebb4fcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39597
69785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.3959769785
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.4260109726
Short name T516
Test name
Test status
Simulation time 549023703 ps
CPU time 24.28 seconds
Started Apr 25 01:53:25 PM PDT 24
Finished Apr 25 01:53:50 PM PDT 24
Peak memory 255884 kb
Host smart-eeffadde-f756-4372-a6b4-50ff409ead94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42601
09726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.4260109726
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.959324376
Short name T544
Test name
Test status
Simulation time 52304083843 ps
CPU time 1136.34 seconds
Started Apr 25 01:53:32 PM PDT 24
Finished Apr 25 02:12:29 PM PDT 24
Peak memory 289092 kb
Host smart-4b0da1f8-c522-4c01-abae-1f03e603bdad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959324376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.959324376
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.1236434588
Short name T547
Test name
Test status
Simulation time 109765811561 ps
CPU time 1636.86 seconds
Started Apr 25 01:53:28 PM PDT 24
Finished Apr 25 02:20:45 PM PDT 24
Peak memory 272884 kb
Host smart-ea00374a-725a-4e88-ae0b-5350e51d8147
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236434588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.1236434588
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.3607272515
Short name T680
Test name
Test status
Simulation time 6269868731 ps
CPU time 250.66 seconds
Started Apr 25 01:53:23 PM PDT 24
Finished Apr 25 01:57:34 PM PDT 24
Peak memory 247904 kb
Host smart-91937e1f-e51e-4078-98a8-42422ca6f45b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607272515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.3607272515
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.4128948712
Short name T395
Test name
Test status
Simulation time 303402549 ps
CPU time 18.22 seconds
Started Apr 25 01:53:33 PM PDT 24
Finished Apr 25 01:53:51 PM PDT 24
Peak memory 255880 kb
Host smart-b34536ce-68e6-41c7-995b-ef2bb13381df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41289
48712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.4128948712
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.2331337145
Short name T634
Test name
Test status
Simulation time 24949298 ps
CPU time 2.75 seconds
Started Apr 25 01:53:22 PM PDT 24
Finished Apr 25 01:53:25 PM PDT 24
Peak memory 240516 kb
Host smart-92210d81-0b32-489f-b361-15178d8c9302
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23313
37145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.2331337145
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.3586454327
Short name T92
Test name
Test status
Simulation time 1307175204 ps
CPU time 43.47 seconds
Started Apr 25 01:53:23 PM PDT 24
Finished Apr 25 01:54:07 PM PDT 24
Peak memory 255864 kb
Host smart-35c9d1c8-326b-497b-9c5e-6cc36308e3a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35864
54327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.3586454327
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.2401485072
Short name T329
Test name
Test status
Simulation time 167995240 ps
CPU time 13.02 seconds
Started Apr 25 01:53:24 PM PDT 24
Finished Apr 25 01:53:38 PM PDT 24
Peak memory 254460 kb
Host smart-8da0dab7-7518-468b-98f4-fb2a1aa358a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24014
85072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.2401485072
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.2199077176
Short name T234
Test name
Test status
Simulation time 404514010327 ps
CPU time 6814.74 seconds
Started Apr 25 01:53:31 PM PDT 24
Finished Apr 25 03:47:07 PM PDT 24
Peak memory 338328 kb
Host smart-0030a185-957c-4ffa-ba1a-6c8e9fcfe37a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199077176 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.2199077176
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.2563917731
Short name T687
Test name
Test status
Simulation time 96380488258 ps
CPU time 1517.81 seconds
Started Apr 25 01:53:41 PM PDT 24
Finished Apr 25 02:18:59 PM PDT 24
Peak memory 271300 kb
Host smart-0d828c9f-0395-41b8-a5e0-b0b05e5dad5b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563917731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.2563917731
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.2296481711
Short name T391
Test name
Test status
Simulation time 374774602 ps
CPU time 6.94 seconds
Started Apr 25 01:53:34 PM PDT 24
Finished Apr 25 01:53:41 PM PDT 24
Peak memory 248640 kb
Host smart-4076fc6d-175b-43f2-afc3-8791a12f4a4e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2296481711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.2296481711
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.1629878088
Short name T14
Test name
Test status
Simulation time 835144061 ps
CPU time 51.25 seconds
Started Apr 25 01:53:31 PM PDT 24
Finished Apr 25 01:54:23 PM PDT 24
Peak memory 248804 kb
Host smart-11159abc-738d-4bbc-8525-0d8419e9461f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16298
78088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.1629878088
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.4246614759
Short name T394
Test name
Test status
Simulation time 138526288 ps
CPU time 6.23 seconds
Started Apr 25 01:53:29 PM PDT 24
Finished Apr 25 01:53:36 PM PDT 24
Peak memory 250804 kb
Host smart-510646dd-cc22-47bc-b28c-e7f4fd2e443e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42466
14759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.4246614759
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.1600333174
Short name T312
Test name
Test status
Simulation time 10256067349 ps
CPU time 689.96 seconds
Started Apr 25 01:53:43 PM PDT 24
Finished Apr 25 02:05:14 PM PDT 24
Peak memory 272264 kb
Host smart-22e83670-02be-449e-b319-f61c054cca67
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600333174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.1600333174
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.952291006
Short name T536
Test name
Test status
Simulation time 187708720388 ps
CPU time 3053.79 seconds
Started Apr 25 01:53:36 PM PDT 24
Finished Apr 25 02:44:31 PM PDT 24
Peak memory 281532 kb
Host smart-329325a4-0791-4322-acf0-6c346d740d67
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952291006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.952291006
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.1465745836
Short name T661
Test name
Test status
Simulation time 18710544642 ps
CPU time 385.74 seconds
Started Apr 25 01:53:34 PM PDT 24
Finished Apr 25 02:00:01 PM PDT 24
Peak memory 247916 kb
Host smart-3124ce56-1a9b-4029-9a29-636edb4e3d91
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465745836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.1465745836
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.3169216572
Short name T649
Test name
Test status
Simulation time 166704311 ps
CPU time 12.35 seconds
Started Apr 25 01:53:30 PM PDT 24
Finished Apr 25 01:53:43 PM PDT 24
Peak memory 254808 kb
Host smart-c247a25c-6bf7-4ac1-b82f-e6c4956413a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31692
16572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.3169216572
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.4010053186
Short name T346
Test name
Test status
Simulation time 689958579 ps
CPU time 20.42 seconds
Started Apr 25 01:53:31 PM PDT 24
Finished Apr 25 01:53:52 PM PDT 24
Peak memory 248720 kb
Host smart-9be9f53f-e7ac-4b9d-90e9-1af5401e0aa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40100
53186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.4010053186
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.527393303
Short name T480
Test name
Test status
Simulation time 1106550200 ps
CPU time 32.96 seconds
Started Apr 25 01:53:28 PM PDT 24
Finished Apr 25 01:54:02 PM PDT 24
Peak memory 256840 kb
Host smart-0c31f00a-d007-4ba8-8a3d-83413286143a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52739
3303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.527393303
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.2214182079
Short name T509
Test name
Test status
Simulation time 65061035577 ps
CPU time 3200.05 seconds
Started Apr 25 01:53:34 PM PDT 24
Finished Apr 25 02:46:55 PM PDT 24
Peak memory 289416 kb
Host smart-7ec564b1-79db-4eec-a23f-0ca599253cfe
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214182079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.2214182079
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.3041286255
Short name T198
Test name
Test status
Simulation time 44999341 ps
CPU time 2.31 seconds
Started Apr 25 01:53:41 PM PDT 24
Finished Apr 25 01:53:44 PM PDT 24
Peak memory 248828 kb
Host smart-2596f25d-1030-40fe-9070-acd4903998b6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3041286255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.3041286255
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.2565945807
Short name T556
Test name
Test status
Simulation time 55600541837 ps
CPU time 1479.05 seconds
Started Apr 25 01:53:36 PM PDT 24
Finished Apr 25 02:18:16 PM PDT 24
Peak memory 289296 kb
Host smart-2459e93e-57c2-492b-ba13-0942734ac01f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565945807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.2565945807
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.2437375076
Short name T579
Test name
Test status
Simulation time 13081992696 ps
CPU time 177.43 seconds
Started Apr 25 01:53:35 PM PDT 24
Finished Apr 25 01:56:33 PM PDT 24
Peak memory 249880 kb
Host smart-f484e336-b71f-4ad9-a1b2-e5ad255235e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24373
75076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.2437375076
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.488727147
Short name T490
Test name
Test status
Simulation time 1781830540 ps
CPU time 51.75 seconds
Started Apr 25 01:53:35 PM PDT 24
Finished Apr 25 01:54:27 PM PDT 24
Peak memory 256144 kb
Host smart-5796672b-be8a-485b-bfa4-c17b59865340
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48872
7147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.488727147
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.609340549
Short name T303
Test name
Test status
Simulation time 88307746557 ps
CPU time 1733.2 seconds
Started Apr 25 01:53:42 PM PDT 24
Finished Apr 25 02:22:36 PM PDT 24
Peak memory 268204 kb
Host smart-c8d719ac-7350-4561-8194-61dab323136a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609340549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.609340549
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.3535257315
Short name T383
Test name
Test status
Simulation time 48419710163 ps
CPU time 1433.68 seconds
Started Apr 25 01:53:42 PM PDT 24
Finished Apr 25 02:17:36 PM PDT 24
Peak memory 273404 kb
Host smart-0c7234ce-1058-4ba6-8d69-0db89547406a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535257315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.3535257315
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.1617407579
Short name T282
Test name
Test status
Simulation time 23580534443 ps
CPU time 247.3 seconds
Started Apr 25 01:53:36 PM PDT 24
Finished Apr 25 01:57:44 PM PDT 24
Peak memory 255204 kb
Host smart-29992c83-7312-4b3c-98d5-a3713726aa2b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617407579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.1617407579
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.1474520510
Short name T469
Test name
Test status
Simulation time 2405181199 ps
CPU time 37.06 seconds
Started Apr 25 01:53:37 PM PDT 24
Finished Apr 25 01:54:15 PM PDT 24
Peak memory 255956 kb
Host smart-d8062d6c-5110-4b38-b7d2-aac80d3bd969
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14745
20510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.1474520510
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.1467963724
Short name T630
Test name
Test status
Simulation time 1405806632 ps
CPU time 8.83 seconds
Started Apr 25 01:53:43 PM PDT 24
Finished Apr 25 01:53:53 PM PDT 24
Peak memory 248892 kb
Host smart-4e7e54bb-1baa-4585-8f57-c9ebe4291800
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14679
63724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.1467963724
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.3860577429
Short name T253
Test name
Test status
Simulation time 314303179 ps
CPU time 18.26 seconds
Started Apr 25 01:53:40 PM PDT 24
Finished Apr 25 01:53:59 PM PDT 24
Peak memory 248708 kb
Host smart-cbc1d32c-0275-43d2-ac30-399eba136c7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38605
77429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.3860577429
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.3288150120
Short name T340
Test name
Test status
Simulation time 79994103 ps
CPU time 6.03 seconds
Started Apr 25 01:53:41 PM PDT 24
Finished Apr 25 01:53:48 PM PDT 24
Peak memory 248708 kb
Host smart-0581b3be-99c3-4b12-beed-14f42aa2e621
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32881
50120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.3288150120
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.2035316378
Short name T665
Test name
Test status
Simulation time 170242060470 ps
CPU time 2535.74 seconds
Started Apr 25 01:53:41 PM PDT 24
Finished Apr 25 02:35:58 PM PDT 24
Peak memory 289096 kb
Host smart-9349adb7-b7fe-44c3-afb7-e4e662144756
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035316378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.2035316378
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.1600535594
Short name T655
Test name
Test status
Simulation time 59230909708 ps
CPU time 1422.07 seconds
Started Apr 25 01:53:49 PM PDT 24
Finished Apr 25 02:17:32 PM PDT 24
Peak memory 289460 kb
Host smart-cc3b076c-4111-464a-a94c-4bec1e011b8c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600535594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.1600535594
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.145598357
Short name T35
Test name
Test status
Simulation time 786102853 ps
CPU time 15.91 seconds
Started Apr 25 01:53:45 PM PDT 24
Finished Apr 25 01:54:01 PM PDT 24
Peak memory 248680 kb
Host smart-70e8ffe0-24fa-4781-8544-2810a796253c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=145598357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.145598357
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.2366414109
Short name T612
Test name
Test status
Simulation time 417079519 ps
CPU time 16.88 seconds
Started Apr 25 01:53:46 PM PDT 24
Finished Apr 25 01:54:03 PM PDT 24
Peak memory 248892 kb
Host smart-660e22c6-6e17-4698-b5e4-0a4928f24fc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23664
14109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.2366414109
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.1005267253
Short name T379
Test name
Test status
Simulation time 75112378 ps
CPU time 8.02 seconds
Started Apr 25 01:53:46 PM PDT 24
Finished Apr 25 01:53:55 PM PDT 24
Peak memory 248724 kb
Host smart-6dcbd242-2084-46f7-bbdf-48733709cc3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10052
67253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.1005267253
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.226351415
Short name T467
Test name
Test status
Simulation time 31599365573 ps
CPU time 694.69 seconds
Started Apr 25 01:53:46 PM PDT 24
Finished Apr 25 02:05:21 PM PDT 24
Peak memory 265176 kb
Host smart-6a1530ed-91bd-4cd4-aeec-c484ca18b564
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226351415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.226351415
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.243732211
Short name T274
Test name
Test status
Simulation time 11642233727 ps
CPU time 398.89 seconds
Started Apr 25 01:53:47 PM PDT 24
Finished Apr 25 02:00:27 PM PDT 24
Peak memory 248096 kb
Host smart-0ebc7d20-67ef-4f55-83b4-6958b42902a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243732211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.243732211
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.2821986617
Short name T341
Test name
Test status
Simulation time 779906791 ps
CPU time 30.82 seconds
Started Apr 25 01:53:45 PM PDT 24
Finished Apr 25 01:54:17 PM PDT 24
Peak memory 248696 kb
Host smart-e6e787f8-23db-4f10-9ffc-af2d10b7ae5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28219
86617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.2821986617
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.3317612194
Short name T435
Test name
Test status
Simulation time 4808595377 ps
CPU time 52.96 seconds
Started Apr 25 01:53:46 PM PDT 24
Finished Apr 25 01:54:40 PM PDT 24
Peak memory 256076 kb
Host smart-1bf84d88-38ac-4da4-a408-95756540be4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33176
12194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.3317612194
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.4236180084
Short name T378
Test name
Test status
Simulation time 372418567 ps
CPU time 29.27 seconds
Started Apr 25 01:53:40 PM PDT 24
Finished Apr 25 01:54:10 PM PDT 24
Peak memory 255912 kb
Host smart-f67fe484-f628-45f6-a77e-e26a56777a9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42361
80084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.4236180084
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.1326508126
Short name T639
Test name
Test status
Simulation time 53702387927 ps
CPU time 1054.13 seconds
Started Apr 25 01:53:47 PM PDT 24
Finished Apr 25 02:11:21 PM PDT 24
Peak memory 283660 kb
Host smart-feca1649-af5b-4fd9-9be7-947ea9dc7a88
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326508126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.1326508126
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.234431544
Short name T226
Test name
Test status
Simulation time 45181322831 ps
CPU time 2500.48 seconds
Started Apr 25 01:53:52 PM PDT 24
Finished Apr 25 02:35:34 PM PDT 24
Peak memory 273512 kb
Host smart-b3d3aca7-71f5-4ea1-9b4b-dddb10afd4fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234431544 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.234431544
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.4133182722
Short name T54
Test name
Test status
Simulation time 168961384 ps
CPU time 3.23 seconds
Started Apr 25 01:53:51 PM PDT 24
Finished Apr 25 01:53:55 PM PDT 24
Peak memory 248864 kb
Host smart-3c603691-6854-4238-b5cf-4c06255213c1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4133182722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.4133182722
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.2852031144
Short name T66
Test name
Test status
Simulation time 444167301957 ps
CPU time 2694.7 seconds
Started Apr 25 01:54:01 PM PDT 24
Finished Apr 25 02:38:57 PM PDT 24
Peak memory 281488 kb
Host smart-7f67e42b-65af-4c13-b28e-3a89c524bc57
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852031144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.2852031144
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.3462425790
Short name T331
Test name
Test status
Simulation time 146125580 ps
CPU time 9.49 seconds
Started Apr 25 01:54:01 PM PDT 24
Finished Apr 25 01:54:12 PM PDT 24
Peak memory 248664 kb
Host smart-ad9ec8bc-1137-4d72-8c09-39733e9caeb1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3462425790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.3462425790
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.2568409943
Short name T359
Test name
Test status
Simulation time 15689753227 ps
CPU time 148.68 seconds
Started Apr 25 01:53:51 PM PDT 24
Finished Apr 25 01:56:21 PM PDT 24
Peak memory 256864 kb
Host smart-537d2163-aae7-41ed-a689-54a2437cb9ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25684
09943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.2568409943
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.2375953560
Short name T567
Test name
Test status
Simulation time 686445326 ps
CPU time 37.45 seconds
Started Apr 25 01:53:52 PM PDT 24
Finished Apr 25 01:54:30 PM PDT 24
Peak memory 248848 kb
Host smart-3a727751-953f-48ce-81b2-e15c06c4a40b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23759
53560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.2375953560
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.1686549214
Short name T416
Test name
Test status
Simulation time 46978017857 ps
CPU time 1238.66 seconds
Started Apr 25 01:53:53 PM PDT 24
Finished Apr 25 02:14:32 PM PDT 24
Peak memory 289556 kb
Host smart-ad4a1213-e870-42a0-a392-2c94adcca1aa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686549214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.1686549214
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.3739457783
Short name T290
Test name
Test status
Simulation time 38554438416 ps
CPU time 323.78 seconds
Started Apr 25 01:53:54 PM PDT 24
Finished Apr 25 01:59:18 PM PDT 24
Peak memory 254884 kb
Host smart-766b323e-9589-4cd7-a642-ce033bdcfafd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739457783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.3739457783
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.1113795261
Short name T420
Test name
Test status
Simulation time 3199480930 ps
CPU time 43.91 seconds
Started Apr 25 01:53:52 PM PDT 24
Finished Apr 25 01:54:36 PM PDT 24
Peak memory 248776 kb
Host smart-f86b8bae-9bb5-4ee7-87b2-c2e48b0e39de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11137
95261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.1113795261
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.4037131462
Short name T374
Test name
Test status
Simulation time 495460056 ps
CPU time 12 seconds
Started Apr 25 01:53:50 PM PDT 24
Finished Apr 25 01:54:03 PM PDT 24
Peak memory 247368 kb
Host smart-b1abdde4-8bf8-4a7a-a876-cd68fc2ec6f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40371
31462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.4037131462
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.2034062838
Short name T409
Test name
Test status
Simulation time 75252453 ps
CPU time 5.38 seconds
Started Apr 25 01:53:51 PM PDT 24
Finished Apr 25 01:53:57 PM PDT 24
Peak memory 240428 kb
Host smart-0a9f138e-7d78-4208-97e7-60c81be7e339
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20340
62838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.2034062838
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.3714232000
Short name T415
Test name
Test status
Simulation time 490650946 ps
CPU time 32.9 seconds
Started Apr 25 01:53:53 PM PDT 24
Finished Apr 25 01:54:26 PM PDT 24
Peak memory 248712 kb
Host smart-2ddf0420-13c1-4250-a535-d17f66c46ab6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37142
32000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.3714232000
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.411495557
Short name T564
Test name
Test status
Simulation time 87926918201 ps
CPU time 2892.27 seconds
Started Apr 25 01:53:54 PM PDT 24
Finished Apr 25 02:42:07 PM PDT 24
Peak memory 286536 kb
Host smart-ada61b66-8235-4eda-a7b5-585d4866fc11
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411495557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_han
dler_stress_all.411495557
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.2342691611
Short name T227
Test name
Test status
Simulation time 80911854645 ps
CPU time 845.92 seconds
Started Apr 25 01:53:52 PM PDT 24
Finished Apr 25 02:07:59 PM PDT 24
Peak memory 289776 kb
Host smart-387087bf-b955-499c-a7fd-8c2dec5b23b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342691611 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.2342691611
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.3776675374
Short name T194
Test name
Test status
Simulation time 111655695 ps
CPU time 3.35 seconds
Started Apr 25 01:54:01 PM PDT 24
Finished Apr 25 01:54:05 PM PDT 24
Peak memory 248876 kb
Host smart-6cd436b2-ab6b-44b4-9ee7-e11ffb82d32a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3776675374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.3776675374
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.59547039
Short name T107
Test name
Test status
Simulation time 41265810945 ps
CPU time 1128.05 seconds
Started Apr 25 01:53:58 PM PDT 24
Finished Apr 25 02:12:46 PM PDT 24
Peak memory 287788 kb
Host smart-81a55121-3105-446a-92c3-2d549d230172
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59547039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.59547039
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.2672851048
Short name T332
Test name
Test status
Simulation time 133505010 ps
CPU time 7.8 seconds
Started Apr 25 01:54:00 PM PDT 24
Finished Apr 25 01:54:08 PM PDT 24
Peak memory 240560 kb
Host smart-5fbe683d-5907-4730-819d-e17671188a5d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2672851048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.2672851048
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.1806911192
Short name T442
Test name
Test status
Simulation time 21696776640 ps
CPU time 310.6 seconds
Started Apr 25 01:54:02 PM PDT 24
Finished Apr 25 01:59:13 PM PDT 24
Peak memory 256852 kb
Host smart-d95ed7bc-ffdd-4058-8ead-8e24d85d121a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18069
11192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.1806911192
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.3084270956
Short name T625
Test name
Test status
Simulation time 50326922 ps
CPU time 2.66 seconds
Started Apr 25 01:53:58 PM PDT 24
Finished Apr 25 01:54:01 PM PDT 24
Peak memory 240472 kb
Host smart-ee514f14-ecf8-47c3-8da1-52fb52e25335
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30842
70956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.3084270956
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.1194234840
Short name T468
Test name
Test status
Simulation time 138206231836 ps
CPU time 1218.21 seconds
Started Apr 25 01:53:58 PM PDT 24
Finished Apr 25 02:14:16 PM PDT 24
Peak memory 267356 kb
Host smart-62d16b57-42b5-47df-a8d5-60e5f960fa40
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194234840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.1194234840
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.581901009
Short name T384
Test name
Test status
Simulation time 18681965548 ps
CPU time 1034.55 seconds
Started Apr 25 01:53:59 PM PDT 24
Finished Apr 25 02:11:14 PM PDT 24
Peak memory 272160 kb
Host smart-7ced243d-873d-45b3-bc96-bcfd6f9f6d71
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581901009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.581901009
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.946599896
Short name T283
Test name
Test status
Simulation time 39331616194 ps
CPU time 408.54 seconds
Started Apr 25 01:53:59 PM PDT 24
Finished Apr 25 02:00:48 PM PDT 24
Peak memory 254184 kb
Host smart-43cc6e4e-a36f-4b18-a8a6-c04a0c035d15
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946599896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.946599896
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.3630663814
Short name T650
Test name
Test status
Simulation time 98174235 ps
CPU time 7.84 seconds
Started Apr 25 01:54:01 PM PDT 24
Finished Apr 25 01:54:10 PM PDT 24
Peak memory 252024 kb
Host smart-d8ac3ccd-8024-4b14-a11f-08d044cecf9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36306
63814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.3630663814
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.2205369616
Short name T444
Test name
Test status
Simulation time 680755261 ps
CPU time 31.8 seconds
Started Apr 25 01:54:01 PM PDT 24
Finished Apr 25 01:54:34 PM PDT 24
Peak memory 255964 kb
Host smart-4f2e4946-3d7e-4eef-a804-85d509b5e9f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22053
69616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.2205369616
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.4074462686
Short name T414
Test name
Test status
Simulation time 1919281909 ps
CPU time 28.69 seconds
Started Apr 25 01:53:57 PM PDT 24
Finished Apr 25 01:54:27 PM PDT 24
Peak memory 254740 kb
Host smart-803d4d8f-985c-44c9-b498-bce582002ba8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40744
62686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.4074462686
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.2917998919
Short name T337
Test name
Test status
Simulation time 313871018 ps
CPU time 25.57 seconds
Started Apr 25 01:53:52 PM PDT 24
Finished Apr 25 01:54:18 PM PDT 24
Peak memory 256008 kb
Host smart-c0e08b82-2fce-48fc-895f-df11c5cdcfd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29179
98919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.2917998919
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.1912773742
Short name T523
Test name
Test status
Simulation time 17865610424 ps
CPU time 1502.23 seconds
Started Apr 25 01:54:00 PM PDT 24
Finished Apr 25 02:19:03 PM PDT 24
Peak memory 288720 kb
Host smart-76c9ef82-43af-4e65-bec0-837a2743794e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912773742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.1912773742
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.2280765160
Short name T206
Test name
Test status
Simulation time 14993237 ps
CPU time 2.34 seconds
Started Apr 25 01:54:03 PM PDT 24
Finished Apr 25 01:54:06 PM PDT 24
Peak memory 248876 kb
Host smart-beda4c8e-a54a-4837-884d-d1916988590e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2280765160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.2280765160
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.1462153113
Short name T407
Test name
Test status
Simulation time 68295852356 ps
CPU time 1651.28 seconds
Started Apr 25 01:54:04 PM PDT 24
Finished Apr 25 02:21:36 PM PDT 24
Peak memory 281536 kb
Host smart-cc57cc83-3bc8-4797-acf2-1ad57e7db4b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462153113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.1462153113
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.3475403612
Short name T592
Test name
Test status
Simulation time 460262710 ps
CPU time 20.18 seconds
Started Apr 25 01:54:05 PM PDT 24
Finished Apr 25 01:54:26 PM PDT 24
Peak memory 248704 kb
Host smart-d29934c7-036f-4c92-917b-ac27ba117a26
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3475403612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.3475403612
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.455898577
Short name T456
Test name
Test status
Simulation time 4573872628 ps
CPU time 68.7 seconds
Started Apr 25 01:54:07 PM PDT 24
Finished Apr 25 01:55:16 PM PDT 24
Peak memory 256116 kb
Host smart-e01fac52-c1ea-4cb2-be91-7638ce341fee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45589
8577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.455898577
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.2749378490
Short name T319
Test name
Test status
Simulation time 144055064638 ps
CPU time 1024.77 seconds
Started Apr 25 01:54:05 PM PDT 24
Finished Apr 25 02:11:11 PM PDT 24
Peak memory 272700 kb
Host smart-798b9558-d767-46dd-aa62-57e65d309c09
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749378490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.2749378490
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.4180198506
Short name T668
Test name
Test status
Simulation time 44813237443 ps
CPU time 2324 seconds
Started Apr 25 01:54:05 PM PDT 24
Finished Apr 25 02:32:50 PM PDT 24
Peak memory 286620 kb
Host smart-5e9dcbf6-e3fd-4029-aa77-f4773dcfbbe1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180198506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.4180198506
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.2062507477
Short name T675
Test name
Test status
Simulation time 13214196812 ps
CPU time 247.64 seconds
Started Apr 25 01:54:09 PM PDT 24
Finished Apr 25 01:58:17 PM PDT 24
Peak memory 248308 kb
Host smart-b6a38250-c689-442a-af32-5685b51bdc50
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062507477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.2062507477
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.2282751238
Short name T410
Test name
Test status
Simulation time 1688023164 ps
CPU time 57.12 seconds
Started Apr 25 01:54:00 PM PDT 24
Finished Apr 25 01:54:57 PM PDT 24
Peak memory 249044 kb
Host smart-d4ff387c-17ee-4e8b-8e90-1b881575582d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22827
51238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.2282751238
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.17259534
Short name T476
Test name
Test status
Simulation time 1624770878 ps
CPU time 17.92 seconds
Started Apr 25 01:54:03 PM PDT 24
Finished Apr 25 01:54:21 PM PDT 24
Peak memory 254828 kb
Host smart-f86fc604-5282-4162-91bd-35a52ffe9c1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17259
534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.17259534
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.2429308297
Short name T501
Test name
Test status
Simulation time 1525231027 ps
CPU time 30.64 seconds
Started Apr 25 01:54:04 PM PDT 24
Finished Apr 25 01:54:35 PM PDT 24
Peak memory 255920 kb
Host smart-3a57a76b-3828-4f11-b556-615f4ab25793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24293
08297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.2429308297
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.3077009303
Short name T557
Test name
Test status
Simulation time 278105729 ps
CPU time 3.47 seconds
Started Apr 25 01:53:58 PM PDT 24
Finished Apr 25 01:54:02 PM PDT 24
Peak memory 240388 kb
Host smart-a102b058-b2fc-4a89-87d3-46e551051809
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30770
09303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.3077009303
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.649873379
Short name T237
Test name
Test status
Simulation time 121433307174 ps
CPU time 3083.78 seconds
Started Apr 25 01:54:12 PM PDT 24
Finished Apr 25 02:45:37 PM PDT 24
Peak memory 322696 kb
Host smart-1f02f3ac-8c4e-4fa9-aab5-8cf3b384a62e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649873379 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.649873379
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.4046179493
Short name T208
Test name
Test status
Simulation time 86400216 ps
CPU time 3.64 seconds
Started Apr 25 01:54:12 PM PDT 24
Finished Apr 25 01:54:16 PM PDT 24
Peak memory 248864 kb
Host smart-68d43ecb-6520-4b1f-a235-21bda171f4be
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4046179493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.4046179493
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.3307039501
Short name T402
Test name
Test status
Simulation time 146341271952 ps
CPU time 2118.55 seconds
Started Apr 25 01:54:13 PM PDT 24
Finished Apr 25 02:29:33 PM PDT 24
Peak memory 270596 kb
Host smart-5a829990-151f-499a-b66c-48cbcdd6394d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307039501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.3307039501
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.527498948
Short name T586
Test name
Test status
Simulation time 407250797 ps
CPU time 11.82 seconds
Started Apr 25 01:54:14 PM PDT 24
Finished Apr 25 01:54:26 PM PDT 24
Peak memory 248628 kb
Host smart-24704c47-b624-4be4-b6ac-c2ce824e5bb2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=527498948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.527498948
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.572888042
Short name T600
Test name
Test status
Simulation time 1592949972 ps
CPU time 65.29 seconds
Started Apr 25 01:54:10 PM PDT 24
Finished Apr 25 01:55:16 PM PDT 24
Peak memory 248716 kb
Host smart-06c6b260-7a43-44e4-b0e2-b4eba585c446
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57288
8042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.572888042
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.1233805905
Short name T280
Test name
Test status
Simulation time 48035927297 ps
CPU time 2705.3 seconds
Started Apr 25 01:54:12 PM PDT 24
Finished Apr 25 02:39:19 PM PDT 24
Peak memory 281532 kb
Host smart-9f5cc0c2-656c-492b-8afd-6a114c16defc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233805905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.1233805905
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.2555027362
Short name T515
Test name
Test status
Simulation time 38712497977 ps
CPU time 783.42 seconds
Started Apr 25 01:54:17 PM PDT 24
Finished Apr 25 02:07:21 PM PDT 24
Peak memory 272356 kb
Host smart-9feb033b-f71a-4bf4-9cb2-9d2aaf429f81
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555027362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.2555027362
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.2537087645
Short name T651
Test name
Test status
Simulation time 200447545 ps
CPU time 18.5 seconds
Started Apr 25 01:54:11 PM PDT 24
Finished Apr 25 01:54:30 PM PDT 24
Peak memory 248796 kb
Host smart-16e6bf09-c33a-41b4-b728-6c716df08b8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25370
87645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.2537087645
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.1719431701
Short name T537
Test name
Test status
Simulation time 2899105923 ps
CPU time 71.21 seconds
Started Apr 25 01:54:10 PM PDT 24
Finished Apr 25 01:55:22 PM PDT 24
Peak memory 256920 kb
Host smart-48d5ed2c-419e-4ff2-bdf7-e3f0d154110d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17194
31701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.1719431701
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.2569699777
Short name T18
Test name
Test status
Simulation time 977371512 ps
CPU time 31.13 seconds
Started Apr 25 01:54:10 PM PDT 24
Finished Apr 25 01:54:42 PM PDT 24
Peak memory 255840 kb
Host smart-e2548655-39e4-48e3-8b3d-70e893569136
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25696
99777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.2569699777
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.3638541264
Short name T670
Test name
Test status
Simulation time 170648017 ps
CPU time 15.46 seconds
Started Apr 25 01:54:09 PM PDT 24
Finished Apr 25 01:54:25 PM PDT 24
Peak memory 255892 kb
Host smart-fd58b0d8-74a9-4eaa-818d-71737e609147
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36385
41264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.3638541264
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.79910827
Short name T24
Test name
Test status
Simulation time 250965445912 ps
CPU time 7185.3 seconds
Started Apr 25 01:54:12 PM PDT 24
Finished Apr 25 03:53:58 PM PDT 24
Peak memory 364672 kb
Host smart-0eb5464a-1dd6-4809-90b2-127624792a73
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79910827 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.79910827
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.308217387
Short name T196
Test name
Test status
Simulation time 50011489 ps
CPU time 3.58 seconds
Started Apr 25 01:52:42 PM PDT 24
Finished Apr 25 01:52:46 PM PDT 24
Peak memory 248904 kb
Host smart-a0e50b86-3d69-49c6-81e5-d94cc3bb8e52
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=308217387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.308217387
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.3342705044
Short name T267
Test name
Test status
Simulation time 17475826890 ps
CPU time 1217.13 seconds
Started Apr 25 01:52:30 PM PDT 24
Finished Apr 25 02:12:48 PM PDT 24
Peak memory 281516 kb
Host smart-357578c1-7806-499c-aa77-edae86da67a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342705044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.3342705044
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.1076780532
Short name T36
Test name
Test status
Simulation time 1881626224 ps
CPU time 16.36 seconds
Started Apr 25 01:52:40 PM PDT 24
Finished Apr 25 01:52:57 PM PDT 24
Peak memory 248676 kb
Host smart-6ee1eebc-8e2b-44e4-91db-cc57a9418df7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1076780532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.1076780532
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.277859074
Short name T663
Test name
Test status
Simulation time 1326952963 ps
CPU time 49.81 seconds
Started Apr 25 01:52:31 PM PDT 24
Finished Apr 25 01:53:21 PM PDT 24
Peak memory 248768 kb
Host smart-c235f295-35d8-4334-9c69-f7436b62036d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27785
9074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.277859074
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.643819321
Short name T86
Test name
Test status
Simulation time 1047116438 ps
CPU time 17.27 seconds
Started Apr 25 01:52:29 PM PDT 24
Finished Apr 25 01:52:47 PM PDT 24
Peak memory 254856 kb
Host smart-e2b3df0e-ac9d-4d41-bcf7-4b3eba35531b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64381
9321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.643819321
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.2715326282
Short name T257
Test name
Test status
Simulation time 143512753384 ps
CPU time 1255.28 seconds
Started Apr 25 01:52:35 PM PDT 24
Finished Apr 25 02:13:31 PM PDT 24
Peak memory 273336 kb
Host smart-2b13c8f9-dfb0-494d-b16a-25299133b9f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715326282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.2715326282
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.2148846757
Short name T690
Test name
Test status
Simulation time 10658806866 ps
CPU time 408.25 seconds
Started Apr 25 01:52:35 PM PDT 24
Finished Apr 25 01:59:24 PM PDT 24
Peak memory 247876 kb
Host smart-61fdf995-472e-4002-8252-00e8349a3de1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148846757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.2148846757
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.1374120277
Short name T343
Test name
Test status
Simulation time 909732079 ps
CPU time 24.77 seconds
Started Apr 25 01:52:30 PM PDT 24
Finished Apr 25 01:52:56 PM PDT 24
Peak memory 248716 kb
Host smart-f19c9780-14e1-437a-a713-c6faa450948e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13741
20277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.1374120277
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.2506897745
Short name T585
Test name
Test status
Simulation time 1722263755 ps
CPU time 26.97 seconds
Started Apr 25 01:52:31 PM PDT 24
Finished Apr 25 01:52:58 PM PDT 24
Peak memory 255448 kb
Host smart-4bcafc22-bcaf-4deb-bd56-a2b2ccea8403
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25068
97745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.2506897745
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.947260974
Short name T583
Test name
Test status
Simulation time 136733847 ps
CPU time 9.52 seconds
Started Apr 25 01:52:28 PM PDT 24
Finished Apr 25 01:52:38 PM PDT 24
Peak memory 248736 kb
Host smart-5c3cd449-01e9-4ed8-8723-648d7735e9db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94726
0974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.947260974
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.2843103824
Short name T677
Test name
Test status
Simulation time 142498520 ps
CPU time 5.45 seconds
Started Apr 25 01:52:34 PM PDT 24
Finished Apr 25 01:52:40 PM PDT 24
Peak memory 248708 kb
Host smart-b6e3ce26-0609-4440-86dd-7d30c9d3e179
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28431
03824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.2843103824
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.785891106
Short name T674
Test name
Test status
Simulation time 9336116406 ps
CPU time 776.58 seconds
Started Apr 25 01:52:34 PM PDT 24
Finished Apr 25 02:05:32 PM PDT 24
Peak memory 272720 kb
Host smart-809ae577-5114-436d-af1c-79fe1b90e49d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785891106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_hand
ler_stress_all.785891106
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.528905028
Short name T541
Test name
Test status
Simulation time 62821429066 ps
CPU time 5627.13 seconds
Started Apr 25 01:52:41 PM PDT 24
Finished Apr 25 03:26:29 PM PDT 24
Peak memory 337508 kb
Host smart-1f264d96-4a22-47c0-9604-e43d7d425269
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528905028 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.528905028
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.3111436517
Short name T411
Test name
Test status
Simulation time 51632103119 ps
CPU time 2631.41 seconds
Started Apr 25 01:54:17 PM PDT 24
Finished Apr 25 02:38:09 PM PDT 24
Peak memory 281452 kb
Host smart-55b92f46-91de-4044-95c0-3a1af9ec11aa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111436517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.3111436517
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.2001795675
Short name T335
Test name
Test status
Simulation time 1979040315 ps
CPU time 145.67 seconds
Started Apr 25 01:54:17 PM PDT 24
Finished Apr 25 01:56:43 PM PDT 24
Peak memory 256820 kb
Host smart-8f82d157-978c-4786-b14c-c69fd398e42e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20017
95675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.2001795675
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.3987289094
Short name T499
Test name
Test status
Simulation time 9410719812 ps
CPU time 50.26 seconds
Started Apr 25 01:54:23 PM PDT 24
Finished Apr 25 01:55:14 PM PDT 24
Peak memory 248756 kb
Host smart-3f5925ac-96fb-42bf-b6a0-cddd8adb6e6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39872
89094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.3987289094
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.2177415360
Short name T694
Test name
Test status
Simulation time 30512236074 ps
CPU time 772.14 seconds
Started Apr 25 01:54:15 PM PDT 24
Finished Apr 25 02:07:08 PM PDT 24
Peak memory 268376 kb
Host smart-65ca27d8-b80a-4615-8203-6cd9894de7d8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177415360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.2177415360
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.2945808373
Short name T360
Test name
Test status
Simulation time 53551171730 ps
CPU time 2173.47 seconds
Started Apr 25 01:54:17 PM PDT 24
Finished Apr 25 02:30:32 PM PDT 24
Peak memory 287736 kb
Host smart-c933580b-46a4-47a4-93f1-5b33f9aa42e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945808373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.2945808373
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.475945087
Short name T635
Test name
Test status
Simulation time 22026871590 ps
CPU time 230.14 seconds
Started Apr 25 01:54:17 PM PDT 24
Finished Apr 25 01:58:08 PM PDT 24
Peak memory 248136 kb
Host smart-0694a377-44b0-4499-b1ac-51aa72b5003e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475945087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.475945087
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.1592257959
Short name T466
Test name
Test status
Simulation time 1270994048 ps
CPU time 6.54 seconds
Started Apr 25 01:54:10 PM PDT 24
Finished Apr 25 01:54:17 PM PDT 24
Peak memory 248668 kb
Host smart-b20ab2cd-1ff0-468b-8d02-d0e0c6b54302
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15922
57959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.1592257959
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.152926916
Short name T673
Test name
Test status
Simulation time 592343169 ps
CPU time 23.02 seconds
Started Apr 25 01:54:12 PM PDT 24
Finished Apr 25 01:54:36 PM PDT 24
Peak memory 248720 kb
Host smart-74f9f7ed-dcbc-4e82-b1a1-e83effa264f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15292
6916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.152926916
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.3734885588
Short name T563
Test name
Test status
Simulation time 2970057938 ps
CPU time 58.68 seconds
Started Apr 25 01:54:17 PM PDT 24
Finished Apr 25 01:55:16 PM PDT 24
Peak memory 248468 kb
Host smart-6f4107cb-f544-4d00-8797-d9a3e0d618e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37348
85588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.3734885588
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.2765834460
Short name T460
Test name
Test status
Simulation time 101015574 ps
CPU time 6.56 seconds
Started Apr 25 01:54:12 PM PDT 24
Finished Apr 25 01:54:20 PM PDT 24
Peak memory 248688 kb
Host smart-096ccc67-7bee-4731-a300-74fc97397bea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27658
34460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.2765834460
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.1021015144
Short name T678
Test name
Test status
Simulation time 241498013914 ps
CPU time 2380.17 seconds
Started Apr 25 01:54:16 PM PDT 24
Finished Apr 25 02:33:57 PM PDT 24
Peak memory 281524 kb
Host smart-99906332-ac9a-41cd-a10d-2e06f89d0066
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021015144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.1021015144
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.3715212317
Short name T187
Test name
Test status
Simulation time 317219422452 ps
CPU time 5315.01 seconds
Started Apr 25 01:54:17 PM PDT 24
Finished Apr 25 03:22:54 PM PDT 24
Peak memory 365700 kb
Host smart-2295064f-4954-4758-a95f-419493b4c37f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715212317 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.3715212317
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.1877346503
Short name T624
Test name
Test status
Simulation time 286162857542 ps
CPU time 1060.97 seconds
Started Apr 25 01:54:24 PM PDT 24
Finished Apr 25 02:12:05 PM PDT 24
Peak memory 272008 kb
Host smart-9e0f42d2-1fd1-46f2-8784-d2ab0c1e74e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877346503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.1877346503
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.3877071848
Short name T390
Test name
Test status
Simulation time 2169577911 ps
CPU time 80.82 seconds
Started Apr 25 01:54:16 PM PDT 24
Finished Apr 25 01:55:37 PM PDT 24
Peak memory 249732 kb
Host smart-099b9688-801f-4585-b69c-8afa4a901eb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38770
71848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.3877071848
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.3830486274
Short name T478
Test name
Test status
Simulation time 675342806 ps
CPU time 39.2 seconds
Started Apr 25 01:54:16 PM PDT 24
Finished Apr 25 01:54:56 PM PDT 24
Peak memory 255868 kb
Host smart-c2e8c53d-50c6-406c-b2d5-8f5f1d5a9985
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38304
86274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.3830486274
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.742241441
Short name T669
Test name
Test status
Simulation time 103349100646 ps
CPU time 3074.32 seconds
Started Apr 25 01:54:21 PM PDT 24
Finished Apr 25 02:45:36 PM PDT 24
Peak memory 289384 kb
Host smart-45ffba48-e340-4c0d-a5f0-be807ce95b0c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742241441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.742241441
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.1176259009
Short name T288
Test name
Test status
Simulation time 13453037972 ps
CPU time 520.57 seconds
Started Apr 25 01:54:22 PM PDT 24
Finished Apr 25 02:03:03 PM PDT 24
Peak memory 247120 kb
Host smart-6b71abc6-4c5f-47cd-aee7-5deae3ab1257
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176259009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.1176259009
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.2422180358
Short name T540
Test name
Test status
Simulation time 1934943873 ps
CPU time 21.87 seconds
Started Apr 25 01:54:17 PM PDT 24
Finished Apr 25 01:54:39 PM PDT 24
Peak memory 248748 kb
Host smart-d3eef7c8-d69b-4642-9fcb-d21c0bace64e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24221
80358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.2422180358
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.1395343632
Short name T81
Test name
Test status
Simulation time 665297605 ps
CPU time 36.51 seconds
Started Apr 25 01:54:15 PM PDT 24
Finished Apr 25 01:54:52 PM PDT 24
Peak memory 255372 kb
Host smart-aa8d7e4e-09aa-4955-86c4-66870ec2a07a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13953
43632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.1395343632
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.853193125
Short name T50
Test name
Test status
Simulation time 112533954 ps
CPU time 11.64 seconds
Started Apr 25 01:54:20 PM PDT 24
Finished Apr 25 01:54:32 PM PDT 24
Peak memory 255524 kb
Host smart-ed1f0b97-021b-491f-af76-5b93c9899ffe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85319
3125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.853193125
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.3414460127
Short name T463
Test name
Test status
Simulation time 134811841 ps
CPU time 5.22 seconds
Started Apr 25 01:54:17 PM PDT 24
Finished Apr 25 01:54:23 PM PDT 24
Peak memory 250796 kb
Host smart-885e1f98-c55b-4b2c-a75c-f6f4a5884c13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34144
60127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.3414460127
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.658279027
Short name T667
Test name
Test status
Simulation time 99409399726 ps
CPU time 1243.51 seconds
Started Apr 25 01:54:22 PM PDT 24
Finished Apr 25 02:15:07 PM PDT 24
Peak memory 289572 kb
Host smart-e157b227-50ae-498a-834f-b8c218b4916e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658279027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_han
dler_stress_all.658279027
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.670351800
Short name T32
Test name
Test status
Simulation time 117057655057 ps
CPU time 9775.26 seconds
Started Apr 25 01:54:23 PM PDT 24
Finished Apr 25 04:37:20 PM PDT 24
Peak memory 363620 kb
Host smart-e7ead6b2-3739-4019-bc76-86e00b6e9115
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670351800 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.670351800
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.1030904646
Short name T429
Test name
Test status
Simulation time 33621969398 ps
CPU time 1951.14 seconds
Started Apr 25 01:54:23 PM PDT 24
Finished Apr 25 02:26:55 PM PDT 24
Peak memory 286084 kb
Host smart-0ba2a958-52b1-4d1d-a5af-75d984560862
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030904646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.1030904646
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.800901327
Short name T388
Test name
Test status
Simulation time 4842119147 ps
CPU time 250.11 seconds
Started Apr 25 01:54:24 PM PDT 24
Finished Apr 25 01:58:35 PM PDT 24
Peak memory 251152 kb
Host smart-67f19e1c-a210-4151-a218-1031eb5f6b08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80090
1327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.800901327
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.2699714609
Short name T658
Test name
Test status
Simulation time 1081357750 ps
CPU time 35.76 seconds
Started Apr 25 01:54:23 PM PDT 24
Finished Apr 25 01:54:59 PM PDT 24
Peak memory 255736 kb
Host smart-18652363-af79-4b5d-b39c-00c20733e6fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26997
14609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.2699714609
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.2707676820
Short name T548
Test name
Test status
Simulation time 49340311166 ps
CPU time 1592.62 seconds
Started Apr 25 01:54:26 PM PDT 24
Finished Apr 25 02:20:59 PM PDT 24
Peak memory 273340 kb
Host smart-9c2de1aa-2416-4242-b230-23f145d8ccc8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707676820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.2707676820
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.2645136662
Short name T5
Test name
Test status
Simulation time 26732779394 ps
CPU time 259.88 seconds
Started Apr 25 01:54:22 PM PDT 24
Finished Apr 25 01:58:42 PM PDT 24
Peak memory 248024 kb
Host smart-7935fc9b-6fa4-4de0-81d8-abc1b99ded78
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645136662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.2645136662
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.767489821
Short name T12
Test name
Test status
Simulation time 3192267525 ps
CPU time 46.07 seconds
Started Apr 25 01:54:21 PM PDT 24
Finished Apr 25 01:55:08 PM PDT 24
Peak memory 248768 kb
Host smart-ae9b9179-e07c-401b-9239-ea19ec3d8b72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76748
9821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.767489821
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.3204741343
Short name T111
Test name
Test status
Simulation time 1852632594 ps
CPU time 26.71 seconds
Started Apr 25 01:54:20 PM PDT 24
Finished Apr 25 01:54:47 PM PDT 24
Peak memory 248664 kb
Host smart-910077eb-df16-4209-a9fb-948b1c36055f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32047
41343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.3204741343
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.369503888
Short name T358
Test name
Test status
Simulation time 559552935 ps
CPU time 9.09 seconds
Started Apr 25 01:54:22 PM PDT 24
Finished Apr 25 01:54:32 PM PDT 24
Peak memory 248704 kb
Host smart-0ef68758-98b3-4e20-8635-a83cf51f96ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36950
3888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.369503888
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.1982697710
Short name T70
Test name
Test status
Simulation time 110219179 ps
CPU time 7.32 seconds
Started Apr 25 01:54:23 PM PDT 24
Finished Apr 25 01:54:31 PM PDT 24
Peak memory 248804 kb
Host smart-94cd87ce-c157-4ff4-86e8-99a56186b1b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19826
97710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.1982697710
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.2621112689
Short name T578
Test name
Test status
Simulation time 2740942988 ps
CPU time 231.97 seconds
Started Apr 25 01:54:27 PM PDT 24
Finished Apr 25 01:58:20 PM PDT 24
Peak memory 256928 kb
Host smart-93e5fc71-217a-45fe-ac8c-3f208338e780
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621112689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.2621112689
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.3559409678
Short name T98
Test name
Test status
Simulation time 262759847882 ps
CPU time 4389.39 seconds
Started Apr 25 01:54:26 PM PDT 24
Finished Apr 25 03:07:37 PM PDT 24
Peak memory 315228 kb
Host smart-9e02fd2d-0241-4f37-ad7f-d3f8597b1d5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559409678 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.3559409678
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.400278980
Short name T422
Test name
Test status
Simulation time 175239615927 ps
CPU time 2700.68 seconds
Started Apr 25 01:54:27 PM PDT 24
Finished Apr 25 02:39:29 PM PDT 24
Peak memory 289176 kb
Host smart-474b8e6d-f124-4002-b10e-a70c0b1ea3f4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400278980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.400278980
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.3760560428
Short name T507
Test name
Test status
Simulation time 775187864 ps
CPU time 23.27 seconds
Started Apr 25 01:54:38 PM PDT 24
Finished Apr 25 01:55:02 PM PDT 24
Peak memory 256272 kb
Host smart-d480c8f1-e603-4dc1-9ef6-fb59e2e9f3be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37605
60428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.3760560428
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.2479995974
Short name T368
Test name
Test status
Simulation time 425509834 ps
CPU time 15.38 seconds
Started Apr 25 01:54:28 PM PDT 24
Finished Apr 25 01:54:44 PM PDT 24
Peak memory 255888 kb
Host smart-3d784c6a-cf0a-48be-9df4-4a7133911afc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24799
95974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.2479995974
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.384209332
Short name T222
Test name
Test status
Simulation time 9054422829 ps
CPU time 876.81 seconds
Started Apr 25 01:54:33 PM PDT 24
Finished Apr 25 02:09:10 PM PDT 24
Peak memory 281920 kb
Host smart-2cd41d9c-d8f3-4508-a6dd-4d6e2cf27338
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384209332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.384209332
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.3284920450
Short name T477
Test name
Test status
Simulation time 10619626421 ps
CPU time 423.93 seconds
Started Apr 25 01:54:26 PM PDT 24
Finished Apr 25 02:01:31 PM PDT 24
Peak memory 256304 kb
Host smart-44cf55bd-8672-47ce-820e-77f9ba1e9818
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284920450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.3284920450
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.993138207
Short name T352
Test name
Test status
Simulation time 667833415 ps
CPU time 46.06 seconds
Started Apr 25 01:54:26 PM PDT 24
Finished Apr 25 01:55:13 PM PDT 24
Peak memory 248668 kb
Host smart-587a2709-2015-443b-9057-197e7d19e7ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99313
8207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.993138207
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.574771615
Short name T51
Test name
Test status
Simulation time 1056538943 ps
CPU time 48.58 seconds
Started Apr 25 01:54:26 PM PDT 24
Finished Apr 25 01:55:16 PM PDT 24
Peak memory 248716 kb
Host smart-a8dedda3-4a80-4a46-8166-94f1df6f7330
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57477
1615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.574771615
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.1453175300
Short name T19
Test name
Test status
Simulation time 733286590 ps
CPU time 35.51 seconds
Started Apr 25 01:54:26 PM PDT 24
Finished Apr 25 01:55:03 PM PDT 24
Peak memory 255912 kb
Host smart-0a454e61-7985-4042-b8ec-8aaf60c2822d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14531
75300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.1453175300
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.1615665255
Short name T219
Test name
Test status
Simulation time 1232499874 ps
CPU time 14.8 seconds
Started Apr 25 01:54:26 PM PDT 24
Finished Apr 25 01:54:41 PM PDT 24
Peak memory 255876 kb
Host smart-2e6507fe-db66-4c93-9164-a84fab89f165
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16156
65255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.1615665255
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.649197071
Short name T571
Test name
Test status
Simulation time 20926673738 ps
CPU time 1059.16 seconds
Started Apr 25 01:54:33 PM PDT 24
Finished Apr 25 02:12:13 PM PDT 24
Peak memory 284904 kb
Host smart-040059bd-6906-4585-86eb-93aff020a515
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649197071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_han
dler_stress_all.649197071
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.1001696756
Short name T652
Test name
Test status
Simulation time 37099723594 ps
CPU time 785.85 seconds
Started Apr 25 01:54:40 PM PDT 24
Finished Apr 25 02:07:46 PM PDT 24
Peak memory 282120 kb
Host smart-6f062e3e-026d-4ad8-9153-2ab4b217ce1d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001696756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.1001696756
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.2128976567
Short name T449
Test name
Test status
Simulation time 14295605104 ps
CPU time 99.33 seconds
Started Apr 25 01:54:32 PM PDT 24
Finished Apr 25 01:56:12 PM PDT 24
Peak memory 249008 kb
Host smart-576401b9-b0e5-46e4-94cf-1b393081d946
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21289
76567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.2128976567
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.1104251513
Short name T432
Test name
Test status
Simulation time 277961329 ps
CPU time 24.63 seconds
Started Apr 25 01:54:33 PM PDT 24
Finished Apr 25 01:54:58 PM PDT 24
Peak memory 255968 kb
Host smart-2010d851-4500-4259-a50a-7df30ae1a284
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11042
51513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.1104251513
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.1809613919
Short name T301
Test name
Test status
Simulation time 119843800216 ps
CPU time 1643.13 seconds
Started Apr 25 01:54:44 PM PDT 24
Finished Apr 25 02:22:08 PM PDT 24
Peak memory 265264 kb
Host smart-b9ffb0c6-9720-495e-af34-563756da36ca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809613919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.1809613919
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.143699858
Short name T605
Test name
Test status
Simulation time 7300525068 ps
CPU time 212.61 seconds
Started Apr 25 01:54:40 PM PDT 24
Finished Apr 25 01:58:13 PM PDT 24
Peak memory 248120 kb
Host smart-1b4e7afa-f3c0-49e2-87ee-6f27893635d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143699858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.143699858
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.1536656606
Short name T621
Test name
Test status
Simulation time 211416850 ps
CPU time 18.9 seconds
Started Apr 25 01:54:33 PM PDT 24
Finished Apr 25 01:54:52 PM PDT 24
Peak memory 256088 kb
Host smart-2e37664d-0115-46b0-8f86-5ec1ce39bf8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15366
56606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.1536656606
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.1316012849
Short name T392
Test name
Test status
Simulation time 803861356 ps
CPU time 41.68 seconds
Started Apr 25 01:54:33 PM PDT 24
Finished Apr 25 01:55:16 PM PDT 24
Peak memory 248716 kb
Host smart-fc396609-3252-40d7-bc89-87c4c0e1c52a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13160
12849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.1316012849
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.3234353425
Short name T448
Test name
Test status
Simulation time 516317657 ps
CPU time 15.82 seconds
Started Apr 25 01:54:32 PM PDT 24
Finished Apr 25 01:54:48 PM PDT 24
Peak memory 247344 kb
Host smart-5b23ae98-2aff-4d28-b797-0d8fb3e430e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32343
53425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.3234353425
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.413772824
Short name T640
Test name
Test status
Simulation time 48864195 ps
CPU time 2.67 seconds
Started Apr 25 01:54:31 PM PDT 24
Finished Apr 25 01:54:34 PM PDT 24
Peak memory 240520 kb
Host smart-556b756d-7378-4483-811f-f7401f6e7c20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41377
2824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.413772824
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.2479052062
Short name T638
Test name
Test status
Simulation time 141937038 ps
CPU time 14.5 seconds
Started Apr 25 01:54:39 PM PDT 24
Finished Apr 25 01:54:54 PM PDT 24
Peak memory 248696 kb
Host smart-f4d52834-4f82-44e2-ad83-9416193a7a59
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479052062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.2479052062
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.1541639137
Short name T123
Test name
Test status
Simulation time 44274260361 ps
CPU time 2854.78 seconds
Started Apr 25 01:54:40 PM PDT 24
Finished Apr 25 02:42:16 PM PDT 24
Peak memory 288476 kb
Host smart-85cf6fc8-768f-485e-9e62-8fe6567a98d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541639137 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.1541639137
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.2156515182
Short name T354
Test name
Test status
Simulation time 1915558187 ps
CPU time 78.02 seconds
Started Apr 25 01:54:39 PM PDT 24
Finished Apr 25 01:55:58 PM PDT 24
Peak memory 249980 kb
Host smart-cc347eef-618e-4206-8489-fd7ab2650dac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21565
15182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.2156515182
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.4185058361
Short name T552
Test name
Test status
Simulation time 420539979 ps
CPU time 10.39 seconds
Started Apr 25 01:54:44 PM PDT 24
Finished Apr 25 01:54:55 PM PDT 24
Peak memory 253832 kb
Host smart-458c59fb-6771-4a16-a2e4-d0f0dfbd73ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41850
58361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.4185058361
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.1458986128
Short name T279
Test name
Test status
Simulation time 100139319159 ps
CPU time 2981.78 seconds
Started Apr 25 01:54:39 PM PDT 24
Finished Apr 25 02:44:21 PM PDT 24
Peak memory 288744 kb
Host smart-bf35a88d-7ce8-4ba4-8c1f-9fef3cd33b77
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458986128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.1458986128
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.1373688321
Short name T500
Test name
Test status
Simulation time 151147550771 ps
CPU time 3033.04 seconds
Started Apr 25 01:54:38 PM PDT 24
Finished Apr 25 02:45:12 PM PDT 24
Peak memory 289136 kb
Host smart-16ab4574-e05e-4701-aaba-52be4c2243fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373688321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.1373688321
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.1845793730
Short name T291
Test name
Test status
Simulation time 9965535338 ps
CPU time 179.72 seconds
Started Apr 25 01:54:40 PM PDT 24
Finished Apr 25 01:57:40 PM PDT 24
Peak memory 247816 kb
Host smart-5f59fe6b-d509-4975-8324-bc4c52fdf638
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845793730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.1845793730
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.1255755862
Short name T484
Test name
Test status
Simulation time 534016567 ps
CPU time 35.42 seconds
Started Apr 25 01:54:37 PM PDT 24
Finished Apr 25 01:55:13 PM PDT 24
Peak memory 255956 kb
Host smart-6326bbe5-9884-418c-ac8c-e7744a9b1dc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12557
55862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.1255755862
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.2528889805
Short name T260
Test name
Test status
Simulation time 3869785040 ps
CPU time 47.73 seconds
Started Apr 25 01:54:39 PM PDT 24
Finished Apr 25 01:55:27 PM PDT 24
Peak memory 255524 kb
Host smart-e358d9e0-4794-4456-8636-cdf3367df7fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25288
89805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.2528889805
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.3206446461
Short name T1
Test name
Test status
Simulation time 2993472894 ps
CPU time 34.67 seconds
Started Apr 25 01:54:39 PM PDT 24
Finished Apr 25 01:55:14 PM PDT 24
Peak memory 248896 kb
Host smart-8800b40d-4445-4677-bceb-14c6c46b3db6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32064
46461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.3206446461
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.1545896209
Short name T364
Test name
Test status
Simulation time 32665278050 ps
CPU time 2337.23 seconds
Started Apr 25 01:54:41 PM PDT 24
Finished Apr 25 02:33:39 PM PDT 24
Peak memory 288780 kb
Host smart-03048a54-7566-4a88-91c2-158f15235444
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545896209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.1545896209
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.1249584582
Short name T664
Test name
Test status
Simulation time 224612724620 ps
CPU time 3124.76 seconds
Started Apr 25 01:54:46 PM PDT 24
Finished Apr 25 02:46:52 PM PDT 24
Peak memory 289308 kb
Host smart-e9b5f765-8d68-4264-a6a0-a523dee8e8d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249584582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.1249584582
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.1853707902
Short name T510
Test name
Test status
Simulation time 775909085 ps
CPU time 69.41 seconds
Started Apr 25 01:54:50 PM PDT 24
Finished Apr 25 01:56:00 PM PDT 24
Peak memory 256604 kb
Host smart-04ed701b-0e51-4085-812b-49bdede353ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18537
07902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.1853707902
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.86987477
Short name T85
Test name
Test status
Simulation time 1616897876 ps
CPU time 40.91 seconds
Started Apr 25 01:54:52 PM PDT 24
Finished Apr 25 01:55:34 PM PDT 24
Peak memory 255920 kb
Host smart-b9e885f2-8906-4192-8553-3443fd7650cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86987
477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.86987477
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.781737180
Short name T17
Test name
Test status
Simulation time 96367733316 ps
CPU time 1061.27 seconds
Started Apr 25 01:54:51 PM PDT 24
Finished Apr 25 02:12:33 PM PDT 24
Peak memory 272552 kb
Host smart-b6095950-a193-4621-b23d-8e517ff171fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781737180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.781737180
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.221916231
Short name T362
Test name
Test status
Simulation time 171557266272 ps
CPU time 2184.92 seconds
Started Apr 25 01:54:47 PM PDT 24
Finished Apr 25 02:31:13 PM PDT 24
Peak memory 288048 kb
Host smart-e4f824dd-7687-4645-ac8b-2eaa70784831
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221916231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.221916231
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.725844012
Short name T217
Test name
Test status
Simulation time 9662351154 ps
CPU time 369.5 seconds
Started Apr 25 01:54:45 PM PDT 24
Finished Apr 25 02:00:55 PM PDT 24
Peak memory 247944 kb
Host smart-ff69918e-0393-46be-a63a-303bbb21c00f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725844012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.725844012
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.1511998215
Short name T330
Test name
Test status
Simulation time 5979190206 ps
CPU time 43.66 seconds
Started Apr 25 01:54:44 PM PDT 24
Finished Apr 25 01:55:28 PM PDT 24
Peak memory 256932 kb
Host smart-c8780df8-7eda-42c3-bfa7-ee2e0f53e19b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15119
98215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.1511998215
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.1316320119
Short name T355
Test name
Test status
Simulation time 247269279 ps
CPU time 10.36 seconds
Started Apr 25 01:54:48 PM PDT 24
Finished Apr 25 01:54:59 PM PDT 24
Peak memory 252324 kb
Host smart-57b5b6eb-40d2-4056-9584-4adf25aaf5f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13163
20119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.1316320119
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.1105613921
Short name T609
Test name
Test status
Simulation time 48374405 ps
CPU time 4.2 seconds
Started Apr 25 01:54:46 PM PDT 24
Finished Apr 25 01:54:50 PM PDT 24
Peak memory 240496 kb
Host smart-0e26ea2e-5285-483e-b126-c5ec648b7421
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11056
13921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.1105613921
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.886666558
Short name T451
Test name
Test status
Simulation time 570028911 ps
CPU time 21.93 seconds
Started Apr 25 01:54:37 PM PDT 24
Finished Apr 25 01:55:00 PM PDT 24
Peak memory 256492 kb
Host smart-7318bbb1-0881-40e1-8521-457d70659f97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88666
6558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.886666558
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.547526222
Short name T59
Test name
Test status
Simulation time 19184202464 ps
CPU time 1648.91 seconds
Started Apr 25 01:54:52 PM PDT 24
Finished Apr 25 02:22:22 PM PDT 24
Peak memory 289688 kb
Host smart-aeabc5f2-8d98-486e-91fe-b45e4e28b67f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547526222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_han
dler_stress_all.547526222
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.501161171
Short name T9
Test name
Test status
Simulation time 73576389836 ps
CPU time 1143.97 seconds
Started Apr 25 01:54:46 PM PDT 24
Finished Apr 25 02:13:51 PM PDT 24
Peak memory 281660 kb
Host smart-ef789f0b-07d1-4e0b-b4fd-db676b089e12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501161171 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.501161171
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.578277010
Short name T405
Test name
Test status
Simulation time 455651564676 ps
CPU time 1944.63 seconds
Started Apr 25 01:54:54 PM PDT 24
Finished Apr 25 02:27:20 PM PDT 24
Peak memory 284256 kb
Host smart-1d5cc07e-3b9b-47fa-8f61-6aff3dd8fe06
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578277010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.578277010
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.2974927429
Short name T426
Test name
Test status
Simulation time 1210102647 ps
CPU time 25.9 seconds
Started Apr 25 01:54:52 PM PDT 24
Finished Apr 25 01:55:18 PM PDT 24
Peak memory 249028 kb
Host smart-77a1b96d-6da1-47c7-98cc-ff81a05bcee0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29749
27429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.2974927429
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.3984829372
Short name T534
Test name
Test status
Simulation time 657584094 ps
CPU time 26.32 seconds
Started Apr 25 01:54:46 PM PDT 24
Finished Apr 25 01:55:13 PM PDT 24
Peak memory 255828 kb
Host smart-04c20378-98e6-4596-8104-d8b31b93865f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39848
29372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.3984829372
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.1276113925
Short name T681
Test name
Test status
Simulation time 32200513116 ps
CPU time 1696.27 seconds
Started Apr 25 01:54:55 PM PDT 24
Finished Apr 25 02:23:12 PM PDT 24
Peak memory 288956 kb
Host smart-c69b41e1-d16f-437c-880e-05a258c8045a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276113925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.1276113925
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.122410553
Short name T539
Test name
Test status
Simulation time 8791997604 ps
CPU time 178.92 seconds
Started Apr 25 01:54:53 PM PDT 24
Finished Apr 25 01:57:53 PM PDT 24
Peak memory 248144 kb
Host smart-d5480596-2a28-4cfa-87b6-d2b805fec8d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122410553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.122410553
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.3048138803
Short name T654
Test name
Test status
Simulation time 221416410 ps
CPU time 20.78 seconds
Started Apr 25 01:54:47 PM PDT 24
Finished Apr 25 01:55:08 PM PDT 24
Peak memory 248652 kb
Host smart-899c0754-8a62-4dda-a0bd-47d7b1d171a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30481
38803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.3048138803
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.4254310561
Short name T417
Test name
Test status
Simulation time 267701610 ps
CPU time 8.03 seconds
Started Apr 25 01:54:52 PM PDT 24
Finished Apr 25 01:55:01 PM PDT 24
Peak memory 250388 kb
Host smart-edc54309-7e92-4dd6-8516-32bfbee979be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42543
10561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.4254310561
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.2380619728
Short name T55
Test name
Test status
Simulation time 725203245 ps
CPU time 40.83 seconds
Started Apr 25 01:54:55 PM PDT 24
Finished Apr 25 01:55:36 PM PDT 24
Peak memory 255528 kb
Host smart-402d2704-6557-46c8-bcfd-daacbd97121f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23806
19728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.2380619728
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.864839033
Short name T11
Test name
Test status
Simulation time 906498494 ps
CPU time 59.62 seconds
Started Apr 25 01:54:47 PM PDT 24
Finished Apr 25 01:55:47 PM PDT 24
Peak memory 256000 kb
Host smart-9e17dacb-79b6-4d7c-bd67-8957d82f09ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86483
9033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.864839033
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.3735773024
Short name T67
Test name
Test status
Simulation time 10800279620 ps
CPU time 795.35 seconds
Started Apr 25 01:54:53 PM PDT 24
Finished Apr 25 02:08:09 PM PDT 24
Peak memory 273120 kb
Host smart-9a471434-5fca-4f26-bcde-7a9ecd06e274
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735773024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.3735773024
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.3724452883
Short name T258
Test name
Test status
Simulation time 62093803267 ps
CPU time 1647.29 seconds
Started Apr 25 01:55:21 PM PDT 24
Finished Apr 25 02:22:48 PM PDT 24
Peak memory 305948 kb
Host smart-aeb70e47-b277-4586-ad60-f0b0085e17db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724452883 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.3724452883
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.3051571738
Short name T259
Test name
Test status
Simulation time 232286233155 ps
CPU time 2217.47 seconds
Started Apr 25 01:54:52 PM PDT 24
Finished Apr 25 02:31:51 PM PDT 24
Peak memory 281592 kb
Host smart-18f28f32-4eea-4b5b-8cb8-af9e0f152aa4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051571738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.3051571738
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.2516248202
Short name T439
Test name
Test status
Simulation time 238673519 ps
CPU time 32.02 seconds
Started Apr 25 01:54:54 PM PDT 24
Finished Apr 25 01:55:27 PM PDT 24
Peak memory 256000 kb
Host smart-f43c1d1f-4a56-4c1d-b28c-4a70c55ce4c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25162
48202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.2516248202
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.3543041744
Short name T220
Test name
Test status
Simulation time 2406557597 ps
CPU time 67.63 seconds
Started Apr 25 01:54:56 PM PDT 24
Finished Apr 25 01:56:04 PM PDT 24
Peak memory 256116 kb
Host smart-5109e598-2be4-4d32-9f52-eeca65fa6e64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35430
41744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.3543041744
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.3384380490
Short name T278
Test name
Test status
Simulation time 30265694294 ps
CPU time 767.44 seconds
Started Apr 25 01:54:54 PM PDT 24
Finished Apr 25 02:07:43 PM PDT 24
Peak memory 273340 kb
Host smart-dae6d47e-d330-4c33-a1be-734dc1a8854a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384380490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.3384380490
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.2450535368
Short name T101
Test name
Test status
Simulation time 17318438070 ps
CPU time 1106.32 seconds
Started Apr 25 01:54:56 PM PDT 24
Finished Apr 25 02:13:23 PM PDT 24
Peak memory 281524 kb
Host smart-dace7d1d-fb53-4e63-bb8e-b19b76605f45
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450535368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.2450535368
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.2347184790
Short name T560
Test name
Test status
Simulation time 13100542918 ps
CPU time 512.49 seconds
Started Apr 25 01:54:54 PM PDT 24
Finished Apr 25 02:03:27 PM PDT 24
Peak memory 247912 kb
Host smart-e53565b4-2591-4b3b-a8af-058ec8923a24
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347184790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.2347184790
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.1552934345
Short name T602
Test name
Test status
Simulation time 489665754 ps
CPU time 7.82 seconds
Started Apr 25 01:54:52 PM PDT 24
Finished Apr 25 01:55:01 PM PDT 24
Peak memory 248748 kb
Host smart-41f23344-5989-4188-9178-ed1850d9ef99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15529
34345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.1552934345
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.952734789
Short name T436
Test name
Test status
Simulation time 637594585 ps
CPU time 26.36 seconds
Started Apr 25 01:54:53 PM PDT 24
Finished Apr 25 01:55:20 PM PDT 24
Peak memory 248780 kb
Host smart-94a954cc-712c-41dc-b577-594de7960611
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95273
4789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.952734789
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.2918085095
Short name T642
Test name
Test status
Simulation time 419515450 ps
CPU time 27.35 seconds
Started Apr 25 01:54:55 PM PDT 24
Finished Apr 25 01:55:23 PM PDT 24
Peak memory 255952 kb
Host smart-7121319b-6aed-4769-8622-b6d29e514676
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29180
85095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.2918085095
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.4229937764
Short name T71
Test name
Test status
Simulation time 1532772137 ps
CPU time 23.02 seconds
Started Apr 25 01:54:55 PM PDT 24
Finished Apr 25 01:55:18 PM PDT 24
Peak memory 248708 kb
Host smart-cf5bc3a6-9e98-41bb-ad10-26823154b02d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42299
37764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.4229937764
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.3619209808
Short name T485
Test name
Test status
Simulation time 100319652036 ps
CPU time 1561.47 seconds
Started Apr 25 01:54:56 PM PDT 24
Finished Apr 25 02:20:58 PM PDT 24
Peak memory 282704 kb
Host smart-171c8804-a377-4eb9-921e-382d8d42d05a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619209808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.3619209808
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.2944831832
Short name T688
Test name
Test status
Simulation time 99932348750 ps
CPU time 783.69 seconds
Started Apr 25 01:55:00 PM PDT 24
Finished Apr 25 02:08:04 PM PDT 24
Peak memory 272728 kb
Host smart-c1ff8edf-395e-4a7f-ab8d-703b6021fe09
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944831832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.2944831832
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.2514829273
Short name T437
Test name
Test status
Simulation time 5035518018 ps
CPU time 73.12 seconds
Started Apr 25 01:54:53 PM PDT 24
Finished Apr 25 01:56:07 PM PDT 24
Peak memory 256964 kb
Host smart-53087785-9d50-4028-b7e2-bbb6a732c58c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25148
29273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.2514829273
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.1214266346
Short name T328
Test name
Test status
Simulation time 353271654 ps
CPU time 6.24 seconds
Started Apr 25 01:54:52 PM PDT 24
Finished Apr 25 01:54:59 PM PDT 24
Peak memory 250888 kb
Host smart-a322dcf4-5b27-442d-af90-8fbcf802aa7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12142
66346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.1214266346
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.1142741204
Short name T636
Test name
Test status
Simulation time 20622639333 ps
CPU time 1544.19 seconds
Started Apr 25 01:55:01 PM PDT 24
Finished Apr 25 02:20:46 PM PDT 24
Peak memory 288512 kb
Host smart-b7647fbe-867b-4767-b9c6-2fae560b91d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142741204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.1142741204
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.2063331782
Short name T584
Test name
Test status
Simulation time 19896730282 ps
CPU time 1138.98 seconds
Started Apr 25 01:54:59 PM PDT 24
Finished Apr 25 02:13:59 PM PDT 24
Peak memory 272892 kb
Host smart-759fc44b-9bb3-448c-87be-c61e74c8d2b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063331782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.2063331782
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.1026285214
Short name T91
Test name
Test status
Simulation time 43800134485 ps
CPU time 314.93 seconds
Started Apr 25 01:55:01 PM PDT 24
Finished Apr 25 02:00:16 PM PDT 24
Peak memory 248216 kb
Host smart-6274f75c-710a-42d0-b6ca-42307ff7ef22
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026285214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.1026285214
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.1922449426
Short name T526
Test name
Test status
Simulation time 290346962 ps
CPU time 23.1 seconds
Started Apr 25 01:54:58 PM PDT 24
Finished Apr 25 01:55:22 PM PDT 24
Peak memory 256516 kb
Host smart-b5091fdc-4013-4200-9690-77071b990d1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19224
49426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.1922449426
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.26321116
Short name T381
Test name
Test status
Simulation time 1208772918 ps
CPU time 33.3 seconds
Started Apr 25 01:54:56 PM PDT 24
Finished Apr 25 01:55:30 PM PDT 24
Peak memory 255936 kb
Host smart-3f04fc60-e9af-46a1-9f2e-7f3b34f1223e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26321
116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.26321116
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.2907810099
Short name T277
Test name
Test status
Simulation time 610560103 ps
CPU time 18.69 seconds
Started Apr 25 01:55:03 PM PDT 24
Finished Apr 25 01:55:22 PM PDT 24
Peak memory 248724 kb
Host smart-8c7314b3-f989-4ca5-8b96-230a2c10fd78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29078
10099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.2907810099
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.1811761382
Short name T561
Test name
Test status
Simulation time 603240977 ps
CPU time 35.35 seconds
Started Apr 25 01:54:56 PM PDT 24
Finished Apr 25 01:55:32 PM PDT 24
Peak memory 248696 kb
Host smart-82af571a-980a-44e1-8e84-c2dba0043234
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18117
61382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.1811761382
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.1815048695
Short name T26
Test name
Test status
Simulation time 42620670768 ps
CPU time 594.86 seconds
Started Apr 25 01:55:01 PM PDT 24
Finished Apr 25 02:04:56 PM PDT 24
Peak memory 266204 kb
Host smart-ecff9147-6047-48d0-bf09-34c6cc690bf5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815048695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.1815048695
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.1587180394
Short name T84
Test name
Test status
Simulation time 26538709068 ps
CPU time 1564.35 seconds
Started Apr 25 01:55:04 PM PDT 24
Finished Apr 25 02:21:09 PM PDT 24
Peak memory 285780 kb
Host smart-d15e14a0-b057-4446-a2e8-62fc1199a7c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587180394 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.1587180394
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.2255280812
Short name T52
Test name
Test status
Simulation time 109033221 ps
CPU time 2.51 seconds
Started Apr 25 01:52:46 PM PDT 24
Finished Apr 25 01:52:49 PM PDT 24
Peak memory 248856 kb
Host smart-8e2a3f5b-6a6e-427c-9c2a-a07e0d9c823b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2255280812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.2255280812
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.2451018651
Short name T15
Test name
Test status
Simulation time 16024432716 ps
CPU time 1207.76 seconds
Started Apr 25 01:52:45 PM PDT 24
Finished Apr 25 02:12:53 PM PDT 24
Peak memory 289444 kb
Host smart-9a1668cb-8d4a-4938-800a-51e2c4303bee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451018651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.2451018651
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.3791663571
Short name T458
Test name
Test status
Simulation time 458799215 ps
CPU time 21.21 seconds
Started Apr 25 01:52:47 PM PDT 24
Finished Apr 25 01:53:08 PM PDT 24
Peak memory 248704 kb
Host smart-cfdedaac-d2e2-48e5-9410-231f2c1c7215
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3791663571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.3791663571
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.3577558851
Short name T553
Test name
Test status
Simulation time 2146438242 ps
CPU time 56.02 seconds
Started Apr 25 01:52:37 PM PDT 24
Finished Apr 25 01:53:34 PM PDT 24
Peak memory 256584 kb
Host smart-63f71aaa-ce0d-4439-93fd-068cc3de8567
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35775
58851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.3577558851
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.1247758367
Short name T683
Test name
Test status
Simulation time 592727119 ps
CPU time 7.77 seconds
Started Apr 25 01:52:38 PM PDT 24
Finished Apr 25 01:52:46 PM PDT 24
Peak memory 253540 kb
Host smart-a5a45edd-e6fd-4c3f-bc81-ec1ac33b329f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12477
58367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.1247758367
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.1619317029
Short name T304
Test name
Test status
Simulation time 25174700732 ps
CPU time 1124.59 seconds
Started Apr 25 01:52:42 PM PDT 24
Finished Apr 25 02:11:28 PM PDT 24
Peak memory 285416 kb
Host smart-3904d693-3362-4011-be6d-3dd963ea9a9b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619317029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.1619317029
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.2334607298
Short name T275
Test name
Test status
Simulation time 21730725420 ps
CPU time 917.92 seconds
Started Apr 25 01:52:39 PM PDT 24
Finished Apr 25 02:07:58 PM PDT 24
Peak memory 273384 kb
Host smart-520a5cea-6365-4f83-88c9-18070d628bb8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334607298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.2334607298
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.1566608638
Short name T505
Test name
Test status
Simulation time 197637250 ps
CPU time 18.99 seconds
Started Apr 25 01:52:39 PM PDT 24
Finished Apr 25 01:52:58 PM PDT 24
Peak memory 248724 kb
Host smart-7b8cc74a-09eb-45f5-a276-96092d35729f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15666
08638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.1566608638
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.4202042475
Short name T601
Test name
Test status
Simulation time 634112626 ps
CPU time 27.55 seconds
Started Apr 25 01:52:48 PM PDT 24
Finished Apr 25 01:53:16 PM PDT 24
Peak memory 249048 kb
Host smart-3079e1b2-9084-468e-8aa4-dcb6faa53434
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42020
42475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.4202042475
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.2539388685
Short name T597
Test name
Test status
Simulation time 261238499 ps
CPU time 9.21 seconds
Started Apr 25 01:52:42 PM PDT 24
Finished Apr 25 01:52:51 PM PDT 24
Peak memory 254184 kb
Host smart-7dd518d6-4893-4e49-8d7f-4b18cfb080ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25393
88685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.2539388685
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.1896759937
Short name T440
Test name
Test status
Simulation time 227935526 ps
CPU time 17.58 seconds
Started Apr 25 01:52:45 PM PDT 24
Finished Apr 25 01:53:03 PM PDT 24
Peak memory 248632 kb
Host smart-87e35955-5161-456f-8e98-3f883b435fcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18967
59937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.1896759937
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.1902347565
Short name T662
Test name
Test status
Simulation time 54037859878 ps
CPU time 2857.89 seconds
Started Apr 25 01:52:49 PM PDT 24
Finished Apr 25 02:40:27 PM PDT 24
Peak memory 289036 kb
Host smart-9994da46-f21f-4a8a-9152-a19d92c2f0d6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902347565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.1902347565
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.3560670146
Short name T89
Test name
Test status
Simulation time 77679949540 ps
CPU time 1577.3 seconds
Started Apr 25 01:52:45 PM PDT 24
Finished Apr 25 02:19:03 PM PDT 24
Peak memory 305132 kb
Host smart-036e37b0-a9da-4da7-9b3b-38edd0d9f449
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560670146 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.3560670146
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.62551678
Short name T525
Test name
Test status
Simulation time 51948088385 ps
CPU time 1862.25 seconds
Started Apr 25 01:55:00 PM PDT 24
Finished Apr 25 02:26:02 PM PDT 24
Peak memory 281572 kb
Host smart-78563950-2611-4413-aa00-62d295bc93d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62551678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.62551678
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.1094455754
Short name T263
Test name
Test status
Simulation time 16725660413 ps
CPU time 129.77 seconds
Started Apr 25 01:54:59 PM PDT 24
Finished Apr 25 01:57:10 PM PDT 24
Peak memory 256900 kb
Host smart-639bc9cf-a5de-4609-893c-65ee2b82b0ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10944
55754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.1094455754
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.137474242
Short name T211
Test name
Test status
Simulation time 78291631380 ps
CPU time 1527.51 seconds
Started Apr 25 01:55:00 PM PDT 24
Finished Apr 25 02:20:28 PM PDT 24
Peak memory 289224 kb
Host smart-72c73746-939c-48f7-9bd7-0818459490b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137474242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.137474242
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.2076289971
Short name T518
Test name
Test status
Simulation time 19484586432 ps
CPU time 1087.39 seconds
Started Apr 25 01:54:59 PM PDT 24
Finished Apr 25 02:13:07 PM PDT 24
Peak memory 273320 kb
Host smart-8417fde7-9f9b-49f6-bd98-05b8ed8623a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076289971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.2076289971
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.3479445170
Short name T697
Test name
Test status
Simulation time 7310868411 ps
CPU time 288.4 seconds
Started Apr 25 01:55:01 PM PDT 24
Finished Apr 25 01:59:50 PM PDT 24
Peak memory 248256 kb
Host smart-18e78136-dc20-4f45-8230-19cdc7a91a14
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479445170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.3479445170
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.4155342565
Short name T44
Test name
Test status
Simulation time 127946396 ps
CPU time 4.6 seconds
Started Apr 25 01:55:02 PM PDT 24
Finished Apr 25 01:55:07 PM PDT 24
Peak memory 240520 kb
Host smart-3c528f59-8f17-4b7c-aeff-c88b3a161cba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41553
42565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.4155342565
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.216483184
Short name T482
Test name
Test status
Simulation time 506343301 ps
CPU time 30.03 seconds
Started Apr 25 01:55:01 PM PDT 24
Finished Apr 25 01:55:32 PM PDT 24
Peak memory 255952 kb
Host smart-bf111e3b-9d1e-4a6a-9ad2-e9e8de61c6d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21648
3184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.216483184
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.1020421306
Short name T532
Test name
Test status
Simulation time 1142794207 ps
CPU time 37.66 seconds
Started Apr 25 01:55:03 PM PDT 24
Finished Apr 25 01:55:41 PM PDT 24
Peak memory 256408 kb
Host smart-b3bd1b95-629e-4bfe-857b-600b25646a0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10204
21306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.1020421306
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.3399799131
Short name T483
Test name
Test status
Simulation time 809325035 ps
CPU time 46.6 seconds
Started Apr 25 01:55:03 PM PDT 24
Finished Apr 25 01:55:50 PM PDT 24
Peak memory 248712 kb
Host smart-7dee5929-28d1-4375-bea8-5b1c906524d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33997
99131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.3399799131
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.2061726057
Short name T248
Test name
Test status
Simulation time 33950155900 ps
CPU time 1869.16 seconds
Started Apr 25 01:55:02 PM PDT 24
Finished Apr 25 02:26:12 PM PDT 24
Peak memory 288420 kb
Host smart-54cfef0b-d4b5-41db-8165-8ee264b3d24d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061726057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.2061726057
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.146696715
Short name T112
Test name
Test status
Simulation time 31095650512 ps
CPU time 257.08 seconds
Started Apr 25 01:55:00 PM PDT 24
Finished Apr 25 01:59:17 PM PDT 24
Peak memory 251452 kb
Host smart-237f8415-b595-4fdc-9fa9-b6d39f457c55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14669
6715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.146696715
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.3629907983
Short name T376
Test name
Test status
Simulation time 241777667 ps
CPU time 21.1 seconds
Started Apr 25 01:55:04 PM PDT 24
Finished Apr 25 01:55:26 PM PDT 24
Peak memory 255888 kb
Host smart-9035ead7-adf3-4e84-8752-dc8e0c47db86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36299
07983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.3629907983
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.3224452728
Short name T121
Test name
Test status
Simulation time 91368292067 ps
CPU time 2349.67 seconds
Started Apr 25 01:55:06 PM PDT 24
Finished Apr 25 02:34:16 PM PDT 24
Peak memory 289660 kb
Host smart-2ff5efc2-4e7f-4c3b-a35a-78bfd91ea1d6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224452728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.3224452728
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.1002685015
Short name T545
Test name
Test status
Simulation time 57840148837 ps
CPU time 1247.97 seconds
Started Apr 25 01:55:04 PM PDT 24
Finished Apr 25 02:15:53 PM PDT 24
Peak memory 285876 kb
Host smart-f46d0700-033c-46e7-869e-5aaeba854cc5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002685015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.1002685015
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.394393810
Short name T551
Test name
Test status
Simulation time 16507415373 ps
CPU time 340.83 seconds
Started Apr 25 01:55:06 PM PDT 24
Finished Apr 25 02:00:47 PM PDT 24
Peak memory 248024 kb
Host smart-87b0c1ce-d1d7-4f65-a779-bb42be0c6bc0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394393810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.394393810
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.319077346
Short name T218
Test name
Test status
Simulation time 215418085 ps
CPU time 11.11 seconds
Started Apr 25 01:55:03 PM PDT 24
Finished Apr 25 01:55:15 PM PDT 24
Peak memory 248712 kb
Host smart-50299920-d189-4827-9690-6dec456aab2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31907
7346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.319077346
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.3532042843
Short name T471
Test name
Test status
Simulation time 1748754187 ps
CPU time 51.86 seconds
Started Apr 25 01:55:01 PM PDT 24
Finished Apr 25 01:55:53 PM PDT 24
Peak memory 255940 kb
Host smart-26b877c1-80b6-4fb6-8dca-a11243e15ea2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35320
42843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.3532042843
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.3917152336
Short name T102
Test name
Test status
Simulation time 1320544795 ps
CPU time 26.45 seconds
Started Apr 25 01:55:02 PM PDT 24
Finished Apr 25 01:55:29 PM PDT 24
Peak memory 254712 kb
Host smart-0106f9ba-0c41-4e97-8e3a-41e26f757dc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39171
52336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.3917152336
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.2700039938
Short name T470
Test name
Test status
Simulation time 545164963 ps
CPU time 30.57 seconds
Started Apr 25 01:55:00 PM PDT 24
Finished Apr 25 01:55:32 PM PDT 24
Peak memory 248700 kb
Host smart-02194be1-91b8-46fb-9839-87fc28bcae41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27000
39938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.2700039938
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.3167115406
Short name T580
Test name
Test status
Simulation time 447802493 ps
CPU time 44.41 seconds
Started Apr 25 01:55:08 PM PDT 24
Finished Apr 25 01:55:53 PM PDT 24
Peak memory 256808 kb
Host smart-5d0161db-3f7a-404e-a6cf-a0b674218ab5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167115406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.3167115406
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.2384318468
Short name T113
Test name
Test status
Simulation time 95679728919 ps
CPU time 1089.48 seconds
Started Apr 25 01:55:12 PM PDT 24
Finished Apr 25 02:13:22 PM PDT 24
Peak memory 281500 kb
Host smart-a69a7689-716a-481f-bc1a-8d63f57c47c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384318468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.2384318468
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.3102192419
Short name T342
Test name
Test status
Simulation time 8052323799 ps
CPU time 223.98 seconds
Started Apr 25 01:55:05 PM PDT 24
Finished Apr 25 01:58:49 PM PDT 24
Peak memory 256916 kb
Host smart-4f9265ae-6813-4575-82d4-41a3b23d25de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31021
92419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.3102192419
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.1348667885
Short name T645
Test name
Test status
Simulation time 280184722 ps
CPU time 16.57 seconds
Started Apr 25 01:55:04 PM PDT 24
Finished Apr 25 01:55:21 PM PDT 24
Peak memory 248684 kb
Host smart-bf9ca651-2b80-4ab9-a8d6-990b48f2b57c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13486
67885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.1348667885
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.3554165105
Short name T519
Test name
Test status
Simulation time 18910123461 ps
CPU time 1286.96 seconds
Started Apr 25 01:55:13 PM PDT 24
Finished Apr 25 02:16:41 PM PDT 24
Peak memory 289460 kb
Host smart-6e56d7a2-0660-4516-b5c8-e0bd5d880fd7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554165105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.3554165105
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.2538413359
Short name T336
Test name
Test status
Simulation time 157582213 ps
CPU time 6.32 seconds
Started Apr 25 01:55:04 PM PDT 24
Finished Apr 25 01:55:11 PM PDT 24
Peak memory 250920 kb
Host smart-f6e5420e-8180-48a5-a444-4dba42b4c2cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25384
13359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.2538413359
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.3590293212
Short name T502
Test name
Test status
Simulation time 273573676 ps
CPU time 12.15 seconds
Started Apr 25 01:55:05 PM PDT 24
Finished Apr 25 01:55:18 PM PDT 24
Peak memory 248668 kb
Host smart-fddc0085-11a1-4c98-9841-206085df8b1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35902
93212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.3590293212
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.921796763
Short name T58
Test name
Test status
Simulation time 115370473 ps
CPU time 6.66 seconds
Started Apr 25 01:55:04 PM PDT 24
Finished Apr 25 01:55:11 PM PDT 24
Peak memory 248704 kb
Host smart-af0880f1-897a-490b-830c-ad849e8add1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92179
6763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.921796763
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.1434534506
Short name T406
Test name
Test status
Simulation time 2235433649 ps
CPU time 31.62 seconds
Started Apr 25 01:55:13 PM PDT 24
Finished Apr 25 01:55:46 PM PDT 24
Peak memory 248772 kb
Host smart-0779d51a-8161-4bbf-b1ec-a855dda1af97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14345
34506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.1434534506
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.2340324929
Short name T511
Test name
Test status
Simulation time 601511351 ps
CPU time 31.53 seconds
Started Apr 25 01:55:14 PM PDT 24
Finished Apr 25 01:55:46 PM PDT 24
Peak memory 256060 kb
Host smart-b861ffa9-e96d-4926-bcce-db001df3d145
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340324929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.2340324929
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.900402218
Short name T29
Test name
Test status
Simulation time 34284800131 ps
CPU time 2916.53 seconds
Started Apr 25 01:55:13 PM PDT 24
Finished Apr 25 02:43:51 PM PDT 24
Peak memory 305692 kb
Host smart-4dfc0040-3c42-4f33-a516-668ca6df78b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900402218 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.900402218
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.4201123894
Short name T555
Test name
Test status
Simulation time 42874455673 ps
CPU time 1205.36 seconds
Started Apr 25 01:55:19 PM PDT 24
Finished Apr 25 02:15:25 PM PDT 24
Peak memory 268236 kb
Host smart-18f82969-5f1d-46a7-98d3-b1ef3859c6c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201123894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.4201123894
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.2506584510
Short name T628
Test name
Test status
Simulation time 1184456857 ps
CPU time 61.7 seconds
Started Apr 25 01:55:17 PM PDT 24
Finished Apr 25 01:56:19 PM PDT 24
Peak memory 256412 kb
Host smart-df0d121e-6099-47b7-b7be-9bcd83d85365
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25065
84510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.2506584510
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.3807151578
Short name T606
Test name
Test status
Simulation time 1943675079 ps
CPU time 63.43 seconds
Started Apr 25 01:55:13 PM PDT 24
Finished Apr 25 01:56:17 PM PDT 24
Peak memory 255720 kb
Host smart-aad15b08-b077-48ef-9b5f-a95ec377adb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38071
51578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.3807151578
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.771370441
Short name T310
Test name
Test status
Simulation time 174000394848 ps
CPU time 1967.96 seconds
Started Apr 25 01:55:18 PM PDT 24
Finished Apr 25 02:28:07 PM PDT 24
Peak memory 273292 kb
Host smart-e5f8aa4f-f391-4e1c-a544-7c0db8fd6a35
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771370441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.771370441
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.2202136571
Short name T428
Test name
Test status
Simulation time 41315158361 ps
CPU time 1723.46 seconds
Started Apr 25 01:55:18 PM PDT 24
Finished Apr 25 02:24:02 PM PDT 24
Peak memory 273312 kb
Host smart-af2c7cda-386b-46d9-a650-996407bf8519
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202136571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.2202136571
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.1491426539
Short name T293
Test name
Test status
Simulation time 20128245053 ps
CPU time 414.29 seconds
Started Apr 25 01:55:18 PM PDT 24
Finished Apr 25 02:02:13 PM PDT 24
Peak memory 247068 kb
Host smart-9d059c0c-115b-4870-8d33-35f32d3d02c0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491426539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.1491426539
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.1050885062
Short name T488
Test name
Test status
Simulation time 7276512635 ps
CPU time 32.78 seconds
Started Apr 25 01:55:13 PM PDT 24
Finished Apr 25 01:55:47 PM PDT 24
Peak memory 248868 kb
Host smart-40d1c294-e591-4cf6-8706-902bf6cc6054
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10508
85062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.1050885062
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.2433238730
Short name T631
Test name
Test status
Simulation time 1642809989 ps
CPU time 25.41 seconds
Started Apr 25 01:55:12 PM PDT 24
Finished Apr 25 01:55:39 PM PDT 24
Peak memory 255884 kb
Host smart-4c7cde9b-399d-413d-b133-b039c7a1f76d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24332
38730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.2433238730
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.3344403985
Short name T521
Test name
Test status
Simulation time 1607244200 ps
CPU time 26.61 seconds
Started Apr 25 01:55:14 PM PDT 24
Finished Apr 25 01:55:41 PM PDT 24
Peak memory 255784 kb
Host smart-cc2b45f8-8a74-4fad-a8d4-e83711a0a629
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33444
03985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.3344403985
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.4096113340
Short name T245
Test name
Test status
Simulation time 66138250448 ps
CPU time 1277.69 seconds
Started Apr 25 01:55:18 PM PDT 24
Finished Apr 25 02:16:37 PM PDT 24
Peak memory 289704 kb
Host smart-21cedf32-930e-4a6e-8218-54b186b6a08d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096113340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.4096113340
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.3124426979
Short name T31
Test name
Test status
Simulation time 157059033828 ps
CPU time 4283.04 seconds
Started Apr 25 01:55:19 PM PDT 24
Finished Apr 25 03:06:43 PM PDT 24
Peak memory 337224 kb
Host smart-608c38b7-9a06-4ea2-bb30-3336aa8564eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124426979 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.3124426979
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.2092532443
Short name T216
Test name
Test status
Simulation time 10405085654 ps
CPU time 135.62 seconds
Started Apr 25 01:55:24 PM PDT 24
Finished Apr 25 01:57:40 PM PDT 24
Peak memory 256936 kb
Host smart-53d1f28a-b763-4d84-bb9d-99f0bb89697f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20925
32443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.2092532443
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.98680688
Short name T347
Test name
Test status
Simulation time 1277527921 ps
CPU time 28.32 seconds
Started Apr 25 01:55:24 PM PDT 24
Finished Apr 25 01:55:53 PM PDT 24
Peak memory 248984 kb
Host smart-7574ac53-c368-4ea1-ac8d-eb1309a2dbed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98680
688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.98680688
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.3581035392
Short name T314
Test name
Test status
Simulation time 57290045972 ps
CPU time 1655.66 seconds
Started Apr 25 01:55:24 PM PDT 24
Finished Apr 25 02:23:00 PM PDT 24
Peak memory 271400 kb
Host smart-8b942760-844d-491c-8f88-14210c9970fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581035392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.3581035392
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.2845690065
Short name T117
Test name
Test status
Simulation time 3887223964 ps
CPU time 44.43 seconds
Started Apr 25 01:55:18 PM PDT 24
Finished Apr 25 01:56:03 PM PDT 24
Peak memory 248740 kb
Host smart-4823fa11-cf7d-41c9-b93f-06b5a9ea0603
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28456
90065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.2845690065
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.2791383289
Short name T695
Test name
Test status
Simulation time 1655818658 ps
CPU time 25.94 seconds
Started Apr 25 01:55:19 PM PDT 24
Finished Apr 25 01:55:45 PM PDT 24
Peak memory 255912 kb
Host smart-0b208c26-002b-43be-a7a3-b7fd7f342c7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27913
83289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.2791383289
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.343089542
Short name T685
Test name
Test status
Simulation time 372617942 ps
CPU time 21.96 seconds
Started Apr 25 01:55:22 PM PDT 24
Finished Apr 25 01:55:44 PM PDT 24
Peak memory 256844 kb
Host smart-67a64cbb-274b-4727-aaeb-9972476bef6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34308
9542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.343089542
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.572285040
Short name T365
Test name
Test status
Simulation time 1817795442 ps
CPU time 14.66 seconds
Started Apr 25 01:55:19 PM PDT 24
Finished Apr 25 01:55:34 PM PDT 24
Peak memory 254632 kb
Host smart-377077b0-66a8-47d2-8f43-a196e6c728ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57228
5040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.572285040
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.384994576
Short name T413
Test name
Test status
Simulation time 2214346710 ps
CPU time 129.53 seconds
Started Apr 25 01:55:29 PM PDT 24
Finished Apr 25 01:57:40 PM PDT 24
Peak memory 256404 kb
Host smart-f0cbf753-5926-404b-a5c1-e3a255240c71
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384994576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_han
dler_stress_all.384994576
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.3571730202
Short name T593
Test name
Test status
Simulation time 100134208455 ps
CPU time 1296.77 seconds
Started Apr 25 01:55:29 PM PDT 24
Finished Apr 25 02:17:07 PM PDT 24
Peak memory 272644 kb
Host smart-8a7b8af4-a899-46e5-acb8-ce48ba777549
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571730202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.3571730202
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.1677396638
Short name T403
Test name
Test status
Simulation time 1084972364 ps
CPU time 92.06 seconds
Started Apr 25 01:55:29 PM PDT 24
Finished Apr 25 01:57:02 PM PDT 24
Peak memory 250180 kb
Host smart-7859e01c-58b6-4d60-a4d6-e2ced06a0bdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16773
96638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.1677396638
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.2220215622
Short name T88
Test name
Test status
Simulation time 599894557 ps
CPU time 37.75 seconds
Started Apr 25 01:55:30 PM PDT 24
Finished Apr 25 01:56:08 PM PDT 24
Peak memory 249100 kb
Host smart-648298f8-4234-4a3e-9538-f5f4ec32cf1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22202
15622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.2220215622
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.2215547134
Short name T309
Test name
Test status
Simulation time 635652115592 ps
CPU time 2516.83 seconds
Started Apr 25 01:55:39 PM PDT 24
Finished Apr 25 02:37:37 PM PDT 24
Peak memory 289412 kb
Host smart-ac27f4ed-1ac0-4d2f-a2af-c754a9fa23a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215547134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.2215547134
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.4151846065
Short name T513
Test name
Test status
Simulation time 37758360483 ps
CPU time 2020.46 seconds
Started Apr 25 01:55:37 PM PDT 24
Finished Apr 25 02:29:18 PM PDT 24
Peak memory 273032 kb
Host smart-420e6b00-9fa2-4090-9ba6-5ce0e22a9e70
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151846065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.4151846065
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.500077184
Short name T294
Test name
Test status
Simulation time 65881220370 ps
CPU time 527.12 seconds
Started Apr 25 01:55:36 PM PDT 24
Finished Apr 25 02:04:23 PM PDT 24
Peak memory 248280 kb
Host smart-08f9fcd6-8681-4dd8-99ac-610463a3ba3b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500077184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.500077184
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.274014044
Short name T270
Test name
Test status
Simulation time 327065264 ps
CPU time 8.53 seconds
Started Apr 25 01:55:31 PM PDT 24
Finished Apr 25 01:55:40 PM PDT 24
Peak memory 248648 kb
Host smart-320b543a-223c-44c7-aebf-4ad2950c95a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27401
4044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.274014044
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.1587087115
Short name T423
Test name
Test status
Simulation time 397879904 ps
CPU time 11.65 seconds
Started Apr 25 01:55:30 PM PDT 24
Finished Apr 25 01:55:42 PM PDT 24
Peak memory 253268 kb
Host smart-4a69e5cb-fa9e-4ef6-80e3-f9bdbf980226
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15870
87115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.1587087115
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.2866295346
Short name T357
Test name
Test status
Simulation time 9110821581 ps
CPU time 36.96 seconds
Started Apr 25 01:55:30 PM PDT 24
Finished Apr 25 01:56:07 PM PDT 24
Peak memory 255480 kb
Host smart-26c24184-5771-4a0c-a60f-45ab55faaa8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28662
95346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.2866295346
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.376014890
Short name T504
Test name
Test status
Simulation time 90313570 ps
CPU time 9.13 seconds
Started Apr 25 01:55:29 PM PDT 24
Finished Apr 25 01:55:39 PM PDT 24
Peak memory 248680 kb
Host smart-64eb2455-092a-4222-b4af-8d01df072397
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37601
4890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.376014890
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.2979832843
Short name T615
Test name
Test status
Simulation time 43739801742 ps
CPU time 1426.4 seconds
Started Apr 25 01:55:36 PM PDT 24
Finished Apr 25 02:19:24 PM PDT 24
Peak memory 273384 kb
Host smart-a866ed43-347a-4a11-b1d9-9e1524e0347b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979832843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.2979832843
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.2641877800
Short name T491
Test name
Test status
Simulation time 26061459229 ps
CPU time 1733.2 seconds
Started Apr 25 01:55:36 PM PDT 24
Finished Apr 25 02:24:30 PM PDT 24
Peak memory 273208 kb
Host smart-6e1ea055-e522-41df-aa28-df47fb1d41a9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641877800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.2641877800
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.4209872803
Short name T617
Test name
Test status
Simulation time 1167715667 ps
CPU time 65.57 seconds
Started Apr 25 01:55:40 PM PDT 24
Finished Apr 25 01:56:46 PM PDT 24
Peak memory 248648 kb
Host smart-2c9f6147-71c9-4b4c-adc3-560f8756bb56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42098
72803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.4209872803
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.1253112505
Short name T582
Test name
Test status
Simulation time 158075995 ps
CPU time 15.06 seconds
Started Apr 25 01:55:35 PM PDT 24
Finished Apr 25 01:55:50 PM PDT 24
Peak memory 255860 kb
Host smart-9fa327a1-b07d-41b4-8235-f16a69d4439a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12531
12505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.1253112505
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.3175725549
Short name T672
Test name
Test status
Simulation time 10747989895 ps
CPU time 1087.98 seconds
Started Apr 25 01:55:35 PM PDT 24
Finished Apr 25 02:13:44 PM PDT 24
Peak memory 289268 kb
Host smart-d32be14c-49b0-46bc-b0cb-4932fd60a266
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175725549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.3175725549
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.2381212361
Short name T604
Test name
Test status
Simulation time 12356265782 ps
CPU time 1042.94 seconds
Started Apr 25 01:55:38 PM PDT 24
Finished Apr 25 02:13:02 PM PDT 24
Peak memory 289028 kb
Host smart-c4c6531a-51b0-4d35-b701-b43ca824a6a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381212361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.2381212361
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.3276015880
Short name T679
Test name
Test status
Simulation time 6911817538 ps
CPU time 290.49 seconds
Started Apr 25 01:55:40 PM PDT 24
Finished Apr 25 02:00:31 PM PDT 24
Peak memory 247820 kb
Host smart-ba8c3f49-5bfb-4f19-bb4e-4b306bee484c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276015880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.3276015880
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.1936867376
Short name T273
Test name
Test status
Simulation time 797623434 ps
CPU time 13.86 seconds
Started Apr 25 01:55:36 PM PDT 24
Finished Apr 25 01:55:50 PM PDT 24
Peak memory 248688 kb
Host smart-b1e4142c-5f85-43f5-9535-b631f021e7fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19368
67376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.1936867376
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.4118383969
Short name T629
Test name
Test status
Simulation time 1947372515 ps
CPU time 28.64 seconds
Started Apr 25 01:55:35 PM PDT 24
Finished Apr 25 01:56:04 PM PDT 24
Peak memory 248664 kb
Host smart-0e614a2d-b780-487a-ab3f-8762ca0729ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41183
83969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.4118383969
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.3692740369
Short name T598
Test name
Test status
Simulation time 821302415 ps
CPU time 27.43 seconds
Started Apr 25 01:55:36 PM PDT 24
Finished Apr 25 01:56:04 PM PDT 24
Peak memory 248716 kb
Host smart-9032a1de-e6fb-4eee-819d-08e7b1d003bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36927
40369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.3692740369
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.1342414384
Short name T648
Test name
Test status
Simulation time 214834882 ps
CPU time 15.24 seconds
Started Apr 25 01:55:36 PM PDT 24
Finished Apr 25 01:55:52 PM PDT 24
Peak memory 248700 kb
Host smart-8ae0a01e-61ad-4512-9eac-f9e52d9cb35e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13424
14384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.1342414384
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.1166295016
Short name T34
Test name
Test status
Simulation time 51006127795 ps
CPU time 373.61 seconds
Started Apr 25 01:55:37 PM PDT 24
Finished Apr 25 02:01:51 PM PDT 24
Peak memory 256996 kb
Host smart-34c2d9ae-2ea8-4136-ae2f-c5baaa9a635c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166295016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.1166295016
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.592314297
Short name T83
Test name
Test status
Simulation time 62763096234 ps
CPU time 950.51 seconds
Started Apr 25 01:55:41 PM PDT 24
Finished Apr 25 02:11:33 PM PDT 24
Peak memory 273156 kb
Host smart-05611c2c-56cc-4efa-ba6e-a9bafd0cde0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592314297 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.592314297
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.2752085626
Short name T345
Test name
Test status
Simulation time 936318018 ps
CPU time 72.2 seconds
Started Apr 25 01:55:41 PM PDT 24
Finished Apr 25 01:56:54 PM PDT 24
Peak memory 248968 kb
Host smart-a33b0f7b-dd09-4c15-a28f-1a5233b4ee54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27520
85626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.2752085626
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.1978216677
Short name T644
Test name
Test status
Simulation time 556448821 ps
CPU time 15.66 seconds
Started Apr 25 01:55:41 PM PDT 24
Finished Apr 25 01:55:58 PM PDT 24
Peak memory 255444 kb
Host smart-ef888797-43c0-4192-a117-d1d950dd6e3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19782
16677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.1978216677
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.660728721
Short name T522
Test name
Test status
Simulation time 130941566953 ps
CPU time 1916.01 seconds
Started Apr 25 01:55:47 PM PDT 24
Finished Apr 25 02:27:45 PM PDT 24
Peak memory 281528 kb
Host smart-1b26e7db-54d7-4b0f-9016-e3f446328afe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660728721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.660728721
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.188542930
Short name T538
Test name
Test status
Simulation time 38918273747 ps
CPU time 1371.8 seconds
Started Apr 25 01:55:47 PM PDT 24
Finished Apr 25 02:18:40 PM PDT 24
Peak memory 272480 kb
Host smart-e061eabf-d22b-4399-8b04-61653e574765
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188542930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.188542930
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.2493706462
Short name T295
Test name
Test status
Simulation time 28991646396 ps
CPU time 592.55 seconds
Started Apr 25 01:55:48 PM PDT 24
Finished Apr 25 02:05:41 PM PDT 24
Peak memory 255204 kb
Host smart-599602b0-e413-4aee-97a8-3cee95ad505f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493706462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.2493706462
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.2687308196
Short name T223
Test name
Test status
Simulation time 885184591 ps
CPU time 49.81 seconds
Started Apr 25 01:55:41 PM PDT 24
Finished Apr 25 01:56:32 PM PDT 24
Peak memory 248712 kb
Host smart-c7308c2c-596e-4a29-833a-84eac531d8f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26873
08196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.2687308196
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.1882178259
Short name T373
Test name
Test status
Simulation time 3418582032 ps
CPU time 38.74 seconds
Started Apr 25 01:55:44 PM PDT 24
Finished Apr 25 01:56:23 PM PDT 24
Peak memory 256876 kb
Host smart-32e19f3d-4274-475d-b0ce-4fb71961a315
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18821
78259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.1882178259
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.2567287414
Short name T446
Test name
Test status
Simulation time 398296110 ps
CPU time 22.93 seconds
Started Apr 25 01:55:43 PM PDT 24
Finished Apr 25 01:56:07 PM PDT 24
Peak memory 255516 kb
Host smart-59954f98-a2d1-4035-9d36-9c9265bfdbee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25672
87414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.2567287414
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.2810354391
Short name T572
Test name
Test status
Simulation time 244621791 ps
CPU time 11.05 seconds
Started Apr 25 01:55:40 PM PDT 24
Finished Apr 25 01:55:51 PM PDT 24
Peak memory 255764 kb
Host smart-02017c44-463a-4082-8a0e-21673d4929ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28103
54391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.2810354391
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.6106157
Short name T427
Test name
Test status
Simulation time 58022594067 ps
CPU time 1378.2 seconds
Started Apr 25 01:55:48 PM PDT 24
Finished Apr 25 02:18:47 PM PDT 24
Peak memory 289276 kb
Host smart-720658bc-f6de-4b55-b357-1fb65ef37384
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6106157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handl
er_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handl
er_stress_all.6106157
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.1706084291
Short name T214
Test name
Test status
Simulation time 77557403572 ps
CPU time 1180.11 seconds
Started Apr 25 01:55:52 PM PDT 24
Finished Apr 25 02:15:33 PM PDT 24
Peak memory 273284 kb
Host smart-05538be9-5732-4fc6-b31f-c227c286effb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706084291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.1706084291
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.2509698039
Short name T401
Test name
Test status
Simulation time 9483258855 ps
CPU time 139.61 seconds
Started Apr 25 01:55:51 PM PDT 24
Finished Apr 25 01:58:12 PM PDT 24
Peak memory 256840 kb
Host smart-be9eb52b-0471-4aa7-8947-ff6aad2dacbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25096
98039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.2509698039
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.1629271188
Short name T361
Test name
Test status
Simulation time 670600579 ps
CPU time 14.71 seconds
Started Apr 25 01:55:53 PM PDT 24
Finished Apr 25 01:56:08 PM PDT 24
Peak memory 248720 kb
Host smart-e59c0519-8577-490e-b5eb-08dc78348b06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16292
71188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.1629271188
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.470917907
Short name T453
Test name
Test status
Simulation time 32042019274 ps
CPU time 762.36 seconds
Started Apr 25 01:55:53 PM PDT 24
Finished Apr 25 02:08:36 PM PDT 24
Peak memory 267204 kb
Host smart-d4885a49-328c-4be9-8dd8-5c1daf0144c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470917907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.470917907
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.1234482670
Short name T419
Test name
Test status
Simulation time 33522646479 ps
CPU time 1686.06 seconds
Started Apr 25 01:55:51 PM PDT 24
Finished Apr 25 02:23:58 PM PDT 24
Peak memory 273332 kb
Host smart-5a448f81-8b6a-4e4a-955b-89824a63b7ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234482670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.1234482670
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.621865071
Short name T524
Test name
Test status
Simulation time 1197902313 ps
CPU time 60.48 seconds
Started Apr 25 01:55:45 PM PDT 24
Finished Apr 25 01:56:46 PM PDT 24
Peak memory 256900 kb
Host smart-cde9d8d2-ed60-4640-9d52-4af965d212f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62186
5071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.621865071
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.4184834329
Short name T69
Test name
Test status
Simulation time 5041388390 ps
CPU time 77.21 seconds
Started Apr 25 01:55:52 PM PDT 24
Finished Apr 25 01:57:10 PM PDT 24
Peak memory 248776 kb
Host smart-cd12d69e-10f8-4ee2-94af-ffcd2d68b4a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41848
34329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.4184834329
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.3934598591
Short name T82
Test name
Test status
Simulation time 204621868 ps
CPU time 9.71 seconds
Started Apr 25 01:55:51 PM PDT 24
Finished Apr 25 01:56:01 PM PDT 24
Peak memory 255532 kb
Host smart-447de249-22d3-4faf-ba96-3d8727a6a0ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39345
98591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.3934598591
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.1831128502
Short name T576
Test name
Test status
Simulation time 363355254 ps
CPU time 30.39 seconds
Started Apr 25 01:55:46 PM PDT 24
Finished Apr 25 01:56:17 PM PDT 24
Peak memory 248720 kb
Host smart-fff6bdaf-dfb4-4844-bab5-f4a8deea94a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18311
28502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.1831128502
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.3467604634
Short name T243
Test name
Test status
Simulation time 179627913550 ps
CPU time 2564.74 seconds
Started Apr 25 01:55:51 PM PDT 24
Finished Apr 25 02:38:37 PM PDT 24
Peak memory 281516 kb
Host smart-46e9df5c-599b-460a-bc38-047679b69ac7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467604634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.3467604634
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.147006140
Short name T433
Test name
Test status
Simulation time 18178224719 ps
CPU time 858.43 seconds
Started Apr 25 01:56:01 PM PDT 24
Finished Apr 25 02:10:20 PM PDT 24
Peak memory 273268 kb
Host smart-1d6593a3-7ef9-432f-9f99-a45f8127901a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147006140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.147006140
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.2094536042
Short name T425
Test name
Test status
Simulation time 469035151 ps
CPU time 42.76 seconds
Started Apr 25 01:56:00 PM PDT 24
Finished Apr 25 01:56:43 PM PDT 24
Peak memory 255952 kb
Host smart-2da81f3c-c513-4f63-bc83-0d7ae04c438e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20945
36042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.2094536042
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.3794299272
Short name T396
Test name
Test status
Simulation time 352467874 ps
CPU time 31.1 seconds
Started Apr 25 01:55:59 PM PDT 24
Finished Apr 25 01:56:30 PM PDT 24
Peak memory 255908 kb
Host smart-1f3338dc-d599-47d7-bc22-2a6ef7eea8d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37942
99272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.3794299272
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.1339996303
Short name T306
Test name
Test status
Simulation time 63932885050 ps
CPU time 3503.39 seconds
Started Apr 25 01:55:58 PM PDT 24
Finished Apr 25 02:54:23 PM PDT 24
Peak memory 289064 kb
Host smart-3ff8c68c-7df4-47b3-beb7-8261d2128744
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339996303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.1339996303
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.1562042463
Short name T618
Test name
Test status
Simulation time 30060966184 ps
CPU time 651.13 seconds
Started Apr 25 01:56:04 PM PDT 24
Finished Apr 25 02:06:56 PM PDT 24
Peak memory 272716 kb
Host smart-613899d4-bc1d-47cc-abed-e94ad96d6e2d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562042463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.1562042463
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.2713542221
Short name T16
Test name
Test status
Simulation time 13221856595 ps
CPU time 525.79 seconds
Started Apr 25 01:55:58 PM PDT 24
Finished Apr 25 02:04:45 PM PDT 24
Peak memory 247964 kb
Host smart-dee039a2-a516-470c-b9ea-fe248c955512
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713542221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.2713542221
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.2810587531
Short name T276
Test name
Test status
Simulation time 115136197 ps
CPU time 10.76 seconds
Started Apr 25 01:55:51 PM PDT 24
Finished Apr 25 01:56:03 PM PDT 24
Peak memory 248688 kb
Host smart-05cfc618-8083-4592-8e13-eff1ce18b7ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28105
87531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.2810587531
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.3404292584
Short name T344
Test name
Test status
Simulation time 97038138 ps
CPU time 14.66 seconds
Started Apr 25 01:55:58 PM PDT 24
Finished Apr 25 01:56:14 PM PDT 24
Peak memory 248860 kb
Host smart-dc30ed49-fa62-4266-8abe-6265f369d887
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34042
92584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.3404292584
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.3553242948
Short name T623
Test name
Test status
Simulation time 278131053 ps
CPU time 22.73 seconds
Started Apr 25 01:56:04 PM PDT 24
Finished Apr 25 01:56:27 PM PDT 24
Peak memory 255836 kb
Host smart-a2ee618b-5848-425e-8bbc-8cec8bb2e76c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35532
42948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.3553242948
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.377409315
Short name T210
Test name
Test status
Simulation time 44235796 ps
CPU time 2.14 seconds
Started Apr 25 01:52:54 PM PDT 24
Finished Apr 25 01:52:57 PM PDT 24
Peak memory 248880 kb
Host smart-a1785bdf-669c-48a3-a1f8-ba0958d0cf11
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=377409315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.377409315
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.4287519417
Short name T577
Test name
Test status
Simulation time 21442172652 ps
CPU time 1346.93 seconds
Started Apr 25 01:52:45 PM PDT 24
Finished Apr 25 02:15:12 PM PDT 24
Peak memory 267212 kb
Host smart-3a931ab2-a4f7-44f7-94f8-02d16b4ef23f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287519417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.4287519417
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.1176061648
Short name T530
Test name
Test status
Simulation time 2470289138 ps
CPU time 43.38 seconds
Started Apr 25 01:52:59 PM PDT 24
Finished Apr 25 01:53:43 PM PDT 24
Peak memory 248768 kb
Host smart-b4c778e4-2cb3-4821-b369-c32414f97bc1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1176061648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.1176061648
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.4281628897
Short name T596
Test name
Test status
Simulation time 16449612533 ps
CPU time 92.62 seconds
Started Apr 25 01:52:44 PM PDT 24
Finished Apr 25 01:54:18 PM PDT 24
Peak memory 249848 kb
Host smart-1689de38-b8ba-4bac-ab2c-db446559ecbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42816
28897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.4281628897
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.3827173249
Short name T533
Test name
Test status
Simulation time 350165450 ps
CPU time 31.59 seconds
Started Apr 25 01:52:50 PM PDT 24
Finished Apr 25 01:53:23 PM PDT 24
Peak memory 256672 kb
Host smart-ed4f6d5f-a2cb-4a2c-888f-7ec5de998dfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38271
73249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.3827173249
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.482330820
Short name T297
Test name
Test status
Simulation time 33934399530 ps
CPU time 811.85 seconds
Started Apr 25 01:52:51 PM PDT 24
Finished Apr 25 02:06:24 PM PDT 24
Peak memory 269300 kb
Host smart-2ce7b3fa-c67d-41fc-9ed8-bce3f73c8e3b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482330820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.482330820
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.2867792487
Short name T399
Test name
Test status
Simulation time 25885138528 ps
CPU time 1452.67 seconds
Started Apr 25 01:52:53 PM PDT 24
Finished Apr 25 02:17:06 PM PDT 24
Peak memory 266176 kb
Host smart-160b8075-789b-4a71-825b-da8fb441f3dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867792487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.2867792487
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.3945982306
Short name T660
Test name
Test status
Simulation time 15076631895 ps
CPU time 175.85 seconds
Started Apr 25 01:52:46 PM PDT 24
Finished Apr 25 01:55:43 PM PDT 24
Peak memory 247000 kb
Host smart-d0e07b90-d2dc-40ef-8598-09082653b84e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945982306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.3945982306
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.3539729803
Short name T430
Test name
Test status
Simulation time 283366780 ps
CPU time 21.94 seconds
Started Apr 25 01:52:47 PM PDT 24
Finished Apr 25 01:53:09 PM PDT 24
Peak memory 248700 kb
Host smart-34f27851-67e9-4beb-a8d4-8be7ff6f4d1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35397
29803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.3539729803
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.3147699596
Short name T666
Test name
Test status
Simulation time 2345815640 ps
CPU time 32.65 seconds
Started Apr 25 01:52:50 PM PDT 24
Finished Apr 25 01:53:23 PM PDT 24
Peak memory 255516 kb
Host smart-c0c48341-cb32-430f-8ccf-82fd6a00d448
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31476
99596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.3147699596
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.3722464515
Short name T622
Test name
Test status
Simulation time 500835985 ps
CPU time 30.03 seconds
Started Apr 25 01:52:45 PM PDT 24
Finished Apr 25 01:53:15 PM PDT 24
Peak memory 255748 kb
Host smart-2f20c21a-7625-45b3-bc63-e5b01d08cfce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37224
64515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.3722464515
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.3474071810
Short name T626
Test name
Test status
Simulation time 1106811682 ps
CPU time 59.23 seconds
Started Apr 25 01:52:45 PM PDT 24
Finished Apr 25 01:53:44 PM PDT 24
Peak memory 255980 kb
Host smart-80eaf568-dbc4-45ea-a5b1-6ba6cef2f7b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34740
71810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.3474071810
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.1106450377
Short name T103
Test name
Test status
Simulation time 32477248345 ps
CPU time 1802.3 seconds
Started Apr 25 01:52:50 PM PDT 24
Finished Apr 25 02:22:53 PM PDT 24
Peak memory 287460 kb
Host smart-ab1117b4-3e31-4888-9ed9-e5761a946919
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106450377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.1106450377
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.459397973
Short name T266
Test name
Test status
Simulation time 7877678300 ps
CPU time 103.54 seconds
Started Apr 25 01:56:04 PM PDT 24
Finished Apr 25 01:57:48 PM PDT 24
Peak memory 256808 kb
Host smart-6d5b00af-8104-4c7d-b987-8813a685ad3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45939
7973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.459397973
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.752305137
Short name T249
Test name
Test status
Simulation time 14825678780 ps
CPU time 57.02 seconds
Started Apr 25 01:56:08 PM PDT 24
Finished Apr 25 01:57:06 PM PDT 24
Peak memory 248720 kb
Host smart-0bf001aa-4e7a-4b8f-8205-e8c87a063442
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75230
5137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.752305137
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.1704907399
Short name T431
Test name
Test status
Simulation time 67732848162 ps
CPU time 2064.4 seconds
Started Apr 25 01:56:10 PM PDT 24
Finished Apr 25 02:30:36 PM PDT 24
Peak memory 288604 kb
Host smart-b5ce4924-9154-43fa-b133-800977a0e947
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704907399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.1704907399
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.1317103273
Short name T535
Test name
Test status
Simulation time 11750711981 ps
CPU time 461.85 seconds
Started Apr 25 01:56:15 PM PDT 24
Finished Apr 25 02:03:58 PM PDT 24
Peak memory 247828 kb
Host smart-51d44b6b-ab83-4af8-ad3c-352c93769cfd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317103273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.1317103273
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.4145005174
Short name T594
Test name
Test status
Simulation time 512922770 ps
CPU time 14.65 seconds
Started Apr 25 01:56:05 PM PDT 24
Finished Apr 25 01:56:20 PM PDT 24
Peak memory 255976 kb
Host smart-d84f1e02-0518-414e-9e20-8166e894ee9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41450
05174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.4145005174
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.1844672398
Short name T48
Test name
Test status
Simulation time 5902960703 ps
CPU time 26.68 seconds
Started Apr 25 01:56:04 PM PDT 24
Finished Apr 25 01:56:31 PM PDT 24
Peak memory 256020 kb
Host smart-a9bfe9d8-4f14-4863-8b77-bdf8c7061f68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18446
72398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.1844672398
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.4192805551
Short name T568
Test name
Test status
Simulation time 1977527709 ps
CPU time 62.89 seconds
Started Apr 25 01:56:06 PM PDT 24
Finished Apr 25 01:57:10 PM PDT 24
Peak memory 256776 kb
Host smart-282114b0-dc8a-4f61-a13b-08fc03daf836
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41928
05551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.4192805551
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.517262096
Short name T656
Test name
Test status
Simulation time 190281737 ps
CPU time 16.23 seconds
Started Apr 25 01:56:05 PM PDT 24
Finished Apr 25 01:56:22 PM PDT 24
Peak memory 248700 kb
Host smart-bf023d05-b263-4f40-8e73-a8efec3ece14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51726
2096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.517262096
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.1505826921
Short name T120
Test name
Test status
Simulation time 117985532811 ps
CPU time 3450.47 seconds
Started Apr 25 01:56:09 PM PDT 24
Finished Apr 25 02:53:40 PM PDT 24
Peak memory 289704 kb
Host smart-43ba4632-b4f9-4a43-88eb-d6a1d09d8495
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505826921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.1505826921
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.3222661109
Short name T353
Test name
Test status
Simulation time 143482473677 ps
CPU time 1160.92 seconds
Started Apr 25 01:56:17 PM PDT 24
Finished Apr 25 02:15:39 PM PDT 24
Peak memory 286720 kb
Host smart-6bcaa188-d57d-4607-a8f7-da634e92d821
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222661109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.3222661109
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.2919223965
Short name T527
Test name
Test status
Simulation time 4390788794 ps
CPU time 250.43 seconds
Started Apr 25 01:56:10 PM PDT 24
Finished Apr 25 02:00:21 PM PDT 24
Peak memory 256928 kb
Host smart-09c3c75a-2c19-4b8b-8778-110b46fd7b5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29192
23965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.2919223965
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.1459741644
Short name T366
Test name
Test status
Simulation time 2960906365 ps
CPU time 46.27 seconds
Started Apr 25 01:56:12 PM PDT 24
Finished Apr 25 01:56:59 PM PDT 24
Peak memory 256076 kb
Host smart-5fd82f58-cf72-4c41-a615-2eb9b75f179e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14597
41644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.1459741644
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.2018180837
Short name T37
Test name
Test status
Simulation time 27968118334 ps
CPU time 1545.68 seconds
Started Apr 25 01:56:15 PM PDT 24
Finished Apr 25 02:22:01 PM PDT 24
Peak memory 265204 kb
Host smart-71a318d2-99d7-435c-b3dc-61bc14afbfa0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018180837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.2018180837
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.652899763
Short name T99
Test name
Test status
Simulation time 35917563963 ps
CPU time 1182.6 seconds
Started Apr 25 01:56:14 PM PDT 24
Finished Apr 25 02:15:58 PM PDT 24
Peak memory 272596 kb
Host smart-3e7f4466-ac73-4ffa-ad98-1135a87666f9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652899763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.652899763
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.169841820
Short name T603
Test name
Test status
Simulation time 40766237161 ps
CPU time 413.1 seconds
Started Apr 25 01:56:20 PM PDT 24
Finished Apr 25 02:03:14 PM PDT 24
Peak memory 247024 kb
Host smart-962bc518-4f81-4399-90d6-68f5eba9ecfd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169841820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.169841820
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.1851313760
Short name T581
Test name
Test status
Simulation time 532013385 ps
CPU time 16.04 seconds
Started Apr 25 01:56:09 PM PDT 24
Finished Apr 25 01:56:26 PM PDT 24
Peak memory 248680 kb
Host smart-bd42a52a-1f5c-4b8d-9528-30da9c2911c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18513
13760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.1851313760
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.475524066
Short name T356
Test name
Test status
Simulation time 858195191 ps
CPU time 49.33 seconds
Started Apr 25 01:56:10 PM PDT 24
Finished Apr 25 01:57:00 PM PDT 24
Peak memory 248688 kb
Host smart-29000ef2-1f53-4250-a970-43bd522006b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47552
4066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.475524066
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.64563065
Short name T497
Test name
Test status
Simulation time 56590874 ps
CPU time 4.7 seconds
Started Apr 25 01:56:20 PM PDT 24
Finished Apr 25 01:56:25 PM PDT 24
Peak memory 239056 kb
Host smart-25a5f5c0-2c5f-4174-9281-16bf813d33ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64563
065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.64563065
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.4056458526
Short name T573
Test name
Test status
Simulation time 916111391 ps
CPU time 16.32 seconds
Started Apr 25 01:56:12 PM PDT 24
Finished Apr 25 01:56:29 PM PDT 24
Peak memory 248696 kb
Host smart-9f22ea32-0d0b-493b-aea4-48398f246b65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40564
58526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.4056458526
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.2602466880
Short name T529
Test name
Test status
Simulation time 22815786730 ps
CPU time 1932.66 seconds
Started Apr 25 01:56:16 PM PDT 24
Finished Apr 25 02:28:30 PM PDT 24
Peak memory 297744 kb
Host smart-c01634e0-46e8-4e43-bcef-ee6185d6b410
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602466880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.2602466880
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.3778493449
Short name T418
Test name
Test status
Simulation time 175951196063 ps
CPU time 2757.49 seconds
Started Apr 25 01:56:25 PM PDT 24
Finished Apr 25 02:42:23 PM PDT 24
Peak memory 281548 kb
Host smart-39d90eea-ce91-4ef4-a327-98b27d510acf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778493449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.3778493449
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.328354060
Short name T367
Test name
Test status
Simulation time 1036321887 ps
CPU time 77.61 seconds
Started Apr 25 01:56:22 PM PDT 24
Finished Apr 25 01:57:40 PM PDT 24
Peak memory 250080 kb
Host smart-3ec8e32f-8724-437f-aec1-e24b590134cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32835
4060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.328354060
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.329049726
Short name T462
Test name
Test status
Simulation time 355241868 ps
CPU time 31.89 seconds
Started Apr 25 01:56:22 PM PDT 24
Finished Apr 25 01:56:54 PM PDT 24
Peak memory 255948 kb
Host smart-c5f15123-3a98-4964-a46c-0f65ac7c37ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32904
9726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.329049726
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.4122121586
Short name T546
Test name
Test status
Simulation time 35621924142 ps
CPU time 1040.01 seconds
Started Apr 25 01:56:23 PM PDT 24
Finished Apr 25 02:13:43 PM PDT 24
Peak memory 273344 kb
Host smart-4fcea91f-94a1-418c-8e6c-2c343155a74e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122121586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.4122121586
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.2211383434
Short name T554
Test name
Test status
Simulation time 55409162586 ps
CPU time 3128.13 seconds
Started Apr 25 01:56:22 PM PDT 24
Finished Apr 25 02:48:31 PM PDT 24
Peak memory 289116 kb
Host smart-5ac9614b-7d99-4158-9eed-79331c44b7a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211383434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.2211383434
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.3442417752
Short name T643
Test name
Test status
Simulation time 13022645258 ps
CPU time 505.26 seconds
Started Apr 25 01:56:24 PM PDT 24
Finished Apr 25 02:04:50 PM PDT 24
Peak memory 247992 kb
Host smart-638cd59f-c591-4d2c-83ae-8443b4236596
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442417752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.3442417752
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.3360948452
Short name T570
Test name
Test status
Simulation time 2153718602 ps
CPU time 21.57 seconds
Started Apr 25 01:56:18 PM PDT 24
Finished Apr 25 01:56:40 PM PDT 24
Peak memory 254872 kb
Host smart-fc68f74d-fa6f-4f56-851e-f3ec6358bf68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33609
48452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.3360948452
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.1566146577
Short name T693
Test name
Test status
Simulation time 2300228804 ps
CPU time 36.37 seconds
Started Apr 25 01:56:21 PM PDT 24
Finished Apr 25 01:56:57 PM PDT 24
Peak memory 248748 kb
Host smart-3d561f52-b655-4033-bff4-19e56baf6929
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15661
46577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.1566146577
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.552371259
Short name T264
Test name
Test status
Simulation time 4044177901 ps
CPU time 58.56 seconds
Started Apr 25 01:56:22 PM PDT 24
Finished Apr 25 01:57:21 PM PDT 24
Peak memory 256240 kb
Host smart-be170a0f-7705-4493-af39-cf254d78a6da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55237
1259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.552371259
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.1651515059
Short name T370
Test name
Test status
Simulation time 3380305915 ps
CPU time 51.77 seconds
Started Apr 25 01:56:21 PM PDT 24
Finished Apr 25 01:57:13 PM PDT 24
Peak memory 248760 kb
Host smart-1ca1670f-ef46-430c-a41d-74535e4983af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16515
15059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.1651515059
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.2489415436
Short name T105
Test name
Test status
Simulation time 19315087422 ps
CPU time 1170.54 seconds
Started Apr 25 01:56:24 PM PDT 24
Finished Apr 25 02:15:55 PM PDT 24
Peak memory 273404 kb
Host smart-014dd570-3944-429f-ac1b-1a5515e72e86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489415436 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.2489415436
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.1000756935
Short name T96
Test name
Test status
Simulation time 10502779388 ps
CPU time 1015.13 seconds
Started Apr 25 01:56:27 PM PDT 24
Finished Apr 25 02:13:23 PM PDT 24
Peak memory 273392 kb
Host smart-eae99810-c514-4646-a6dd-9c2da79e0c0d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000756935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.1000756935
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.853032364
Short name T386
Test name
Test status
Simulation time 820523401 ps
CPU time 46.35 seconds
Started Apr 25 01:56:38 PM PDT 24
Finished Apr 25 01:57:25 PM PDT 24
Peak memory 249076 kb
Host smart-bc4422a0-f686-4227-88f5-895e94b0a994
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85303
2364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.853032364
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.898140805
Short name T87
Test name
Test status
Simulation time 425953273 ps
CPU time 15.76 seconds
Started Apr 25 01:56:29 PM PDT 24
Finished Apr 25 01:56:46 PM PDT 24
Peak memory 255776 kb
Host smart-e0c6aeb8-ceaf-43d1-b56e-c54116e29e23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89814
0805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.898140805
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.681208695
Short name T559
Test name
Test status
Simulation time 63418473357 ps
CPU time 845.39 seconds
Started Apr 25 01:56:29 PM PDT 24
Finished Apr 25 02:10:35 PM PDT 24
Peak memory 270744 kb
Host smart-48a80490-98f9-4cfc-a975-7fc0f97eefef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681208695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.681208695
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.1790461437
Short name T646
Test name
Test status
Simulation time 60570495214 ps
CPU time 1764.46 seconds
Started Apr 25 01:56:28 PM PDT 24
Finished Apr 25 02:25:53 PM PDT 24
Peak memory 289308 kb
Host smart-e857f4e3-98c7-45eb-ac54-3530bbfa92c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790461437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.1790461437
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.851184996
Short name T212
Test name
Test status
Simulation time 8931177349 ps
CPU time 327.89 seconds
Started Apr 25 01:56:29 PM PDT 24
Finished Apr 25 02:01:57 PM PDT 24
Peak memory 247012 kb
Host smart-f873c839-d4fc-4fc8-a163-5aaf7c7546b7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851184996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.851184996
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.2034309403
Short name T474
Test name
Test status
Simulation time 2089073100 ps
CPU time 62.2 seconds
Started Apr 25 01:56:23 PM PDT 24
Finished Apr 25 01:57:25 PM PDT 24
Peak memory 248724 kb
Host smart-f4de0394-7698-4a1c-b43f-9bc2b4543e71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20343
09403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.2034309403
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.2041584989
Short name T506
Test name
Test status
Simulation time 150793758 ps
CPU time 9.89 seconds
Started Apr 25 01:56:24 PM PDT 24
Finished Apr 25 01:56:34 PM PDT 24
Peak memory 248540 kb
Host smart-b6359b97-3a25-458b-9a85-2d0ec73ee301
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20415
84989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.2041584989
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.23006939
Short name T608
Test name
Test status
Simulation time 257549407 ps
CPU time 15.79 seconds
Started Apr 25 01:56:24 PM PDT 24
Finished Apr 25 01:56:40 PM PDT 24
Peak memory 248688 kb
Host smart-2871a3d0-f513-4e02-ab50-87e7b4e6a4e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23006
939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.23006939
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.482290920
Short name T588
Test name
Test status
Simulation time 17792342514 ps
CPU time 189.55 seconds
Started Apr 25 01:56:28 PM PDT 24
Finished Apr 25 01:59:38 PM PDT 24
Peak memory 256948 kb
Host smart-3bf80985-32b8-4de6-ac55-f0b5e189c0cb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482290920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_han
dler_stress_all.482290920
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.1775718043
Short name T28
Test name
Test status
Simulation time 42977033476 ps
CPU time 1823.92 seconds
Started Apr 25 01:56:27 PM PDT 24
Finished Apr 25 02:26:52 PM PDT 24
Peak memory 298228 kb
Host smart-92a07d5a-ac71-4445-8bd7-0bc905bdb0cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775718043 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.1775718043
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.3019736992
Short name T271
Test name
Test status
Simulation time 3257015767 ps
CPU time 115.91 seconds
Started Apr 25 01:56:35 PM PDT 24
Finished Apr 25 01:58:31 PM PDT 24
Peak memory 256968 kb
Host smart-7183cfd2-9715-4bfe-b5ff-0910e1b7f2ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30197
36992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.3019736992
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.1406069949
Short name T398
Test name
Test status
Simulation time 290492812 ps
CPU time 26.38 seconds
Started Apr 25 01:56:36 PM PDT 24
Finished Apr 25 01:57:03 PM PDT 24
Peak memory 255884 kb
Host smart-ec418cf7-f502-46eb-a798-cdc286eaf071
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14060
69949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.1406069949
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.133231504
Short name T318
Test name
Test status
Simulation time 73514649788 ps
CPU time 2426.83 seconds
Started Apr 25 01:56:40 PM PDT 24
Finished Apr 25 02:37:08 PM PDT 24
Peak memory 284544 kb
Host smart-e4a9e645-fbbb-4e06-bcbd-9a0ac2f1424c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133231504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.133231504
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.2300844796
Short name T115
Test name
Test status
Simulation time 305288930020 ps
CPU time 2204.37 seconds
Started Apr 25 01:56:40 PM PDT 24
Finished Apr 25 02:33:25 PM PDT 24
Peak memory 286072 kb
Host smart-6a5b4e24-d13d-414d-bbed-8f364f621a54
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300844796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.2300844796
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.1952858306
Short name T464
Test name
Test status
Simulation time 64375105632 ps
CPU time 286.8 seconds
Started Apr 25 01:56:40 PM PDT 24
Finished Apr 25 02:01:28 PM PDT 24
Peak memory 248204 kb
Host smart-c8acc727-7b3d-4b9f-85bc-85450500099f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952858306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.1952858306
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.4284047089
Short name T590
Test name
Test status
Simulation time 799358184 ps
CPU time 7.56 seconds
Started Apr 25 01:56:36 PM PDT 24
Finished Apr 25 01:56:44 PM PDT 24
Peak memory 248720 kb
Host smart-4d559148-edd4-4f88-9b23-4006148a4e7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42840
47089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.4284047089
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.284100337
Short name T619
Test name
Test status
Simulation time 2213296570 ps
CPU time 58.13 seconds
Started Apr 25 01:56:36 PM PDT 24
Finished Apr 25 01:57:34 PM PDT 24
Peak memory 255848 kb
Host smart-30d64979-f4fb-4fac-bcdb-395d044d5af6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28410
0337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.284100337
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.3385335394
Short name T377
Test name
Test status
Simulation time 779677276 ps
CPU time 12.23 seconds
Started Apr 25 01:56:35 PM PDT 24
Finished Apr 25 01:56:47 PM PDT 24
Peak memory 248932 kb
Host smart-9bebc2d4-6c04-4e4e-8afb-e28db50dcab7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33853
35394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.3385335394
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.1305491389
Short name T75
Test name
Test status
Simulation time 476499289 ps
CPU time 48.73 seconds
Started Apr 25 01:56:29 PM PDT 24
Finished Apr 25 01:57:18 PM PDT 24
Peak memory 248720 kb
Host smart-8163c27e-ab9d-4e19-b0ee-6931787d22bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13054
91389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.1305491389
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.1064892531
Short name T235
Test name
Test status
Simulation time 23067042016 ps
CPU time 2226.34 seconds
Started Apr 25 01:56:40 PM PDT 24
Finished Apr 25 02:33:47 PM PDT 24
Peak memory 305120 kb
Host smart-06292ba8-8aaf-4a60-9cc0-fa03f911ef17
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064892531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.1064892531
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.233763976
Short name T479
Test name
Test status
Simulation time 109892172368 ps
CPU time 1169.34 seconds
Started Apr 25 01:56:48 PM PDT 24
Finished Apr 25 02:16:18 PM PDT 24
Peak memory 273380 kb
Host smart-be7b974f-3ade-4be4-8c54-def5d968fd83
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233763976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.233763976
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.1081663419
Short name T671
Test name
Test status
Simulation time 323333441 ps
CPU time 6.06 seconds
Started Apr 25 01:56:47 PM PDT 24
Finished Apr 25 01:56:54 PM PDT 24
Peak memory 240552 kb
Host smart-36b13a55-0cec-485b-b537-74b4c4bc1be1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10816
63419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.1081663419
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.3848672317
Short name T397
Test name
Test status
Simulation time 571830016 ps
CPU time 33.19 seconds
Started Apr 25 01:56:47 PM PDT 24
Finished Apr 25 01:57:20 PM PDT 24
Peak memory 255876 kb
Host smart-294a3f19-a40e-49c3-93ed-0415de7cd072
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38486
72317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.3848672317
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.2914825945
Short name T494
Test name
Test status
Simulation time 69315100208 ps
CPU time 1944.06 seconds
Started Apr 25 01:56:55 PM PDT 24
Finished Apr 25 02:29:20 PM PDT 24
Peak memory 283892 kb
Host smart-d8be2a6b-c56d-4fec-8fb0-e4149d660da6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914825945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.2914825945
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.3969972294
Short name T698
Test name
Test status
Simulation time 57563105579 ps
CPU time 1863.19 seconds
Started Apr 25 01:56:53 PM PDT 24
Finished Apr 25 02:27:57 PM PDT 24
Peak memory 281596 kb
Host smart-0b689aec-4954-40a5-853c-5a82fa5e55ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969972294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.3969972294
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.2382008316
Short name T450
Test name
Test status
Simulation time 29013654672 ps
CPU time 325.08 seconds
Started Apr 25 01:56:49 PM PDT 24
Finished Apr 25 02:02:14 PM PDT 24
Peak memory 247816 kb
Host smart-6b209805-0466-4b5a-a6d2-5bc40206373f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382008316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.2382008316
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.1026979741
Short name T486
Test name
Test status
Simulation time 3268044305 ps
CPU time 43.86 seconds
Started Apr 25 01:56:41 PM PDT 24
Finished Apr 25 01:57:25 PM PDT 24
Peak memory 248784 kb
Host smart-97fca8f9-c8dc-47b5-b30a-d33c917397ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10269
79741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.1026979741
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.299737332
Short name T80
Test name
Test status
Simulation time 755373564 ps
CPU time 43.32 seconds
Started Apr 25 01:56:40 PM PDT 24
Finished Apr 25 01:57:24 PM PDT 24
Peak memory 255576 kb
Host smart-f0d7c55f-6760-418e-bfad-5e6e5bbae038
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29973
7332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.299737332
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.3964724938
Short name T100
Test name
Test status
Simulation time 211787095 ps
CPU time 22.02 seconds
Started Apr 25 01:56:47 PM PDT 24
Finished Apr 25 01:57:09 PM PDT 24
Peak memory 248632 kb
Host smart-9ab2815f-cdda-49a9-bab1-c65e48761b47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39647
24938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.3964724938
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.1782961251
Short name T334
Test name
Test status
Simulation time 715510201 ps
CPU time 45.57 seconds
Started Apr 25 01:56:40 PM PDT 24
Finished Apr 25 01:57:26 PM PDT 24
Peak memory 256076 kb
Host smart-79ec149c-0975-4153-8c78-4d0f529a270c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17829
61251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.1782961251
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.2221587152
Short name T400
Test name
Test status
Simulation time 1685764139 ps
CPU time 151.34 seconds
Started Apr 25 01:56:55 PM PDT 24
Finished Apr 25 01:59:26 PM PDT 24
Peak memory 256876 kb
Host smart-ecac5ee3-fb08-48c0-bc12-aa44fa6c4b73
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221587152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.2221587152
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.954740182
Short name T74
Test name
Test status
Simulation time 8516839059 ps
CPU time 958.24 seconds
Started Apr 25 01:56:58 PM PDT 24
Finished Apr 25 02:12:57 PM PDT 24
Peak memory 281600 kb
Host smart-ff07603f-17cd-4992-a0c3-b154e3d74b8b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954740182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.954740182
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.2629328409
Short name T514
Test name
Test status
Simulation time 14690990374 ps
CPU time 208.47 seconds
Started Apr 25 01:56:53 PM PDT 24
Finished Apr 25 02:00:22 PM PDT 24
Peak memory 250212 kb
Host smart-e2d40aef-e3b5-4847-a438-5e5da9989e8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26293
28409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.2629328409
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.376651169
Short name T412
Test name
Test status
Simulation time 23057441675 ps
CPU time 70.08 seconds
Started Apr 25 01:56:54 PM PDT 24
Finished Apr 25 01:58:05 PM PDT 24
Peak memory 248768 kb
Host smart-2ace9115-62b4-4ec4-beca-7bcae8de6720
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37665
1169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.376651169
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.3391910433
Short name T315
Test name
Test status
Simulation time 191572447024 ps
CPU time 2923.2 seconds
Started Apr 25 01:56:59 PM PDT 24
Finished Apr 25 02:45:43 PM PDT 24
Peak memory 289300 kb
Host smart-3aa9afd3-ff89-41f5-92e4-49986800b636
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391910433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.3391910433
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.3906603241
Short name T543
Test name
Test status
Simulation time 11942637870 ps
CPU time 1219.81 seconds
Started Apr 25 01:57:00 PM PDT 24
Finished Apr 25 02:17:20 PM PDT 24
Peak memory 289704 kb
Host smart-2541767c-3829-4062-9dc2-105352c9c8db
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906603241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.3906603241
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.3444925306
Short name T286
Test name
Test status
Simulation time 17462171249 ps
CPU time 343.62 seconds
Started Apr 25 01:57:00 PM PDT 24
Finished Apr 25 02:02:44 PM PDT 24
Peak memory 248140 kb
Host smart-66b6cd27-e1e7-47e6-87c6-557d326d2c57
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444925306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.3444925306
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.2381956922
Short name T385
Test name
Test status
Simulation time 1388778782 ps
CPU time 41.93 seconds
Started Apr 25 01:56:54 PM PDT 24
Finished Apr 25 01:57:36 PM PDT 24
Peak memory 248728 kb
Host smart-3312aa31-c8fd-4206-a440-fb4289797fc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23819
56922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.2381956922
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.3045462712
Short name T389
Test name
Test status
Simulation time 1358877427 ps
CPU time 11.24 seconds
Started Apr 25 01:56:55 PM PDT 24
Finished Apr 25 01:57:07 PM PDT 24
Peak memory 248872 kb
Host smart-71ec6f75-34a6-4aeb-a553-8b925465c676
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30454
62712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.3045462712
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.2451745584
Short name T434
Test name
Test status
Simulation time 166932122 ps
CPU time 9.84 seconds
Started Apr 25 01:56:59 PM PDT 24
Finished Apr 25 01:57:09 PM PDT 24
Peak memory 256840 kb
Host smart-c273c61c-80e2-4f21-89c5-a8241b80c74b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24517
45584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.2451745584
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.1749303313
Short name T452
Test name
Test status
Simulation time 191877065 ps
CPU time 21.87 seconds
Started Apr 25 01:56:53 PM PDT 24
Finished Apr 25 01:57:16 PM PDT 24
Peak memory 248720 kb
Host smart-0e25b062-4d72-4918-97f6-44d1c9a65737
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17493
03313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.1749303313
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.1595558323
Short name T455
Test name
Test status
Simulation time 2483556479 ps
CPU time 237.61 seconds
Started Apr 25 01:57:06 PM PDT 24
Finished Apr 25 02:01:04 PM PDT 24
Peak memory 256940 kb
Host smart-fdc2f17c-b263-48ff-a523-1f1f68ee8d11
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595558323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.1595558323
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.3914383104
Short name T21
Test name
Test status
Simulation time 118054070687 ps
CPU time 2337.68 seconds
Started Apr 25 01:57:04 PM PDT 24
Finished Apr 25 02:36:02 PM PDT 24
Peak memory 300448 kb
Host smart-9cb0d65e-cc28-418d-939b-556f8c6fb769
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914383104 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.3914383104
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.2225990856
Short name T657
Test name
Test status
Simulation time 18911880224 ps
CPU time 1561 seconds
Started Apr 25 01:57:06 PM PDT 24
Finished Apr 25 02:23:08 PM PDT 24
Peak memory 281524 kb
Host smart-094c584d-4224-42df-8ff8-71f1ad5c2765
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225990856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.2225990856
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.1810538118
Short name T49
Test name
Test status
Simulation time 3136544254 ps
CPU time 71.35 seconds
Started Apr 25 01:57:05 PM PDT 24
Finished Apr 25 01:58:16 PM PDT 24
Peak memory 249124 kb
Host smart-2e6bf483-4867-413d-a8ee-fad476c2ac59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18105
38118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.1810538118
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.3300085916
Short name T531
Test name
Test status
Simulation time 2420894433 ps
CPU time 35.07 seconds
Started Apr 25 01:57:06 PM PDT 24
Finished Apr 25 01:57:41 PM PDT 24
Peak memory 256028 kb
Host smart-c8151ca7-4c76-474f-b141-f0466bea775a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33000
85916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.3300085916
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.1074596682
Short name T549
Test name
Test status
Simulation time 43436318710 ps
CPU time 890.13 seconds
Started Apr 25 01:57:12 PM PDT 24
Finished Apr 25 02:12:03 PM PDT 24
Peak memory 273172 kb
Host smart-fe2b68ba-9cd9-45ce-9064-90feb1d28636
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074596682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.1074596682
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.3103549223
Short name T224
Test name
Test status
Simulation time 127905560646 ps
CPU time 1244.6 seconds
Started Apr 25 01:57:17 PM PDT 24
Finished Apr 25 02:18:02 PM PDT 24
Peak memory 273352 kb
Host smart-4827b80f-285f-459d-b873-aafd689536a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103549223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.3103549223
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.3749523419
Short name T299
Test name
Test status
Simulation time 32202813079 ps
CPU time 237.66 seconds
Started Apr 25 01:57:12 PM PDT 24
Finished Apr 25 02:01:11 PM PDT 24
Peak memory 248280 kb
Host smart-b0d84c38-4515-47d3-8b47-3f16986e4535
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749523419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.3749523419
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.2993553392
Short name T475
Test name
Test status
Simulation time 4020883499 ps
CPU time 57.19 seconds
Started Apr 25 01:57:06 PM PDT 24
Finished Apr 25 01:58:04 PM PDT 24
Peak memory 256012 kb
Host smart-45b8c79b-c008-4b9e-bfb0-b84fbdcb4d66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29935
53392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.2993553392
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.3960166264
Short name T247
Test name
Test status
Simulation time 2824463916 ps
CPU time 47.81 seconds
Started Apr 25 01:57:07 PM PDT 24
Finished Apr 25 01:57:56 PM PDT 24
Peak memory 248732 kb
Host smart-bdf5e99c-3787-4a6f-a5cb-40d11505cda9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39601
66264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.3960166264
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.3923107030
Short name T333
Test name
Test status
Simulation time 139610126 ps
CPU time 3.83 seconds
Started Apr 25 01:57:06 PM PDT 24
Finished Apr 25 01:57:11 PM PDT 24
Peak memory 240468 kb
Host smart-0fdb3193-9ca8-4b5b-9cf3-384cbd133c0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39231
07030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.3923107030
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.37815982
Short name T13
Test name
Test status
Simulation time 23200101737 ps
CPU time 1361.17 seconds
Started Apr 25 01:57:19 PM PDT 24
Finished Apr 25 02:20:01 PM PDT 24
Peak memory 269464 kb
Host smart-2bd9d666-071c-41b8-88a7-c593a97a4a3b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37815982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_hand
ler_stress_all.37815982
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.2225834856
Short name T97
Test name
Test status
Simulation time 68550231806 ps
CPU time 1245.87 seconds
Started Apr 25 01:57:23 PM PDT 24
Finished Apr 25 02:18:10 PM PDT 24
Peak memory 289348 kb
Host smart-03db75b3-25ab-4dac-987f-9a9ecff79c4f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225834856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.2225834856
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.2218004413
Short name T487
Test name
Test status
Simulation time 8691669672 ps
CPU time 134.25 seconds
Started Apr 25 01:57:24 PM PDT 24
Finished Apr 25 01:59:39 PM PDT 24
Peak memory 248996 kb
Host smart-bd9d6c08-c0dc-48b1-b89f-f111e31345f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22180
04413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.2218004413
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.2246777522
Short name T349
Test name
Test status
Simulation time 621078831 ps
CPU time 33.2 seconds
Started Apr 25 01:57:24 PM PDT 24
Finished Apr 25 01:57:58 PM PDT 24
Peak memory 256904 kb
Host smart-ba620b0c-b972-4bbb-bf30-743b6de398a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22467
77522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.2246777522
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.3511477687
Short name T311
Test name
Test status
Simulation time 32976586662 ps
CPU time 1718.32 seconds
Started Apr 25 01:57:31 PM PDT 24
Finished Apr 25 02:26:10 PM PDT 24
Peak memory 272500 kb
Host smart-2c3de18c-5465-4a10-aeb4-645e4b322b8d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511477687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.3511477687
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.2011046816
Short name T339
Test name
Test status
Simulation time 20360281755 ps
CPU time 1134.26 seconds
Started Apr 25 01:57:29 PM PDT 24
Finished Apr 25 02:16:24 PM PDT 24
Peak memory 265148 kb
Host smart-93e60ad7-121f-480a-a6ac-127a646099f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011046816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.2011046816
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.2591741034
Short name T33
Test name
Test status
Simulation time 7392612337 ps
CPU time 130.79 seconds
Started Apr 25 01:57:25 PM PDT 24
Finished Apr 25 01:59:36 PM PDT 24
Peak memory 247804 kb
Host smart-54ded6f9-78bc-4bc6-aca6-4ce4360c0ce4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591741034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.2591741034
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.4167537183
Short name T459
Test name
Test status
Simulation time 42969450 ps
CPU time 4.32 seconds
Started Apr 25 01:57:17 PM PDT 24
Finished Apr 25 01:57:22 PM PDT 24
Peak memory 248708 kb
Host smart-15c6aa86-bc98-47a4-82ad-470652d48a65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41675
37183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.4167537183
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.3638501802
Short name T106
Test name
Test status
Simulation time 718207446 ps
CPU time 43.24 seconds
Started Apr 25 01:57:19 PM PDT 24
Finished Apr 25 01:58:03 PM PDT 24
Peak memory 248708 kb
Host smart-32786813-0d52-4e4a-8855-55ad4f5ef15f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36385
01802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.3638501802
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.1285617670
Short name T565
Test name
Test status
Simulation time 393176224 ps
CPU time 23.66 seconds
Started Apr 25 01:57:23 PM PDT 24
Finished Apr 25 01:57:48 PM PDT 24
Peak memory 248780 kb
Host smart-a7a44c2c-18c3-40d4-b199-3696fc3781b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12856
17670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.1285617670
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.3654088963
Short name T613
Test name
Test status
Simulation time 1026556996 ps
CPU time 25.03 seconds
Started Apr 25 01:57:19 PM PDT 24
Finished Apr 25 01:57:45 PM PDT 24
Peak memory 248684 kb
Host smart-d2c3149d-174b-4776-9519-583b785bc66d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36540
88963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.3654088963
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.1105561218
Short name T239
Test name
Test status
Simulation time 7871016802 ps
CPU time 418.49 seconds
Started Apr 25 01:57:29 PM PDT 24
Finished Apr 25 02:04:28 PM PDT 24
Peak memory 256940 kb
Host smart-41dcf209-522d-41d6-855b-f03c78b51415
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105561218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.1105561218
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.826896404
Short name T566
Test name
Test status
Simulation time 27402155403 ps
CPU time 1381.48 seconds
Started Apr 25 01:57:36 PM PDT 24
Finished Apr 25 02:20:39 PM PDT 24
Peak memory 265152 kb
Host smart-d199d5fc-d8d0-425c-b63d-299986da71a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826896404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.826896404
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.1778515576
Short name T424
Test name
Test status
Simulation time 9612594919 ps
CPU time 140.67 seconds
Started Apr 25 01:57:37 PM PDT 24
Finished Apr 25 01:59:58 PM PDT 24
Peak memory 256928 kb
Host smart-2987f2a2-d22c-4bdb-b2e0-2f3ee5683fc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17785
15576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.1778515576
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.525935577
Short name T215
Test name
Test status
Simulation time 386693124 ps
CPU time 11.16 seconds
Started Apr 25 01:57:36 PM PDT 24
Finished Apr 25 01:57:48 PM PDT 24
Peak memory 248680 kb
Host smart-d270cc96-3a98-45e1-a367-f4736c1b643e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52593
5577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.525935577
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.476409971
Short name T307
Test name
Test status
Simulation time 67009969200 ps
CPU time 1443.16 seconds
Started Apr 25 01:57:41 PM PDT 24
Finished Apr 25 02:21:45 PM PDT 24
Peak memory 288816 kb
Host smart-d72748da-f409-468f-bab9-b8e54c93284e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476409971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.476409971
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.3354691269
Short name T517
Test name
Test status
Simulation time 278045076364 ps
CPU time 2207.1 seconds
Started Apr 25 01:57:42 PM PDT 24
Finished Apr 25 02:34:30 PM PDT 24
Peak memory 273296 kb
Host smart-83f6b5b1-4f1f-419a-bc6b-3d84e28c2d1c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354691269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.3354691269
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.937341588
Short name T300
Test name
Test status
Simulation time 106250363681 ps
CPU time 387.9 seconds
Started Apr 25 01:57:39 PM PDT 24
Finished Apr 25 02:04:08 PM PDT 24
Peak memory 255036 kb
Host smart-d1e8aef4-a812-4a36-b0ba-1ace44f8f1a4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937341588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.937341588
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.1605185894
Short name T351
Test name
Test status
Simulation time 1094751285 ps
CPU time 59.22 seconds
Started Apr 25 01:57:36 PM PDT 24
Finished Apr 25 01:58:36 PM PDT 24
Peak memory 248636 kb
Host smart-a20be712-bdd5-46b4-8fec-bd765ce7a589
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16051
85894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.1605185894
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.4065495922
Short name T461
Test name
Test status
Simulation time 354307545 ps
CPU time 27.88 seconds
Started Apr 25 01:57:36 PM PDT 24
Finished Apr 25 01:58:05 PM PDT 24
Peak memory 248588 kb
Host smart-99e41296-6f32-4750-bdd4-45c4496ce1da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40654
95922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.4065495922
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.1377839960
Short name T231
Test name
Test status
Simulation time 2622762095 ps
CPU time 40.42 seconds
Started Apr 25 01:57:36 PM PDT 24
Finished Apr 25 01:58:17 PM PDT 24
Peak memory 249172 kb
Host smart-f398bac1-be7b-467e-ac06-d610a8ec90bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13778
39960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.1377839960
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.589334551
Short name T441
Test name
Test status
Simulation time 577627419 ps
CPU time 30.76 seconds
Started Apr 25 01:57:29 PM PDT 24
Finished Apr 25 01:58:00 PM PDT 24
Peak memory 248676 kb
Host smart-9580bd41-a12b-415a-80e9-f6fc30f016f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58933
4551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.589334551
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.1546208763
Short name T209
Test name
Test status
Simulation time 19907429 ps
CPU time 2.7 seconds
Started Apr 25 01:52:51 PM PDT 24
Finished Apr 25 01:52:55 PM PDT 24
Peak memory 248892 kb
Host smart-41fff287-c5d0-4baf-b161-e700dd3547b6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1546208763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.1546208763
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.1712388181
Short name T73
Test name
Test status
Simulation time 419513935817 ps
CPU time 1635.13 seconds
Started Apr 25 01:52:50 PM PDT 24
Finished Apr 25 02:20:06 PM PDT 24
Peak memory 282784 kb
Host smart-b3a986eb-f80e-4ea3-8c97-3d81093c0f46
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712388181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.1712388181
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.2265869037
Short name T213
Test name
Test status
Simulation time 1639427532 ps
CPU time 18.84 seconds
Started Apr 25 01:52:57 PM PDT 24
Finished Apr 25 01:53:17 PM PDT 24
Peak memory 240472 kb
Host smart-2440a9ec-8016-43d9-af0b-24d30039baf4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2265869037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.2265869037
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.2418246523
Short name T610
Test name
Test status
Simulation time 592853786 ps
CPU time 37.34 seconds
Started Apr 25 01:53:27 PM PDT 24
Finished Apr 25 01:54:04 PM PDT 24
Peak memory 255956 kb
Host smart-c38219d9-aea3-4334-8d4e-2f6c3b5a466d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24182
46523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.2418246523
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.98961447
Short name T589
Test name
Test status
Simulation time 3188385337 ps
CPU time 49.18 seconds
Started Apr 25 01:52:57 PM PDT 24
Finished Apr 25 01:53:48 PM PDT 24
Peak memory 256036 kb
Host smart-959521b4-926e-4b5e-9353-871da13b06f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98961
447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.98961447
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.1996587809
Short name T302
Test name
Test status
Simulation time 69050565793 ps
CPU time 1348.95 seconds
Started Apr 25 01:52:51 PM PDT 24
Finished Apr 25 02:15:20 PM PDT 24
Peak memory 281552 kb
Host smart-a7b5a90f-db95-4432-b192-94a462134d5d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996587809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.1996587809
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.2857274220
Short name T489
Test name
Test status
Simulation time 55458936285 ps
CPU time 1602.53 seconds
Started Apr 25 01:52:51 PM PDT 24
Finished Apr 25 02:19:34 PM PDT 24
Peak memory 272700 kb
Host smart-e6931ef9-8aa7-49ee-a8ab-243fc6114f7c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857274220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.2857274220
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.2390615950
Short name T614
Test name
Test status
Simulation time 3113767401 ps
CPU time 32.58 seconds
Started Apr 25 01:52:53 PM PDT 24
Finished Apr 25 01:53:26 PM PDT 24
Peak memory 255908 kb
Host smart-398c0b11-edaa-4b7f-8ded-fc796569dc91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23906
15950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.2390615950
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.2450323714
Short name T575
Test name
Test status
Simulation time 1077711571 ps
CPU time 24.68 seconds
Started Apr 25 01:52:53 PM PDT 24
Finished Apr 25 01:53:18 PM PDT 24
Peak memory 247492 kb
Host smart-ff327750-b26a-465a-b634-dcef82a9e8c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24503
23714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.2450323714
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.3976635070
Short name T109
Test name
Test status
Simulation time 458357222 ps
CPU time 27.41 seconds
Started Apr 25 01:52:56 PM PDT 24
Finished Apr 25 01:53:24 PM PDT 24
Peak memory 255352 kb
Host smart-68843ece-f49d-4ed6-a140-22aff56a8193
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39766
35070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.3976635070
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.3086006914
Short name T221
Test name
Test status
Simulation time 839703235 ps
CPU time 51.07 seconds
Started Apr 25 01:52:54 PM PDT 24
Finished Apr 25 01:53:46 PM PDT 24
Peak memory 248704 kb
Host smart-7977a866-2dcf-46d9-9e5e-9ac76f81029c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30860
06914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.3086006914
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.1015020341
Short name T574
Test name
Test status
Simulation time 647723945781 ps
CPU time 2834.78 seconds
Started Apr 25 01:52:55 PM PDT 24
Finished Apr 25 02:40:11 PM PDT 24
Peak memory 281548 kb
Host smart-0ba44e26-8646-41d2-8c03-60d1ff4b2e07
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015020341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.1015020341
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.4121947476
Short name T246
Test name
Test status
Simulation time 366002677216 ps
CPU time 8693.89 seconds
Started Apr 25 01:52:54 PM PDT 24
Finished Apr 25 04:17:49 PM PDT 24
Peak memory 395304 kb
Host smart-782b2b12-1f07-4b2c-bdb4-a8e846abcd09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121947476 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.4121947476
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.497969341
Short name T195
Test name
Test status
Simulation time 70024190 ps
CPU time 2.99 seconds
Started Apr 25 01:52:56 PM PDT 24
Finished Apr 25 01:53:00 PM PDT 24
Peak memory 248880 kb
Host smart-e44cec20-1c4b-41c1-9f97-536e11bb4c2e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=497969341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.497969341
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.2517767688
Short name T473
Test name
Test status
Simulation time 13788858170 ps
CPU time 1328.21 seconds
Started Apr 25 01:52:59 PM PDT 24
Finished Apr 25 02:15:08 PM PDT 24
Peak memory 289412 kb
Host smart-a54bfff8-cb96-4700-b126-c1d5ef9d5dff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517767688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.2517767688
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.2723715385
Short name T550
Test name
Test status
Simulation time 3288610733 ps
CPU time 39.87 seconds
Started Apr 25 01:52:57 PM PDT 24
Finished Apr 25 01:53:38 PM PDT 24
Peak memory 248760 kb
Host smart-d3da8c60-9841-40c4-b555-ced2925dd9ae
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2723715385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.2723715385
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.311644842
Short name T380
Test name
Test status
Simulation time 5971253039 ps
CPU time 166.37 seconds
Started Apr 25 01:52:55 PM PDT 24
Finished Apr 25 01:55:42 PM PDT 24
Peak memory 256764 kb
Host smart-ec9cbfbe-8262-4f09-bbb5-d02e456dee3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31164
4842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.311644842
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.2966300125
Short name T79
Test name
Test status
Simulation time 3690696447 ps
CPU time 50.46 seconds
Started Apr 25 01:52:53 PM PDT 24
Finished Apr 25 01:53:44 PM PDT 24
Peak memory 256036 kb
Host smart-77c38ab3-ce32-4542-8891-b6d6af8d65ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29663
00125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.2966300125
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.3213392509
Short name T599
Test name
Test status
Simulation time 40295723894 ps
CPU time 1204.17 seconds
Started Apr 25 01:52:57 PM PDT 24
Finished Apr 25 02:13:02 PM PDT 24
Peak memory 265152 kb
Host smart-074ea7ea-e4a5-45cf-b0df-0a61cfdb3988
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213392509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.3213392509
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.2412092474
Short name T350
Test name
Test status
Simulation time 139456350720 ps
CPU time 1542.01 seconds
Started Apr 25 01:52:57 PM PDT 24
Finished Apr 25 02:18:40 PM PDT 24
Peak memory 288992 kb
Host smart-85eb8d2b-5a25-4614-ac6b-b3c134bc2497
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412092474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.2412092474
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.3217334626
Short name T607
Test name
Test status
Simulation time 25072031900 ps
CPU time 528.92 seconds
Started Apr 25 01:52:56 PM PDT 24
Finished Apr 25 02:01:45 PM PDT 24
Peak memory 248160 kb
Host smart-dbeb0c1a-0f88-4040-9612-f7eb342c7435
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217334626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.3217334626
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.767310335
Short name T72
Test name
Test status
Simulation time 903674601 ps
CPU time 15.56 seconds
Started Apr 25 01:52:53 PM PDT 24
Finished Apr 25 01:53:10 PM PDT 24
Peak memory 248708 kb
Host smart-26a67af2-a853-4e78-a557-00e445db14b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76731
0335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.767310335
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.2672743402
Short name T122
Test name
Test status
Simulation time 652147065 ps
CPU time 33.96 seconds
Started Apr 25 01:52:52 PM PDT 24
Finished Apr 25 01:53:27 PM PDT 24
Peak memory 255956 kb
Host smart-e5243fa4-9756-49e9-a6cf-7729aa252bbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26727
43402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.2672743402
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.1760787930
Short name T696
Test name
Test status
Simulation time 276798880 ps
CPU time 20.32 seconds
Started Apr 25 01:52:57 PM PDT 24
Finished Apr 25 01:53:18 PM PDT 24
Peak memory 256708 kb
Host smart-0a0e7650-2d6b-4b89-a79e-dc68afed76bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17607
87930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.1760787930
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.4020849252
Short name T363
Test name
Test status
Simulation time 22221677 ps
CPU time 3.29 seconds
Started Apr 25 01:52:52 PM PDT 24
Finished Apr 25 01:52:56 PM PDT 24
Peak memory 240392 kb
Host smart-aa4e4675-0f87-4ab7-af9b-55d8568c2b1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40208
49252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.4020849252
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.1910079369
Short name T241
Test name
Test status
Simulation time 14826684681 ps
CPU time 1449.85 seconds
Started Apr 25 01:52:58 PM PDT 24
Finished Apr 25 02:17:09 PM PDT 24
Peak memory 289412 kb
Host smart-c7b4c87a-4a36-400f-8d72-3e3724b55072
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910079369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.1910079369
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.1253790480
Short name T65
Test name
Test status
Simulation time 123476047060 ps
CPU time 8943.06 seconds
Started Apr 25 01:52:59 PM PDT 24
Finished Apr 25 04:22:03 PM PDT 24
Peak memory 322680 kb
Host smart-73facac9-83b4-4003-ac50-9aa41867e9a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253790480 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.1253790480
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.210505948
Short name T193
Test name
Test status
Simulation time 162725705 ps
CPU time 3.58 seconds
Started Apr 25 01:53:06 PM PDT 24
Finished Apr 25 01:53:10 PM PDT 24
Peak memory 248896 kb
Host smart-4a5af728-2c53-4b08-badb-adcb5b83a367
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=210505948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.210505948
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.1101568096
Short name T57
Test name
Test status
Simulation time 415563245054 ps
CPU time 1316.98 seconds
Started Apr 25 01:53:00 PM PDT 24
Finished Apr 25 02:14:57 PM PDT 24
Peak memory 273312 kb
Host smart-68dd5249-50ce-460d-81a0-3eea1a0fb8dd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101568096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.1101568096
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.1812641617
Short name T326
Test name
Test status
Simulation time 600503405 ps
CPU time 26.8 seconds
Started Apr 25 01:53:06 PM PDT 24
Finished Apr 25 01:53:33 PM PDT 24
Peak memory 248716 kb
Host smart-e69999fd-2ae3-4240-bf77-08f3c1988ef9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1812641617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.1812641617
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.2697630964
Short name T686
Test name
Test status
Simulation time 17672869207 ps
CPU time 237.35 seconds
Started Apr 25 01:53:02 PM PDT 24
Finished Apr 25 01:57:00 PM PDT 24
Peak memory 250156 kb
Host smart-9020d942-fb9c-4ac3-970c-4a2eb41452ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26976
30964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.2697630964
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.3248657949
Short name T438
Test name
Test status
Simulation time 2653402332 ps
CPU time 33.04 seconds
Started Apr 25 01:52:58 PM PDT 24
Finished Apr 25 01:53:32 PM PDT 24
Peak memory 256060 kb
Host smart-f0e3c883-8098-4f45-94cd-1654e36252ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32486
57949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.3248657949
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.1831896002
Short name T269
Test name
Test status
Simulation time 36540709255 ps
CPU time 2064.84 seconds
Started Apr 25 01:53:03 PM PDT 24
Finished Apr 25 02:27:28 PM PDT 24
Peak memory 284592 kb
Host smart-c6e96b3d-821b-4b7f-92cb-77c609eef280
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831896002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.1831896002
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.2201595462
Short name T465
Test name
Test status
Simulation time 69586265821 ps
CPU time 1900.86 seconds
Started Apr 25 01:53:00 PM PDT 24
Finished Apr 25 02:24:42 PM PDT 24
Peak memory 281532 kb
Host smart-68ee601e-ffff-4cdf-bb0d-7bd633b9f1ca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201595462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.2201595462
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.3737604804
Short name T495
Test name
Test status
Simulation time 31073986447 ps
CPU time 321.04 seconds
Started Apr 25 01:53:01 PM PDT 24
Finished Apr 25 01:58:23 PM PDT 24
Peak memory 248768 kb
Host smart-85728ba1-c35d-4486-8b0a-1a025446340a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737604804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.3737604804
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.3367764260
Short name T421
Test name
Test status
Simulation time 4435355069 ps
CPU time 70.68 seconds
Started Apr 25 01:52:59 PM PDT 24
Finished Apr 25 01:54:11 PM PDT 24
Peak memory 248760 kb
Host smart-6ba91f7d-15c0-443f-8a1b-ad52415cbb00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33677
64260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.3367764260
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.2355631408
Short name T408
Test name
Test status
Simulation time 2456396544 ps
CPU time 34.46 seconds
Started Apr 25 01:52:59 PM PDT 24
Finished Apr 25 01:53:35 PM PDT 24
Peak memory 249052 kb
Host smart-6c0f95f5-27f2-4cba-a3e5-eba1ba6bb69d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23556
31408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.2355631408
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.3702370841
Short name T447
Test name
Test status
Simulation time 793673936 ps
CPU time 11.39 seconds
Started Apr 25 01:52:59 PM PDT 24
Finished Apr 25 01:53:12 PM PDT 24
Peak memory 253964 kb
Host smart-697d8888-93c4-4c61-a460-71f0f6eb1807
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37023
70841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.3702370841
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.463337518
Short name T611
Test name
Test status
Simulation time 62117609 ps
CPU time 2.84 seconds
Started Apr 25 01:53:25 PM PDT 24
Finished Apr 25 01:53:28 PM PDT 24
Peak memory 240520 kb
Host smart-169bb5c6-db6e-4ff4-b506-715889081560
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46333
7518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.463337518
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.4215127676
Short name T90
Test name
Test status
Simulation time 5654210865 ps
CPU time 302.3 seconds
Started Apr 25 01:53:03 PM PDT 24
Finished Apr 25 01:58:06 PM PDT 24
Peak memory 255692 kb
Host smart-46873029-383f-469e-be10-71f961d4cf1d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215127676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.4215127676
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.224755590
Short name T201
Test name
Test status
Simulation time 17191920 ps
CPU time 2.43 seconds
Started Apr 25 01:53:06 PM PDT 24
Finished Apr 25 01:53:09 PM PDT 24
Peak memory 248864 kb
Host smart-198ab0cb-14d4-4841-bc61-52da8b5dc87f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=224755590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.224755590
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.3672751247
Short name T496
Test name
Test status
Simulation time 73201251034 ps
CPU time 1886.05 seconds
Started Apr 25 01:53:07 PM PDT 24
Finished Apr 25 02:24:33 PM PDT 24
Peak memory 272320 kb
Host smart-29459477-d84e-4232-bc85-a1c0a3b3a2ff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672751247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.3672751247
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.401302864
Short name T558
Test name
Test status
Simulation time 305303437 ps
CPU time 10.47 seconds
Started Apr 25 01:53:10 PM PDT 24
Finished Apr 25 01:53:21 PM PDT 24
Peak memory 248700 kb
Host smart-d6c7fcae-c0be-4cf2-8267-a04dd7425013
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=401302864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.401302864
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.576914236
Short name T616
Test name
Test status
Simulation time 3787347594 ps
CPU time 61.58 seconds
Started Apr 25 01:53:06 PM PDT 24
Finished Apr 25 01:54:08 PM PDT 24
Peak memory 255612 kb
Host smart-6b28e362-1abc-436e-bbd1-b34197be09ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57691
4236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.576914236
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.2879533436
Short name T632
Test name
Test status
Simulation time 2134698772 ps
CPU time 31.64 seconds
Started Apr 25 01:53:06 PM PDT 24
Finished Apr 25 01:53:38 PM PDT 24
Peak memory 255948 kb
Host smart-724ae883-261a-4d73-a9da-3318d98f8747
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28795
33436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.2879533436
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.284740647
Short name T316
Test name
Test status
Simulation time 92435450489 ps
CPU time 1407.07 seconds
Started Apr 25 01:53:11 PM PDT 24
Finished Apr 25 02:16:39 PM PDT 24
Peak memory 266364 kb
Host smart-7bee68c7-5ed4-420f-8ab8-64923f5fdff8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284740647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.284740647
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.1209477305
Short name T562
Test name
Test status
Simulation time 10972442268 ps
CPU time 954.77 seconds
Started Apr 25 01:53:07 PM PDT 24
Finished Apr 25 02:09:02 PM PDT 24
Peak memory 272352 kb
Host smart-545e2fb5-2cc5-4b6b-a0b7-26a3bf8858bb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209477305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.1209477305
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.2886287257
Short name T692
Test name
Test status
Simulation time 43285787892 ps
CPU time 477.58 seconds
Started Apr 25 01:53:06 PM PDT 24
Finished Apr 25 02:01:05 PM PDT 24
Peak memory 247872 kb
Host smart-baf73a4c-a5be-4b90-aeb2-e8f64bbb4c89
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886287257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.2886287257
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.2464059099
Short name T63
Test name
Test status
Simulation time 697398944 ps
CPU time 41.81 seconds
Started Apr 25 01:53:07 PM PDT 24
Finished Apr 25 01:53:49 PM PDT 24
Peak memory 248688 kb
Host smart-f6efb6be-d4b3-444b-8496-9997b24f3a73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24640
59099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.2464059099
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.1433844783
Short name T620
Test name
Test status
Simulation time 409290522 ps
CPU time 27.93 seconds
Started Apr 25 01:53:10 PM PDT 24
Finished Apr 25 01:53:38 PM PDT 24
Peak memory 248856 kb
Host smart-b187f9bc-5ad7-4e4f-a583-f131763b189f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14338
44783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.1433844783
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.4146399315
Short name T387
Test name
Test status
Simulation time 738521946 ps
CPU time 16.69 seconds
Started Apr 25 01:53:07 PM PDT 24
Finished Apr 25 01:53:24 PM PDT 24
Peak memory 255000 kb
Host smart-cae5cc42-e095-4dae-bf58-f2cbd7bd0ecf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41463
99315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.4146399315
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.2962687443
Short name T369
Test name
Test status
Simulation time 505193634 ps
CPU time 4.26 seconds
Started Apr 25 01:53:05 PM PDT 24
Finished Apr 25 01:53:10 PM PDT 24
Peak memory 240520 kb
Host smart-b711ab04-8c48-4847-a270-e1dd8f1a8191
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29626
87443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.2962687443
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.3185888710
Short name T443
Test name
Test status
Simulation time 624824168849 ps
CPU time 3330.91 seconds
Started Apr 25 01:53:09 PM PDT 24
Finished Apr 25 02:48:41 PM PDT 24
Peak memory 289188 kb
Host smart-4abb318d-9ec5-41fa-9d99-5455217e0be3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185888710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.3185888710
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.198584832
Short name T200
Test name
Test status
Simulation time 103543557 ps
CPU time 4.66 seconds
Started Apr 25 01:53:12 PM PDT 24
Finished Apr 25 01:53:18 PM PDT 24
Peak memory 248892 kb
Host smart-3b1028fd-7923-45b6-ae3c-fd3d8608ef7d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=198584832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.198584832
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.3006354884
Short name T689
Test name
Test status
Simulation time 226979997820 ps
CPU time 2358.99 seconds
Started Apr 25 01:53:09 PM PDT 24
Finished Apr 25 02:32:29 PM PDT 24
Peak memory 282604 kb
Host smart-04b31302-0a48-4923-8985-91f161e14ba3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006354884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.3006354884
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.797539033
Short name T520
Test name
Test status
Simulation time 778115645 ps
CPU time 28.14 seconds
Started Apr 25 01:53:12 PM PDT 24
Finished Apr 25 01:53:41 PM PDT 24
Peak memory 248700 kb
Host smart-cf235392-a2d0-44f9-97c4-74fae4fbcfac
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=797539033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.797539033
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.3613708615
Short name T653
Test name
Test status
Simulation time 5214421696 ps
CPU time 109.81 seconds
Started Apr 25 01:53:08 PM PDT 24
Finished Apr 25 01:54:59 PM PDT 24
Peak memory 256900 kb
Host smart-349a0d11-a95e-49ac-b376-ffd44f9f3414
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36137
08615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.3613708615
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.192952288
Short name T404
Test name
Test status
Simulation time 4438039017 ps
CPU time 61.61 seconds
Started Apr 25 01:53:07 PM PDT 24
Finished Apr 25 01:54:09 PM PDT 24
Peak memory 256260 kb
Host smart-33357d82-780a-4d94-95dc-8d10bc318a65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19295
2288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.192952288
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.2098740699
Short name T627
Test name
Test status
Simulation time 164381897604 ps
CPU time 2240.1 seconds
Started Apr 25 01:53:12 PM PDT 24
Finished Apr 25 02:30:33 PM PDT 24
Peak memory 272884 kb
Host smart-595bb364-0d76-447e-87c0-2790e9b6d5f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098740699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.2098740699
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.3994382583
Short name T43
Test name
Test status
Simulation time 16991391488 ps
CPU time 1044.54 seconds
Started Apr 25 01:53:14 PM PDT 24
Finished Apr 25 02:10:40 PM PDT 24
Peak memory 265456 kb
Host smart-f154c159-1666-4d6c-ab26-e5e1e664a075
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994382583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.3994382583
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.2872725580
Short name T637
Test name
Test status
Simulation time 9923056210 ps
CPU time 388.81 seconds
Started Apr 25 01:53:07 PM PDT 24
Finished Apr 25 01:59:36 PM PDT 24
Peak memory 247012 kb
Host smart-b08ab280-9b3b-4f77-ab7b-04ffa687f059
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872725580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.2872725580
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.2476075107
Short name T118
Test name
Test status
Simulation time 243850059 ps
CPU time 8.3 seconds
Started Apr 25 01:53:08 PM PDT 24
Finished Apr 25 01:53:17 PM PDT 24
Peak memory 248668 kb
Host smart-02b7cc26-1ce6-4462-bd66-9f8f58563b02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24760
75107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.2476075107
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.1531545027
Short name T498
Test name
Test status
Simulation time 120266162 ps
CPU time 6.86 seconds
Started Apr 25 01:53:11 PM PDT 24
Finished Apr 25 01:53:18 PM PDT 24
Peak memory 240508 kb
Host smart-f66fbc84-43c2-4e83-af9d-d3b1b5e11e0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15315
45027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.1531545027
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.1378485934
Short name T116
Test name
Test status
Simulation time 88548611 ps
CPU time 10.8 seconds
Started Apr 25 01:54:12 PM PDT 24
Finished Apr 25 01:54:23 PM PDT 24
Peak memory 247384 kb
Host smart-e235398c-076f-4db9-95f3-905706fff35e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13784
85934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.1378485934
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.2348737301
Short name T633
Test name
Test status
Simulation time 43045086 ps
CPU time 4.07 seconds
Started Apr 25 01:53:09 PM PDT 24
Finished Apr 25 01:53:13 PM PDT 24
Peak memory 240560 kb
Host smart-e1265694-c1a1-4f2c-98a6-a18a41d2497e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23487
37301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.2348737301
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.3155416307
Short name T691
Test name
Test status
Simulation time 243682186077 ps
CPU time 2162.53 seconds
Started Apr 25 01:53:16 PM PDT 24
Finished Apr 25 02:29:19 PM PDT 24
Peak memory 282244 kb
Host smart-3da4152e-b7d9-4071-95ee-95439275cc87
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155416307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.3155416307
Directory /workspace/9.alert_handler_stress_all/latest
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