Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	60050125	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

29066160

1

T1

91079

T2

3101

T3

4736

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	13705757	1			T1	31745		T2	1223		T3	1783
values[0x0]	36807943	1			T1	84658		T2	4264		T3	6488
values[0x1]	38602585	1			T1	128461		T2	4248		T3	6430

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	51305856	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

37810429

1

T1

137167

T2

3883

T3

5960

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	325897	1			T1	922		T2	31		T3	66
valid_sources[0x01]	282383	1			T1	805		T2	39		T3	49
valid_sources[0x02]	684255	1			T1	919		T2	35		T3	55
valid_sources[0x03]	287313	1			T1	1011		T2	36		T3	62
valid_sources[0x04]	999220	1			T1	1058		T2	38		T3	61
valid_sources[0x05]	285249	1			T1	855		T2	45		T3	60
valid_sources[0x06]	290889	1			T1	1065		T2	52		T3	47
valid_sources[0x07]	300859	1			T1	1034		T2	35		T3	71
valid_sources[0x08]	296861	1			T1	924		T2	26		T3	59
valid_sources[0x09]	287025	1			T1	772		T2	27		T3	56
valid_sources[0x0a]	285598	1			T1	985		T2	33		T3	52
valid_sources[0x0b]	289977	1			T1	924		T2	35		T3	64
valid_sources[0x0c]	289420	1			T1	1093		T2	34		T3	45
valid_sources[0x0d]	289246	1			T1	790		T2	46		T3	66
valid_sources[0x0e]	618471	1			T1	927		T2	45		T3	45
valid_sources[0x0f]	289036	1			T1	928		T2	40		T3	34
valid_sources[0x10]	282383	1			T1	1065		T2	30		T3	63
valid_sources[0x11]	285641	1			T1	890		T2	38		T3	60
valid_sources[0x12]	285653	1			T1	1027		T2	37		T3	67
valid_sources[0x13]	294162	1			T1	906		T2	28		T3	55
valid_sources[0x14]	308918	1			T1	973		T2	40		T3	55
valid_sources[0x15]	284572	1			T1	1058		T2	32		T3	53
valid_sources[0x16]	283335	1			T1	903		T2	47		T3	89
valid_sources[0x17]	291813	1			T1	1004		T2	43		T3	93
valid_sources[0x18]	286055	1			T1	924		T2	37		T3	56
valid_sources[0x19]	627465	1			T1	937		T2	35		T3	60
valid_sources[0x1a]	294770	1			T1	924		T2	28		T3	86
valid_sources[0x1b]	288249	1			T1	1068		T2	39		T3	58
valid_sources[0x1c]	288257	1			T1	912		T2	30		T3	49
valid_sources[0x1d]	291300	1			T1	869		T2	39		T3	52
valid_sources[0x1e]	287997	1			T1	768		T2	42		T3	64
valid_sources[0x1f]	287981	1			T1	946		T2	37		T3	58
valid_sources[0x20]	298046	1			T1	935		T2	39		T3	49
valid_sources[0x21]	288757	1			T1	1003		T2	38		T3	63
valid_sources[0x22]	668049	1			T1	931		T2	39		T3	58
valid_sources[0x23]	332915	1			T1	947		T2	27		T3	68
valid_sources[0x24]	290335	1			T1	1005		T2	30		T3	58
valid_sources[0x25]	293664	1			T1	879		T2	30		T3	84
valid_sources[0x26]	683853	1			T1	858		T2	44		T3	63
valid_sources[0x27]	288644	1			T1	967		T2	39		T3	64
valid_sources[0x28]	324413	1			T1	970		T2	32		T3	50
valid_sources[0x29]	680750	1			T1	1015		T2	40		T3	38
valid_sources[0x2a]	287462	1			T1	1091		T2	41		T3	58
valid_sources[0x2b]	292275	1			T1	1046		T2	46		T3	52
valid_sources[0x2c]	584749	1			T1	1093		T2	35		T3	52
valid_sources[0x2d]	333459	1			T1	1084		T2	34		T3	38
valid_sources[0x2e]	282668	1			T1	1010		T2	39		T3	47
valid_sources[0x2f]	291308	1			T1	877		T2	30		T3	52
valid_sources[0x30]	294572	1			T1	949		T2	35		T3	62
valid_sources[0x31]	297648	1			T1	1106		T2	42		T3	61
valid_sources[0x32]	285903	1			T1	915		T2	37		T3	58
valid_sources[0x33]	289552	1			T1	828		T2	32		T3	59
valid_sources[0x34]	754011	1			T1	972		T2	50		T3	46
valid_sources[0x35]	287390	1			T1	1019		T2	38		T3	38
valid_sources[0x36]	330077	1			T1	916		T2	36		T3	67
valid_sources[0x37]	283664	1			T1	1006		T2	42		T3	60
valid_sources[0x38]	503657	1			T1	848		T2	42		T3	44
valid_sources[0x39]	292672	1			T1	1052		T2	46		T3	86
valid_sources[0x3a]	725902	1			T1	1016		T2	32		T3	37
valid_sources[0x3b]	290057	1			T1	952		T2	58		T3	72
valid_sources[0x3c]	864937	1			T1	1056		T2	35		T3	60
valid_sources[0x3d]	282610	1			T1	1025		T2	34		T3	42
valid_sources[0x3e]	285012	1			T1	925		T2	41		T3	82
valid_sources[0x3f]	1032722	1			T1	998		T2	39		T3	62
valid_sources[0x40]	288930	1			T1	985		T2	38		T3	45
valid_sources[0x41]	287742	1			T1	855		T2	35		T3	56
valid_sources[0x42]	286006	1			T1	896		T2	47		T3	67
valid_sources[0x43]	288894	1			T1	994		T2	33		T3	70
valid_sources[0x44]	288515	1			T1	915		T2	34		T3	63
valid_sources[0x45]	293533	1			T1	982		T2	46		T3	99
valid_sources[0x46]	291673	1			T1	804		T2	32		T3	84
valid_sources[0x47]	291930	1			T1	819		T2	34		T3	53
valid_sources[0x48]	288261	1			T1	897		T2	36		T3	48
valid_sources[0x49]	286764	1			T1	1020		T2	34		T3	47
valid_sources[0x4a]	284443	1			T1	971		T2	37		T3	40
valid_sources[0x4b]	290004	1			T1	995		T2	40		T3	77
valid_sources[0x4c]	290676	1			T1	910		T2	48		T3	48
valid_sources[0x4d]	292481	1			T1	1005		T2	39		T3	47
valid_sources[0x4e]	291301	1			T1	939		T2	33		T3	63
valid_sources[0x4f]	285654	1			T1	960		T2	30		T3	49
valid_sources[0x50]	288589	1			T1	946		T2	42		T3	62
valid_sources[0x51]	283122	1			T1	889		T2	25		T3	47
valid_sources[0x52]	620807	1			T1	832		T2	51		T3	69
valid_sources[0x53]	291004	1			T1	930		T2	30		T3	43
valid_sources[0x54]	297815	1			T1	929		T2	25		T3	85
valid_sources[0x55]	288164	1			T1	1038		T2	40		T3	44
valid_sources[0x56]	291425	1			T1	914		T2	33		T3	43
valid_sources[0x57]	292388	1			T1	1120		T2	40		T3	74
valid_sources[0x58]	286747	1			T1	965		T2	46		T3	80
valid_sources[0x59]	304333	1			T1	859		T2	46		T3	65
valid_sources[0x5a]	287627	1			T1	942		T2	43		T3	68
valid_sources[0x5b]	294040	1			T1	1004		T2	37		T3	62
valid_sources[0x5c]	285912	1			T1	902		T2	40		T3	48
valid_sources[0x5d]	295834	1			T1	928		T2	46		T3	58
valid_sources[0x5e]	289068	1			T1	875		T2	19		T3	53
valid_sources[0x5f]	284656	1			T1	1035		T2	42		T3	59
valid_sources[0x60]	294804	1			T1	900		T2	35		T3	60
valid_sources[0x61]	758367	1			T1	948		T2	37		T3	30
valid_sources[0x62]	418723	1			T1	991		T2	43		T3	25
valid_sources[0x63]	287886	1			T1	866		T2	46		T3	66
valid_sources[0x64]	293693	1			T1	941		T2	29		T3	52
valid_sources[0x65]	283889	1			T1	945		T2	36		T3	71
valid_sources[0x66]	285147	1			T1	881		T2	29		T3	39
valid_sources[0x67]	288133	1			T1	1000		T2	47		T3	68
valid_sources[0x68]	289601	1			T1	954		T2	31		T3	49
valid_sources[0x69]	293613	1			T1	873		T2	30		T3	55
valid_sources[0x6a]	283691	1			T1	926		T2	29		T3	75
valid_sources[0x6b]	284950	1			T1	991		T2	37		T3	63
valid_sources[0x6c]	287428	1			T1	1011		T2	41		T3	58
valid_sources[0x6d]	285636	1			T1	1011		T2	50		T3	75
valid_sources[0x6e]	284101	1			T1	997		T2	39		T3	97
valid_sources[0x6f]	281940	1			T1	899		T2	39		T3	87
valid_sources[0x70]	289791	1			T1	1011		T2	31		T3	77
valid_sources[0x71]	291510	1			T1	989		T2	38		T3	61
valid_sources[0x72]	513498	1			T1	919		T2	39		T3	48
valid_sources[0x73]	293109	1			T1	910		T2	44		T3	44
valid_sources[0x74]	286805	1			T1	960		T2	47		T3	68
valid_sources[0x75]	296929	1			T1	927		T2	32		T3	79
valid_sources[0x76]	292286	1			T1	1073		T2	39		T3	68
valid_sources[0x77]	333406	1			T1	926		T2	45		T3	76
valid_sources[0x78]	287406	1			T1	933		T2	34		T3	45
valid_sources[0x79]	289185	1			T1	913		T2	47		T3	37
valid_sources[0x7a]	663044	1			T1	985		T2	34		T3	55
valid_sources[0x7b]	287568	1			T1	794		T2	43		T3	54
valid_sources[0x7c]	287115	1			T1	985		T2	41		T3	25
valid_sources[0x7d]	293978	1			T1	1041		T2	42		T3	49
valid_sources[0x7e]	293428	1			T1	1081		T2	37		T3	53
valid_sources[0x7f]	289870	1			T1	862		T2	36		T3	36
valid_sources[0x80]	297669	1			T1	946		T2	34		T3	66

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6775973

1

T1

20573

T2

600

T3

865

values[0x0]

all_enables

biggest_size

14072809

1

T1

40762

T2

1570

T3

2468

values[0x1]

all_enables

biggest_size

8217378

1

T1

29744

T2

931

T3

1403