Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	73490	1			T1	2		T33	5083		T11	1
class_i[0x1]	58716	1			T54	2		T4	601		T56	11
class_i[0x2]	47533	1			T55	2		T71	2		T56	4802
class_i[0x3]	59429	1			T4	5		T40	7		T55	23

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	60852	1			T33	1224		T11	1		T54	1
alert[0x1]	58631	1			T1	1		T33	1305		T4	193
alert[0x2]	62903	1			T33	1307		T4	154		T55	4
alert[0x3]	56782	1			T1	1		T33	1247		T54	1

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

238898

1

T33

5083

T11

1

T4

606

esc_ping_fail

270

1

T1

2

T54

2

T55

15

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	60778	1			T33	1224		T11	1		T4	113
esc_integrity_fail	alert[0x1]	58562	1			T33	1305		T4	193		T40	6
esc_integrity_fail	alert[0x2]	62840	1			T33	1307		T4	154		T22	8
esc_integrity_fail	alert[0x3]	56718	1			T33	1247		T4	146		T55	2
esc_ping_fail	alert[0x0]	74	1			T54	1		T55	4		T69	2
esc_ping_fail	alert[0x1]	69	1			T1	1		T55	4		T71	2
esc_ping_fail	alert[0x2]	63	1			T55	4		T71	1		T69	2
esc_ping_fail	alert[0x3]	64	1			T1	1		T54	1		T55	3

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	73435	1			T33	5083		T11	1		T22	9
esc_integrity_fail	class_i[0x1]	58656	1			T4	601		T56	11		T27	7
esc_integrity_fail	class_i[0x2]	47466	1			T55	2		T56	4802		T69	11
esc_integrity_fail	class_i[0x3]	59341	1			T4	5		T40	7		T55	8
esc_ping_fail	class_i[0x0]	55	1			T1	2		T71	3		T69	1
esc_ping_fail	class_i[0x1]	60	1			T54	2		T75	6		T124	7
esc_ping_fail	class_i[0x2]	67	1			T71	2		T75	2		T125	1
esc_ping_fail	class_i[0x3]	88	1			T55	15		T69	5		T75	1