Unified Coverage Report

Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	709906063	0	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	709906063	0	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	709906063	0	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	709906063	0	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	709906063	0	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	709906063	0	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	709906063	0	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	709906063	0	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	709906063	0	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	709906063	0	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	709906063	0	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	709906063	0	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	709906063	0	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	709906063	0	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	709906063	0	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	709906063	0	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	709906063	0	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	709906063	0	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	709906063	0	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	709906063	0	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	709906063	0	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	709906063	0	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	709906063	0	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	709906063	0	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	709906063	0	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	709906063	0	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	709906063	0	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	709906063	0	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	709906063	0	0	0
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	709906063	0	0	624
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	709906063	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	709906063	709834722	0	0
tb.dut.CheckAccuCntDw	0	0	624	624	0	0
tb.dut.CheckEscCntDw	0	0	624	624	0	0
tb.dut.CheckNAlerts	0	0	624	624	0	0
tb.dut.CheckNClasses	0	0	624	624	0	0
tb.dut.CheckNEscSev	0	0	624	624	0	0
tb.dut.CrashdumpKnownO_A	0	0	709906063	709834722	0	0
tb.dut.EdnKnownO_A	0	0	709906063	709834722	0	0
tb.dut.EscPKnownO_A	0	0	709906063	709834722	0	0
tb.dut.IrqAKnownO_A	0	0	709906063	709834722	0	0
tb.dut.IrqBKnownO_A	0	0	709906063	709834722	0	0
tb.dut.IrqCKnownO_A	0	0	709906063	709834722	0	0
tb.dut.IrqDKnownO_A	0	0	709906063	709834722	0	0
tb.dut.TlAReadyKnownO_A	0	0	709906063	709834722	0	0
tb.dut.TlDValidKnownO_A	0	0	709906063	709834722	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	731548820	2938040	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	731548820	12302	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	731548820	12016	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	731548820	11777	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	731548820	12088	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	731548820	11784	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	731548820	12048	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	731548820	11998	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	731548820	12330	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	731548820	12148	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	731548820	12287	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	731548820	12138	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	731548820	11910	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	731548820	11799	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	731548820	11974	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	731548820	11846	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	731548820	12166	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	731548820	11880	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	731548820	11750	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	731548820	12077	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	731548820	11958	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	731548820	12212	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	731548820	12121	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	731548820	11775	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	731548820	12078	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	731548820	11919	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	731548820	12492	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	731548820	11944	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	731548820	12184	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	731548820	11941	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	731548820	12239	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	731548820	11864	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	731548820	12112	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	731548820	12042	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	731548820	11947	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	731548820	11842	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	731548820	11686	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	731548820	11903	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	731548820	11876	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	731548820	12475	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	731548820	11995	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	731548820	12123	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	731548820	11671	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	731548820	12083	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	731548820	12122	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	731548820	12069	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	731548820	12178	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	731548820	11571	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	731548820	12243	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	731548820	11949	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	731548820	11815	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	731548820	11930	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	731548820	11851	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	731548820	11957	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	731548820	12212	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	731548820	11872	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	731548820	11826	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	731548820	11774	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	731548820	11894	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	731548820	12469	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	731548820	11953	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	731548820	12344	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	731548820	12089	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	731548820	12011	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	731548820	12015	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	731548820	11958	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	731548820	11823	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	731548820	12107	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	731548820	12071	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	731548820	12024	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	731548820	21393	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	731548820	12269	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	731548820	11833	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	731548820	12255	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	731548820	11893	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	731548820	11994	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	731548820	12125	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	731548820	12024	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	731548820	11803	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	709906063	5599	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	709906063	219338	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	709906063	361578291	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	709906063	884	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	709906063	37	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	709906063	463	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	709906063	275822624	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	709906063	993	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	709906063	975	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	709906063	944	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	709906063	927	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	709906063	721	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	709906063	103236	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	709906063	588	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	709906063	94	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	709906063	709834722	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	624	624	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	709906063	709834722	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	709906063	963	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	709906063	190994	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	709906063	406373530	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	709906063	532	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	709906063	25	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	709906063	263	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	709906063	327342456	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	709906063	600	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	709906063	590	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	709906063	582	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	709906063	570	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	709906063	1227	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	709906063	151355	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	709906063	1141	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	709906063	56	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	709906063	709834722	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	624	624	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	709906063	709834722	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	709906063	2941	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	709906063	181566	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	709906063	452061029	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	709906063	509	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	709906063	26	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	709906063	250	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	709906063	383099503	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	709906063	587	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	709906063	569	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	709906063	555	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	709906063	546	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	709906063	1333	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	709906063	154735	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	709906063	1246	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	709906063	61	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	709906063	709834722	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	624	624	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	709906063	709834722	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	709906063	5525	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	709906063	227738	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	709906063	377790642	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	709906063	520	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	709906063	27	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	709906063	256	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	709906063	296140471	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	709906063	616	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	709906063	605	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	709906063	590	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	709906063	578	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	709906063	1160	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	709906063	139842	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	709906063	1048	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	709906063	84	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	709906063	709834722	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	624	624	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	709906063	709834722	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	731548820	131660713	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	731548820	731000314	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	731548820	731000314	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	731548820	199796656	0	0
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tb.dut.tlul_assert_device.gen_assert_final[189].noOutstandingReqsAtEndOfSim_A	0	0	829	829	0	0
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tb.dut.tlul_assert_device.gen_assert_final[193].noOutstandingReqsAtEndOfSim_A	0	0	829	829	0	0
tb.dut.tlul_assert_device.gen_assert_final[194].noOutstandingReqsAtEndOfSim_A	0	0	829	829	0	0
tb.dut.tlul_assert_device.gen_assert_final[195].noOutstandingReqsAtEndOfSim_A	0	0	829	829	0	0
tb.dut.tlul_assert_device.gen_assert_final[196].noOutstandingReqsAtEndOfSim_A	0	0	829	829	0	0
tb.dut.tlul_assert_device.gen_assert_final[197].noOutstandingReqsAtEndOfSim_A	0	0	829	829	0	0
tb.dut.tlul_assert_device.gen_assert_final[198].noOutstandingReqsAtEndOfSim_A	0	0	829	829	0	0
tb.dut.tlul_assert_device.gen_assert_final[199].noOutstandingReqsAtEndOfSim_A	0	0	829	829	0	0

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	ASSERT	PROPERTIES	SEQUENCES
Total	1279	0	10
Category 0	1279	0	10

	ASSERT	PROPERTIES	SEQUENCES
Total	1279	0	10
Severity 0	1279	0	10

	NUMBER	PERCENT
Total Number	1279	100.00
Uncovered	31	2.42
Success	1248	97.58
Failure	0	0.00
Incomplete	49	3.83
Without Attempts	0	0.00

	NUMBER	PERCENT
Total Number	10	100.00
Uncovered	6	60.00
All Matches	4	40.00
First Matches	4	40.00