Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.61	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	2	42	95.45

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	2	42	95.45	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	183	1			T11	1		T55	1		T100	1
index[0x1]	178	1			T10	1		T20	1		T11	1
index[0x2]	179	1			T4	1		T22	2		T61	1
index[0x3]	173	1			T2	3		T11	1		T26	1

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	215	1			T11	3		T26	1		T55	1
lens_less_than_1000[1]	122	1			T2	1		T4	1		T22	1
lens_less_than_1000[2]	91	1			T2	1		T10	1		T56	1
lens_less_than_1000[3]	85	1			T20	1		T100	1		T27	2
lens_less_than_1000[4]	54	1			T68	1		T77	3		T35	1
lens_less_than_1000[5]	48	1			T22	2		T127	1		T114	1
lens_less_than_1000[6]	32	1			T41	2		T105	1		T260	1
lens_less_than_1000[7]	21	1			T83	1		T289	1		T110	1
lens_less_than_1000[8]	25	1			T2	1		T22	2		T263	1
lens_less_than_1000[9]	2	1			T118	1		T290	1		-	-
len_2	18	1			T56	1		T24	2		T291	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	2	42	95.45	2

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x0]]	[lens_less_than_1000[9]]	0	1	1
[index[0x3]]	[lens_less_than_1000[9]]	0	1	1

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	55	1			T11	1		T55	1		T99	1
index[0x0]	lens_less_than_1000[1]	31	1			T117	2		T292	1		T92	1
index[0x0]	lens_less_than_1000[2]	23	1			T127	1		T139	1		T89	4
index[0x0]	lens_less_than_1000[3]	20	1			T100	1		T27	2		T12	1
index[0x0]	lens_less_than_1000[4]	12	1			T77	2		T44	1		T110	1
index[0x0]	lens_less_than_1000[5]	11	1			T106	1		T293	1		T42	1
index[0x0]	lens_less_than_1000[6]	12	1			T294	1		T276	1		T295	1
index[0x0]	lens_less_than_1000[7]	7	1			T83	1		T296	1		T283	3
index[0x0]	lens_less_than_1000[8]	10	1			T263	1		T44	1		T297	1
index[0x0]	len_2	2	1			T291	1		T298	1		-	-
index[0x1]	lens_less_than_1000[0]	53	1			T11	1		T74	1		T65	1
index[0x1]	lens_less_than_1000[1]	21	1			T18	1		T37	1		T89	1
index[0x1]	lens_less_than_1000[2]	32	1			T10	1		T17	1		T102	1
index[0x1]	lens_less_than_1000[3]	23	1			T20	1		T18	1		T24	1
index[0x1]	lens_less_than_1000[4]	17	1			T77	1		T254	1		T83	1
index[0x1]	lens_less_than_1000[5]	8	1			T114	1		T299	1		T92	1
index[0x1]	lens_less_than_1000[6]	7	1			T41	1		T50	1		T276	1
index[0x1]	lens_less_than_1000[7]	5	1			T289	1		T300	1		T301	1
index[0x1]	lens_less_than_1000[8]	5	1			T302	1		T303	1		T304	1
index[0x1]	lens_less_than_1000[9]	1	1			T290	1		-	-		-	-
index[0x1]	len_2	6	1			T56	1		T24	2		T305	1
index[0x2]	lens_less_than_1000[0]	50	1			T61	1		T127	1		T268	2
index[0x2]	lens_less_than_1000[1]	40	1			T4	1		T24	1		T83	1
index[0x2]	lens_less_than_1000[2]	17	1			T306	1		T118	1		T45	1
index[0x2]	lens_less_than_1000[3]	20	1			T30	1		T44	1		T50	2
index[0x2]	lens_less_than_1000[4]	17	1			T35	1		T307	1		T89	1
index[0x2]	lens_less_than_1000[5]	13	1			T254	1		T308	2		T39	1
index[0x2]	lens_less_than_1000[6]	5	1			T41	1		T294	1		T309	2
index[0x2]	lens_less_than_1000[7]	4	1			T110	1		T138	1		T275	1
index[0x2]	lens_less_than_1000[8]	7	1			T22	2		T310	1		T311	1
index[0x2]	lens_less_than_1000[9]	1	1			T118	1		-	-		-	-
index[0x2]	len_2	5	1			T312	1		T313	1		T314	1
index[0x3]	lens_less_than_1000[0]	57	1			T11	1		T26	1		T27	1
index[0x3]	lens_less_than_1000[1]	30	1			T2	1		T22	1		T24	2
index[0x3]	lens_less_than_1000[2]	19	1			T2	1		T56	1		T84	1
index[0x3]	lens_less_than_1000[3]	22	1			T17	1		T44	1		T137	1
index[0x3]	lens_less_than_1000[4]	8	1			T68	1		T315	1		T316	1
index[0x3]	lens_less_than_1000[5]	16	1			T22	2		T127	1		T262	1
index[0x3]	lens_less_than_1000[6]	8	1			T105	1		T260	1		T134	1
index[0x3]	lens_less_than_1000[7]	5	1			T94	1		T133	1		T317	1
index[0x3]	lens_less_than_1000[8]	3	1			T2	1		T318	1		T319	1
index[0x3]	len_2	5	1			T46	5		-	-		-	-