Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	2	38	95.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	2	38	95.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	94	1			T23	1		T103	1		T24	1
class_index[0x1]	56	1			T77	1		T65	1		T23	1
class_index[0x2]	61	1			T65	1		T17	1		T23	1
class_index[0x3]	84	1			T29	3		T56	1		T65	2

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	106	1			T29	3		T77	1		T65	2
intr_timeout_cnt[1]	60	1			T56	1		T65	1		T17	1
intr_timeout_cnt[2]	27	1			T24	1		T30	1		T83	1
intr_timeout_cnt[3]	16	1			T110	1		T118	1		T138	1
intr_timeout_cnt[4]	16	1			T30	1		T89	1		T52	1
intr_timeout_cnt[5]	17	1			T30	1		T84	1		T94	4
intr_timeout_cnt[6]	21	1			T83	1		T44	1		T108	1
intr_timeout_cnt[7]	15	1			T23	1		T105	1		T83	1
intr_timeout_cnt[8]	11	1			T65	1		T30	1		T121	1
intr_timeout_cnt[9]	6	1			T23	1		T118	1		T269	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	2	38	95.00	2

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x1]]	[intr_timeout_cnt[8]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[9]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	45	1			T24	1		T107	1		T109	5
class_index[0x0]	intr_timeout_cnt[1]	17	1			T103	1		T270	1		T91	1
class_index[0x0]	intr_timeout_cnt[2]	7	1			T108	1		T43	2		T271	1
class_index[0x0]	intr_timeout_cnt[3]	2	1			T272	1		T273	1		-	-
class_index[0x0]	intr_timeout_cnt[4]	4	1			T274	1		T275	1		T206	1
class_index[0x0]	intr_timeout_cnt[5]	3	1			T276	1		T274	1		T121	1
class_index[0x0]	intr_timeout_cnt[6]	5	1			T83	1		T44	1		T264	1
class_index[0x0]	intr_timeout_cnt[7]	6	1			T23	1		T105	1		T84	2
class_index[0x0]	intr_timeout_cnt[8]	2	1			T121	1		T277	1		-	-
class_index[0x0]	intr_timeout_cnt[9]	3	1			T118	1		T269	1		T278	1
class_index[0x1]	intr_timeout_cnt[0]	22	1			T77	1		T24	1		T35	1
class_index[0x1]	intr_timeout_cnt[1]	15	1			T65	1		T83	1		T44	2
class_index[0x1]	intr_timeout_cnt[2]	4	1			T24	1		T83	1		T264	1
class_index[0x1]	intr_timeout_cnt[3]	3	1			T118	1		T138	1		T130	1
class_index[0x1]	intr_timeout_cnt[4]	5	1			T30	1		T89	1		T52	1
class_index[0x1]	intr_timeout_cnt[5]	1	1			T273	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[6]	2	1			T108	1		T121	1		-	-
class_index[0x1]	intr_timeout_cnt[7]	3	1			T279	1		T267	2		-	-
class_index[0x1]	intr_timeout_cnt[9]	1	1			T23	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	15	1			T104	1		T106	1		T280	1
class_index[0x2]	intr_timeout_cnt[1]	9	1			T17	1		T23	1		T35	2
class_index[0x2]	intr_timeout_cnt[2]	7	1			T30	1		T110	1		T138	1
class_index[0x2]	intr_timeout_cnt[3]	8	1			T110	1		T38	1		T281	1
class_index[0x2]	intr_timeout_cnt[4]	3	1			T282	1		T38	1		T283	1
class_index[0x2]	intr_timeout_cnt[5]	6	1			T94	3		T274	1		T46	1
class_index[0x2]	intr_timeout_cnt[6]	2	1			T91	1		T267	1		-	-
class_index[0x2]	intr_timeout_cnt[7]	5	1			T83	1		T37	3		T284	1
class_index[0x2]	intr_timeout_cnt[8]	4	1			T65	1		T122	1		T265	1
class_index[0x2]	intr_timeout_cnt[9]	2	1			T267	1		T273	1		-	-
class_index[0x3]	intr_timeout_cnt[0]	24	1			T29	3		T65	2		T102	1
class_index[0x3]	intr_timeout_cnt[1]	19	1			T56	1		T89	1		T129	1
class_index[0x3]	intr_timeout_cnt[2]	9	1			T44	1		T89	1		T45	1
class_index[0x3]	intr_timeout_cnt[3]	3	1			T281	1		T285	1		T80	1
class_index[0x3]	intr_timeout_cnt[4]	4	1			T286	1		T269	1		T203	1
class_index[0x3]	intr_timeout_cnt[5]	7	1			T30	1		T84	1		T94	1
class_index[0x3]	intr_timeout_cnt[6]	12	1			T287	4		T269	5		T283	1
class_index[0x3]	intr_timeout_cnt[7]	1	1			T288	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[8]	5	1			T30	1		T122	1		T219	1