Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	353825	1			T1	15		T2	11		T3	11
all_values[1]	353825	1			T1	15		T2	11		T3	11
all_values[2]	353825	1			T1	15		T2	11		T3	11
all_values[3]	353825	1			T1	15		T2	11		T3	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

704531

1

T2

24

T3

30

T7

3554

auto[1]

710769

1

T1

60

T2

20

T3

14

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

846263

1

T1

53

T2

24

T3

39

auto[1]

569037

1

T1

7

T2

20

T3

5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	101820	1			T2	2		T3	3		T7	456
all_values[0]	auto[0]	auto[1]	74137	1			T2	2		T3	3		T7	453
all_values[0]	auto[1]	auto[0]	103259	1			T1	13		T2	4		T3	3
all_values[0]	auto[1]	auto[1]	74609	1			T1	2		T2	3		T3	2
all_values[1]	auto[0]	auto[0]	106744	1			T2	3		T3	7		T7	432
all_values[1]	auto[0]	auto[1]	69595	1			T2	3		T7	423		T8	1
all_values[1]	auto[1]	auto[0]	107671	1			T1	15		T2	3		T3	4
all_values[1]	auto[1]	auto[1]	69815	1			T2	2		T7	475		T16	7
all_values[2]	auto[0]	auto[0]	106625	1			T2	4		T3	9		T7	450
all_values[2]	auto[0]	auto[1]	69286	1			T2	3		T7	431		T8	1
all_values[2]	auto[1]	auto[0]	108272	1			T1	13		T2	2		T3	2
all_values[2]	auto[1]	auto[1]	69642	1			T1	2		T2	2		T7	467
all_values[3]	auto[0]	auto[0]	105408	1			T2	4		T3	8		T7	455
all_values[3]	auto[0]	auto[1]	70916	1			T2	3		T7	454		T8	210
all_values[3]	auto[1]	auto[0]	106464	1			T1	12		T2	2		T3	3
all_values[3]	auto[1]	auto[1]	71037	1			T1	3		T2	2		T7	455