Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	353825	1			T1	15		T2	11		T3	11
all_pins[1]	353825	1			T1	15		T2	11		T3	11
all_pins[2]	353825	1			T1	15		T2	11		T3	11
all_pins[3]	353825	1			T1	15		T2	11		T3	11

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1130197	1			T1	53		T2	35		T3	42
values[0x1]	285103	1			T1	7		T2	9		T3	2
transitions[0x0=>0x1]	189278	1			T1	7		T2	5		T3	2
transitions[0x1=>0x0]	189538	1			T1	7		T2	6		T3	2

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	279216	1			T1	13		T2	8		T3	9
all_pins[0]	values[0x1]	74609	1			T1	2		T2	3		T3	2
all_pins[0]	transitions[0x0=>0x1]	73924	1			T1	2		T2	2		T3	2
all_pins[0]	transitions[0x1=>0x0]	70612	1			T1	3		T2	2		T7	455
all_pins[1]	values[0x0]	284010	1			T1	15		T2	9		T3	11
all_pins[1]	values[0x1]	69815	1			T2	2		T7	475		T16	7
all_pins[1]	transitions[0x0=>0x1]	37917	1			T2	1		T7	233		T16	3
all_pins[1]	transitions[0x1=>0x0]	42711	1			T1	2		T2	2		T3	2
all_pins[2]	values[0x0]	284183	1			T1	13		T2	9		T3	11
all_pins[2]	values[0x1]	69642	1			T1	2		T2	2		T7	467
all_pins[2]	transitions[0x0=>0x1]	38094	1			T1	2		T2	1		T7	216
all_pins[2]	transitions[0x1=>0x0]	38267	1			T2	1		T7	224		T16	5
all_pins[3]	values[0x0]	282788	1			T1	12		T2	9		T3	11
all_pins[3]	values[0x1]	71037	1			T1	3		T2	2		T7	455
all_pins[3]	transitions[0x0=>0x1]	39343	1			T1	3		T2	1		T7	213
all_pins[3]	transitions[0x1=>0x0]	37948	1			T1	2		T2	1		T7	225