Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	278	1			T180	4		T181	7		T182	7
all_values[1]	278	1			T180	4		T181	7		T182	7
all_values[2]	278	1			T180	4		T181	7		T182	7
all_values[3]	278	1			T180	4		T181	7		T182	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

612

1

T180

9

T181

6

T182

12

auto[1]

500

1

T180

7

T181

22

T182

16

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

388

1

T180

4

T181

1

T182

17

auto[1]

724

1

T180

12

T181

27

T182

11

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

611

1

T180

5

T181

11

T182

17

auto[1]

501

1

T180

11

T181

17

T182

11

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

58

1

T180

1

T181

1

T371

3

all_values[0]

auto[0]

auto[0]

auto[1]

28

1

T372

1

T373

1

T374

1

all_values[0]

auto[0]

auto[1]

auto[0]

35

1

T182

2

T375

1

T376

3

all_values[0]

auto[0]

auto[1]

auto[1]

28

1

T180

1

T181

1

T377

1

all_values[0]

auto[1]

auto[0]

auto[1]

78

1

T180

2

T181

2

T182

3

all_values[0]

auto[1]

auto[1]

auto[1]

51

1

T181

3

T182

2

T372

3

all_values[1]

auto[0]

auto[0]

auto[0]

59

1

T182

1

T371

1

T376

1

all_values[1]

auto[0]

auto[0]

auto[1]

23

1

T371

1

T372

2

T378

1

all_values[1]

auto[0]

auto[1]

auto[0]

41

1

T180

1

T182

2

T371

1

all_values[1]

auto[0]

auto[1]

auto[1]

29

1

T181

4

T376

1

T373

2

all_values[1]

auto[1]

auto[0]

auto[1]

70

1

T182

1

T371

1

T372

1

all_values[1]

auto[1]

auto[1]

auto[1]

56

1

T180

3

T181

3

T182

3

all_values[2]

auto[0]

auto[0]

auto[0]

49

1

T182

3

T371

1

T375

1

all_values[2]

auto[0]

auto[0]

auto[1]

29

1

T375

2

T376

1

T377

1

all_values[2]

auto[0]

auto[1]

auto[0]

30

1

T180

1

T182

3

T372

1

all_values[2]

auto[0]

auto[1]

auto[1]

36

1

T181

2

T377

1

T378

1

all_values[2]

auto[1]

auto[0]

auto[1]

75

1

T180

3

T181

2

T182

1

all_values[2]

auto[1]

auto[1]

auto[1]

59

1

T181

3

T371

2

T375

1

all_values[3]

auto[0]

auto[0]

auto[0]

59

1

T180

1

T182

3

T371

1

all_values[3]

auto[0]

auto[0]

auto[1]

19

1

T371

1

T375

1

T378

1

all_values[3]

auto[0]

auto[1]

auto[0]

57

1

T182

3

T371

1

T376

1

all_values[3]

auto[0]

auto[1]

auto[1]

31

1

T181

3

T376

1

T374

2

all_values[3]

auto[1]

auto[0]

auto[1]

65

1

T180

2

T181

1

T371

1

all_values[3]

auto[1]

auto[1]

auto[1]

47

1

T180

1

T181

3

T182

1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal