Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	88400	1			T7	1440		T10	888		T33	906
accum_cnt_1000	219676	1			T7	1514		T8	2060		T10	992
accum_cnt_100	29269	1			T7	83		T8	245		T10	56
accum_cnt_50	63293	1			T2	1		T7	69		T8	161
accum_cnt_10	168687	1			T1	2		T2	17		T3	7
accum_cnt_0	425487	1			T1	38		T2	6		T3	21

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	260677	1			T1	10		T2	6		T3	7
class_index[0x1]	260677	1			T1	10		T2	6		T3	7
class_index[0x2]	260677	1			T1	10		T2	6		T3	7
class_index[0x3]	260677	1			T1	10		T2	6		T3	7

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	26078	1			T7	437		T33	232		T64	424
class_index[0x0]	accum_cnt_1000	59530	1			T7	410		T8	1126		T49	354
class_index[0x0]	accum_cnt_100	9861	1			T7	22		T8	76		T49	153
class_index[0x0]	accum_cnt_50	18733	1			T7	21		T8	58		T16	2
class_index[0x0]	accum_cnt_10	42221	1			T2	6		T3	7		T7	2
class_index[0x0]	accum_cnt_0	93704	1			T1	10		T8	2		T15	4
class_index[0x1]	accum_cnt_2000	22168	1			T7	582		T33	674		T63	177
class_index[0x1]	accum_cnt_1000	53357	1			T7	705		T33	620		T4	417
class_index[0x1]	accum_cnt_100	6883	1			T7	41		T33	37		T4	52
class_index[0x1]	accum_cnt_50	13874	1			T7	31		T9	13		T33	24
class_index[0x1]	accum_cnt_10	46728	1			T2	1		T7	7		T9	3
class_index[0x1]	accum_cnt_0	107061	1			T1	10		T2	5		T3	7
class_index[0x2]	accum_cnt_2000	17524	1			T10	453		T63	155		T61	546
class_index[0x2]	accum_cnt_1000	48453	1			T10	608		T63	656		T61	682
class_index[0x2]	accum_cnt_100	5551	1			T10	33		T63	34		T61	39
class_index[0x2]	accum_cnt_50	15014	1			T2	1		T10	27		T25	10
class_index[0x2]	accum_cnt_10	41521	1			T1	1		T2	5		T8	1282
class_index[0x2]	accum_cnt_0	121357	1			T1	9		T3	7		T7	1372
class_index[0x3]	accum_cnt_2000	22630	1			T7	421		T10	435		T26	368
class_index[0x3]	accum_cnt_1000	58336	1			T7	399		T8	934		T10	384
class_index[0x3]	accum_cnt_100	6974	1			T7	20		T8	169		T10	23
class_index[0x3]	accum_cnt_50	15672	1			T7	17		T8	103		T16	4
class_index[0x3]	accum_cnt_10	38217	1			T1	1		T2	5		T7	4
class_index[0x3]	accum_cnt_0	103365	1			T1	9		T2	1		T3	7