Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	11682	1			T40	395		T55	1		T124	1
alert[0x1]	3403	1			T33	22		T11	1		T54	1
alert[0x2]	3913	1			T33	140		T22	45		T17	2
alert[0x3]	5176	1			T40	21		T71	1		T56	247
alert[0x4]	6760	1			T33	1		T25	1		T72	5
alert[0x5]	9529	1			T54	1		T40	1402		T22	24
alert[0x6]	11615	1			T33	1874		T11	1		T40	3
alert[0x7]	14011	1			T33	41		T22	68		T56	69
alert[0x8]	4226	1			T33	458		T4	9		T72	1
alert[0x9]	14980	1			T11	29		T22	69		T99	1
alert[0xa]	5274	1			T8	1		T20	1		T33	11
alert[0xb]	4358	1			T33	71		T75	1		T125	1
alert[0xc]	4791	1			T40	49		T55	2		T22	1329
alert[0xd]	9638	1			T33	51		T4	9		T22	63
alert[0xe]	4640	1			T33	71		T54	1		T71	1
alert[0xf]	3394	1			T1	1		T40	6		T69	1
alert[0x10]	6194	1			T4	120		T40	242		T69	1
alert[0x11]	7025	1			T40	196		T75	1		T17	6
alert[0x12]	10166	1			T25	3		T40	3283		T22	2160
alert[0x13]	5842	1			T33	92		T4	4		T40	281
alert[0x14]	12103	1			T40	37		T55	1		T22	5428
alert[0x15]	3982	1			T25	1		T22	474		T69	2
alert[0x16]	7514	1			T33	771		T22	34		T71	1
alert[0x17]	4135	1			T65	6		T124	1		T17	2
alert[0x18]	7779	1			T8	2		T75	1		T124	1
alert[0x19]	3699	1			T33	27		T22	31		T71	1
alert[0x1a]	14818	1			T1	1		T33	116		T55	1
alert[0x1b]	7884	1			T33	40		T40	3258		T22	100
alert[0x1c]	5461	1			T33	71		T40	42		T22	124
alert[0x1d]	17565	1			T33	51		T40	40		T22	105
alert[0x1e]	9695	1			T40	71		T71	2		T56	276
alert[0x1f]	5028	1			T33	133		T40	286		T55	1
alert[0x20]	5185	1			T69	1		T322	61		T139	105
alert[0x21]	4279	1			T25	15		T55	1		T22	41
alert[0x22]	6882	1			T40	50		T69	1		T125	1
alert[0x23]	5007	1			T11	10		T40	503		T22	707
alert[0x24]	6342	1			T40	458		T55	1		T17	7
alert[0x25]	13994	1			T22	13		T253	1		T322	96
alert[0x26]	3239	1			T33	122		T25	1		T22	438
alert[0x27]	10504	1			T33	508		T40	220		T55	2
alert[0x28]	4043	1			T1	1		T22	396		T124	1
alert[0x29]	10174	1			T40	123		T22	1269		T17	44
alert[0x2a]	7735	1			T22	29		T124	1		T76	1
alert[0x2b]	3584	1			T33	93		T25	5		T40	155
alert[0x2c]	8747	1			T33	62		T25	20		T40	3064
alert[0x2d]	10193	1			T40	38		T22	473		T56	102
alert[0x2e]	9945	1			T1	1		T40	90		T71	1
alert[0x2f]	5224	1			T40	82		T72	1		T124	1
alert[0x30]	5535	1			T33	3		T40	301		T22	137
alert[0x31]	4230	1			T33	17		T40	44		T22	183
alert[0x32]	7200	1			T25	2		T55	1		T22	236
alert[0x33]	3026	1			T54	1		T40	239		T30	3
alert[0x34]	10629	1			T25	1		T40	57		T22	220
alert[0x35]	6044	1			T1	1		T4	63		T40	47
alert[0x36]	7671	1			T33	22		T40	31		T22	93
alert[0x37]	5887	1			T40	603		T69	1		T75	1
alert[0x38]	7457	1			T11	3		T25	1		T40	79
alert[0x39]	6526	1			T33	586		T72	1		T76	3
alert[0x3a]	8061	1			T4	27		T22	80		T30	2
alert[0x3b]	5511	1			T55	1		T27	1		T24	1
alert[0x3c]	3892	1			T33	183		T22	88		T56	11
alert[0x3d]	2357	1			T40	5		T55	1		T56	79
alert[0x3e]	2122	1			T54	1		T56	33		T17	8
alert[0x3f]	5659	1			T33	114		T40	9		T99	3
alert[0x40]	5139	1			T33	86		T56	21		T24	43

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	106687	1			T8	3		T25	22		T4	232
class_i[0x1]	80820	1			T20	1		T33	7		T11	44
class_i[0x2]	123830	1			T1	2		T25	28		T54	4
class_i[0x3]	146966	1			T1	3		T33	5830		T40	16723

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

457605

1

T20

1

T33

5837

T11

44

alert_ping_fail

698

1

T1

5

T8

3

T54

5

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	11667	1			T40	395		T17	47		T30	67
alert_integrity_fail	alert[0x1]	3389	1			T33	22		T11	1		T72	9
alert_integrity_fail	alert[0x2]	3910	1			T33	140		T22	45		T17	2
alert_integrity_fail	alert[0x3]	5165	1			T40	21		T56	247		T72	9
alert_integrity_fail	alert[0x4]	6753	1			T33	1		T25	1		T72	5
alert_integrity_fail	alert[0x5]	9515	1			T40	1402		T22	24		T99	5
alert_integrity_fail	alert[0x6]	11608	1			T33	1874		T11	1		T40	3
alert_integrity_fail	alert[0x7]	14000	1			T33	41		T22	68		T56	69
alert_integrity_fail	alert[0x8]	4209	1			T33	458		T4	9		T72	1
alert_integrity_fail	alert[0x9]	14971	1			T11	29		T22	69		T99	1
alert_integrity_fail	alert[0xa]	5258	1			T20	1		T33	11		T40	913
alert_integrity_fail	alert[0xb]	4345	1			T33	71		T268	2		T30	1
alert_integrity_fail	alert[0xc]	4779	1			T40	49		T22	1329		T65	1
alert_integrity_fail	alert[0xd]	9628	1			T33	51		T4	9		T22	63
alert_integrity_fail	alert[0xe]	4628	1			T33	71		T17	1		T35	18
alert_integrity_fail	alert[0xf]	3389	1			T40	6		T65	2		T322	18
alert_integrity_fail	alert[0x10]	6183	1			T4	120		T40	242		T17	22
alert_integrity_fail	alert[0x11]	7019	1			T40	196		T17	6		T24	1
alert_integrity_fail	alert[0x12]	10154	1			T25	3		T40	3283		T22	2160
alert_integrity_fail	alert[0x13]	5830	1			T33	92		T4	4		T40	281
alert_integrity_fail	alert[0x14]	12085	1			T40	37		T22	5428		T72	4
alert_integrity_fail	alert[0x15]	3973	1			T25	1		T22	474		T17	7
alert_integrity_fail	alert[0x16]	7498	1			T33	771		T22	34		T65	2
alert_integrity_fail	alert[0x17]	4126	1			T65	6		T17	2		T24	19
alert_integrity_fail	alert[0x18]	7765	1			T35	103		T50	44		T13	81
alert_integrity_fail	alert[0x19]	3691	1			T33	27		T22	31		T65	7
alert_integrity_fail	alert[0x1a]	14800	1			T33	116		T22	5		T56	114
alert_integrity_fail	alert[0x1b]	7871	1			T33	40		T40	3258		T22	100
alert_integrity_fail	alert[0x1c]	5444	1			T33	71		T40	42		T22	124
alert_integrity_fail	alert[0x1d]	17561	1			T33	51		T40	40		T22	105
alert_integrity_fail	alert[0x1e]	9686	1			T40	71		T56	276		T322	4292
alert_integrity_fail	alert[0x1f]	5010	1			T33	133		T40	286		T22	34
alert_integrity_fail	alert[0x20]	5178	1			T322	61		T139	105		T83	1
alert_integrity_fail	alert[0x21]	4272	1			T25	15		T22	41		T322	5
alert_integrity_fail	alert[0x22]	6862	1			T40	50		T24	2		T30	77
alert_integrity_fail	alert[0x23]	5002	1			T11	10		T40	503		T22	707
alert_integrity_fail	alert[0x24]	6336	1			T40	458		T17	7		T35	7
alert_integrity_fail	alert[0x25]	13989	1			T22	13		T322	96		T105	1
alert_integrity_fail	alert[0x26]	3227	1			T33	122		T25	1		T22	438
alert_integrity_fail	alert[0x27]	10494	1			T33	508		T40	220		T22	401
alert_integrity_fail	alert[0x28]	4028	1			T22	396		T18	16		T24	32
alert_integrity_fail	alert[0x29]	10168	1			T40	123		T22	1269		T17	44
alert_integrity_fail	alert[0x2a]	7721	1			T22	29		T18	2		T35	23
alert_integrity_fail	alert[0x2b]	3574	1			T33	93		T25	5		T40	155
alert_integrity_fail	alert[0x2c]	8731	1			T33	62		T25	20		T40	3064
alert_integrity_fail	alert[0x2d]	10178	1			T40	38		T22	473		T56	102
alert_integrity_fail	alert[0x2e]	9930	1			T40	90		T56	152		T18	6
alert_integrity_fail	alert[0x2f]	5212	1			T40	82		T72	1		T35	162
alert_integrity_fail	alert[0x30]	5522	1			T33	3		T40	301		T22	137
alert_integrity_fail	alert[0x31]	4225	1			T33	17		T40	44		T22	183
alert_integrity_fail	alert[0x32]	7184	1			T25	2		T22	236		T65	4
alert_integrity_fail	alert[0x33]	3016	1			T40	239		T30	3		T322	674
alert_integrity_fail	alert[0x34]	10625	1			T25	1		T40	57		T22	220
alert_integrity_fail	alert[0x35]	6030	1			T4	63		T40	47		T24	3
alert_integrity_fail	alert[0x36]	7659	1			T33	22		T40	31		T22	93
alert_integrity_fail	alert[0x37]	5871	1			T40	603		T99	6		T17	3
alert_integrity_fail	alert[0x38]	7446	1			T11	3		T25	1		T40	79
alert_integrity_fail	alert[0x39]	6519	1			T33	586		T72	1		T35	5
alert_integrity_fail	alert[0x3a]	8051	1			T4	27		T22	80		T30	2
alert_integrity_fail	alert[0x3b]	5505	1			T27	1		T24	1		T322	15
alert_integrity_fail	alert[0x3c]	3887	1			T33	183		T22	88		T56	11
alert_integrity_fail	alert[0x3d]	2352	1			T40	5		T56	79		T72	2
alert_integrity_fail	alert[0x3e]	2112	1			T56	33		T17	8		T24	2
alert_integrity_fail	alert[0x3f]	5655	1			T33	114		T40	9		T99	3
alert_integrity_fail	alert[0x40]	5134	1			T33	86		T56	21		T24	43
alert_ping_fail	alert[0x0]	15	1			T55	1		T124	1		T289	1
alert_ping_fail	alert[0x1]	14	1			T54	1		T75	1		T125	2
alert_ping_fail	alert[0x2]	3	1			T125	1		T323	1		T324	1
alert_ping_fail	alert[0x3]	11	1			T71	1		T76	1		T325	1
alert_ping_fail	alert[0x4]	7	1			T126	1		T325	1		T326	1
alert_ping_fail	alert[0x5]	14	1			T54	1		T69	1		T124	1
alert_ping_fail	alert[0x6]	7	1			T55	1		T327	1		T325	1
alert_ping_fail	alert[0x7]	11	1			T124	2		T76	1		T328	1
alert_ping_fail	alert[0x8]	17	1			T124	1		T126	1		T76	1
alert_ping_fail	alert[0x9]	9	1			T289	1		T329	1		T330	3
alert_ping_fail	alert[0xa]	16	1			T8	1		T55	1		T71	1
alert_ping_fail	alert[0xb]	13	1			T75	1		T125	1		T331	1
alert_ping_fail	alert[0xc]	12	1			T55	2		T124	1		T332	1
alert_ping_fail	alert[0xd]	10	1			T124	1		T76	1		T333	1
alert_ping_fail	alert[0xe]	12	1			T54	1		T71	1		T126	1
alert_ping_fail	alert[0xf]	5	1			T1	1		T69	1		T325	1
alert_ping_fail	alert[0x10]	11	1			T69	1		T124	1		T334	1
alert_ping_fail	alert[0x11]	6	1			T75	1		T335	1		T336	1
alert_ping_fail	alert[0x12]	12	1			T126	1		T76	1		T331	1
alert_ping_fail	alert[0x13]	12	1			T68	2		T125	1		T76	1
alert_ping_fail	alert[0x14]	18	1			T55	1		T321	1		T337	1
alert_ping_fail	alert[0x15]	9	1			T69	2		T335	2		T338	1
alert_ping_fail	alert[0x16]	16	1			T71	1		T117	1		T339	3
alert_ping_fail	alert[0x17]	9	1			T124	1		T76	1		T338	1
alert_ping_fail	alert[0x18]	14	1			T8	2		T75	1		T124	1
alert_ping_fail	alert[0x19]	8	1			T71	1		T76	1		T331	1
alert_ping_fail	alert[0x1a]	18	1			T1	1		T55	1		T69	1
alert_ping_fail	alert[0x1b]	13	1			T253	1		T70	2		T117	1
alert_ping_fail	alert[0x1c]	17	1			T75	1		T253	1		T117	1
alert_ping_fail	alert[0x1d]	4	1			T339	1		T340	1		T341	1
alert_ping_fail	alert[0x1e]	9	1			T71	2		T339	1		T335	1
alert_ping_fail	alert[0x1f]	18	1			T55	1		T69	2		T76	2
alert_ping_fail	alert[0x20]	7	1			T69	1		T325	1		T326	1
alert_ping_fail	alert[0x21]	7	1			T55	1		T69	1		T331	1
alert_ping_fail	alert[0x22]	20	1			T69	1		T125	1		T328	1
alert_ping_fail	alert[0x23]	5	1			T325	1		T342	1		T343	1
alert_ping_fail	alert[0x24]	6	1			T55	1		T70	1		T331	1
alert_ping_fail	alert[0x25]	5	1			T253	1		T344	1		T345	1
alert_ping_fail	alert[0x26]	12	1			T69	1		T75	1		T124	1
alert_ping_fail	alert[0x27]	10	1			T55	2		T331	1		T337	1
alert_ping_fail	alert[0x28]	15	1			T1	1		T124	1		T76	2
alert_ping_fail	alert[0x29]	6	1			T333	1		T340	1		T346	1
alert_ping_fail	alert[0x2a]	14	1			T124	1		T76	1		T338	1
alert_ping_fail	alert[0x2b]	10	1			T55	1		T126	1		T334	1
alert_ping_fail	alert[0x2c]	16	1			T71	1		T76	1		T347	1
alert_ping_fail	alert[0x2d]	15	1			T125	1		T337	1		T344	2
alert_ping_fail	alert[0x2e]	15	1			T1	1		T71	1		T69	2
alert_ping_fail	alert[0x2f]	12	1			T124	1		T337	1		T348	1
alert_ping_fail	alert[0x30]	13	1			T71	1		T124	1		T337	1
alert_ping_fail	alert[0x31]	5	1			T69	1		T289	1		T344	1
alert_ping_fail	alert[0x32]	16	1			T55	1		T71	1		T69	2
alert_ping_fail	alert[0x33]	10	1			T54	1		T344	1		T345	1
alert_ping_fail	alert[0x34]	4	1			T71	1		T335	2		T336	1
alert_ping_fail	alert[0x35]	14	1			T1	1		T75	2		T124	1
alert_ping_fail	alert[0x36]	12	1			T76	1		T325	1		T338	2
alert_ping_fail	alert[0x37]	16	1			T69	1		T75	1		T126	1
alert_ping_fail	alert[0x38]	11	1			T126	1		T253	1		T337	1
alert_ping_fail	alert[0x39]	7	1			T76	3		T330	1		T346	1
alert_ping_fail	alert[0x3a]	10	1			T325	1		T339	1		T334	2
alert_ping_fail	alert[0x3b]	6	1			T55	1		T338	1		T329	1
alert_ping_fail	alert[0x3c]	5	1			T124	1		T349	1		T350	1
alert_ping_fail	alert[0x3d]	5	1			T55	1		T351	1		T352	1
alert_ping_fail	alert[0x3e]	10	1			T54	1		T126	2		T76	1
alert_ping_fail	alert[0x3f]	4	1			T346	1		T336	1		T353	1
alert_ping_fail	alert[0x40]	5	1			T338	1		T340	1		T352	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	106477	1			T25	22		T4	232		T65	173
alert_integrity_fail	class_i[0x1]	80693	1			T20	1		T33	7		T11	44
alert_integrity_fail	class_i[0x2]	123631	1			T25	28		T22	15654		T56	5
alert_integrity_fail	class_i[0x3]	146804	1			T33	5830		T40	16723		T56	1835
alert_ping_fail	class_i[0x0]	210	1			T8	3		T55	16		T71	4
alert_ping_fail	class_i[0x1]	127	1			T54	1		T71	3		T68	3
alert_ping_fail	class_i[0x2]	199	1			T1	2		T54	4		T71	3
alert_ping_fail	class_i[0x3]	162	1			T1	3		T71	2		T69	2