Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.68	99.86	98.48	89.99	91.94	99.81	97.13	99.52

Total test records in report: 829

T775	/workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.393468690	Apr 30 02:20:27 PM PDT 24	Apr 30 02:20:34 PM PDT 24	37047702 ps
T776	/workspace/coverage/cover_reg_top/33.alert_handler_intr_test.2424712672	Apr 30 02:20:52 PM PDT 24	Apr 30 02:20:54 PM PDT 24	27146363 ps
T172	/workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.1671751215	Apr 30 02:20:49 PM PDT 24	Apr 30 02:31:51 PM PDT 24	18665356190 ps
T777	/workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.1304064959	Apr 30 02:20:41 PM PDT 24	Apr 30 02:20:50 PM PDT 24	424369705 ps
T778	/workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.3113553161	Apr 30 02:20:46 PM PDT 24	Apr 30 02:21:29 PM PDT 24	642528174 ps
T779	/workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.3189068630	Apr 30 02:20:42 PM PDT 24	Apr 30 02:20:46 PM PDT 24	69987353 ps
T780	/workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.3491984848	Apr 30 02:20:27 PM PDT 24	Apr 30 02:20:33 PM PDT 24	292242544 ps
T781	/workspace/coverage/cover_reg_top/19.alert_handler_intr_test.3113505143	Apr 30 02:20:44 PM PDT 24	Apr 30 02:20:45 PM PDT 24	9993773 ps
T782	/workspace/coverage/cover_reg_top/31.alert_handler_intr_test.3335747588	Apr 30 02:20:49 PM PDT 24	Apr 30 02:20:51 PM PDT 24	24720260 ps
T783	/workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.3813497128	Apr 30 02:20:18 PM PDT 24	Apr 30 02:20:34 PM PDT 24	327568315 ps
T784	/workspace/coverage/cover_reg_top/10.alert_handler_intr_test.1383914024	Apr 30 02:20:40 PM PDT 24	Apr 30 02:20:42 PM PDT 24	9640385 ps
T785	/workspace/coverage/cover_reg_top/18.alert_handler_intr_test.2671661730	Apr 30 02:20:48 PM PDT 24	Apr 30 02:20:51 PM PDT 24	28539823 ps
T193	/workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.104675026	Apr 30 02:20:28 PM PDT 24	Apr 30 02:21:10 PM PDT 24	1267255672 ps
T786	/workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.2966478580	Apr 30 02:20:27 PM PDT 24	Apr 30 02:20:49 PM PDT 24	173759631 ps
T787	/workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.1081344813	Apr 30 02:20:18 PM PDT 24	Apr 30 02:24:15 PM PDT 24	3948619092 ps
T788	/workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.2643379080	Apr 30 02:20:36 PM PDT 24	Apr 30 02:20:42 PM PDT 24	50271698 ps
T789	/workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.891894194	Apr 30 02:20:50 PM PDT 24	Apr 30 02:21:16 PM PDT 24	188013377 ps
T790	/workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.974135413	Apr 30 02:20:10 PM PDT 24	Apr 30 02:20:15 PM PDT 24	116964094 ps
T791	/workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.3401228085	Apr 30 02:20:43 PM PDT 24	Apr 30 02:20:48 PM PDT 24	30339176 ps
T792	/workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.392740221	Apr 30 02:20:23 PM PDT 24	Apr 30 02:20:34 PM PDT 24	1212926216 ps
T154	/workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.1817783757	Apr 30 02:20:19 PM PDT 24	Apr 30 02:26:12 PM PDT 24	16242411885 ps
T793	/workspace/coverage/cover_reg_top/36.alert_handler_intr_test.1987305502	Apr 30 02:20:51 PM PDT 24	Apr 30 02:20:53 PM PDT 24	8009541 ps
T794	/workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1897133617	Apr 30 02:20:17 PM PDT 24	Apr 30 02:20:39 PM PDT 24	1032776363 ps
T795	/workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.3882109125	Apr 30 02:20:37 PM PDT 24	Apr 30 02:20:57 PM PDT 24	575581363 ps
T796	/workspace/coverage/cover_reg_top/3.alert_handler_intr_test.2870993681	Apr 30 02:20:24 PM PDT 24	Apr 30 02:20:26 PM PDT 24	6690430 ps
T797	/workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.1961243	Apr 30 02:20:38 PM PDT 24	Apr 30 02:20:51 PM PDT 24	725312275 ps
T798	/workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.1729106394	Apr 30 02:20:38 PM PDT 24	Apr 30 02:21:01 PM PDT 24	1031733064 ps
T799	/workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.4092579223	Apr 30 02:20:12 PM PDT 24	Apr 30 02:20:36 PM PDT 24	682326975 ps
T170	/workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.3394323511	Apr 30 02:20:18 PM PDT 24	Apr 30 02:23:53 PM PDT 24	1584851630 ps
T171	/workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.2953129009	Apr 30 02:20:46 PM PDT 24	Apr 30 02:24:01 PM PDT 24	15424264625 ps
T58	/workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.1322591393	Apr 30 02:20:27 PM PDT 24	Apr 30 02:28:41 PM PDT 24	24016555456 ps
T191	/workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.2365113996	Apr 30 02:20:12 PM PDT 24	Apr 30 02:20:48 PM PDT 24	938260189 ps
T800	/workspace/coverage/cover_reg_top/46.alert_handler_intr_test.3968760542	Apr 30 02:20:53 PM PDT 24	Apr 30 02:20:55 PM PDT 24	6365045 ps
T383	/workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.3554220511	Apr 30 02:20:37 PM PDT 24	Apr 30 02:29:35 PM PDT 24	28204315014 ps
T801	/workspace/coverage/cover_reg_top/32.alert_handler_intr_test.638810737	Apr 30 02:20:52 PM PDT 24	Apr 30 02:20:55 PM PDT 24	24900038 ps
T802	/workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.3078375644	Apr 30 02:20:25 PM PDT 24	Apr 30 02:20:35 PM PDT 24	104063449 ps
T803	/workspace/coverage/cover_reg_top/11.alert_handler_intr_test.2485472925	Apr 30 02:20:40 PM PDT 24	Apr 30 02:20:42 PM PDT 24	14869780 ps
T804	/workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.298872351	Apr 30 02:20:11 PM PDT 24	Apr 30 02:20:22 PM PDT 24	247429027 ps
T805	/workspace/coverage/cover_reg_top/13.alert_handler_intr_test.2994690611	Apr 30 02:20:49 PM PDT 24	Apr 30 02:20:52 PM PDT 24	10546783 ps
T806	/workspace/coverage/cover_reg_top/28.alert_handler_intr_test.558133738	Apr 30 02:20:51 PM PDT 24	Apr 30 02:20:53 PM PDT 24	6312901 ps
T807	/workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.1295287146	Apr 30 02:20:48 PM PDT 24	Apr 30 02:20:54 PM PDT 24	75715162 ps
T808	/workspace/coverage/cover_reg_top/5.alert_handler_intr_test.406833719	Apr 30 02:20:30 PM PDT 24	Apr 30 02:20:31 PM PDT 24	20342849 ps
T167	/workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.37270940	Apr 30 02:20:47 PM PDT 24	Apr 30 02:22:58 PM PDT 24	8486304260 ps
T190	/workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.2602902663	Apr 30 02:20:35 PM PDT 24	Apr 30 02:20:39 PM PDT 24	92624133 ps
T809	/workspace/coverage/cover_reg_top/30.alert_handler_intr_test.285212220	Apr 30 02:20:51 PM PDT 24	Apr 30 02:20:53 PM PDT 24	6800433 ps
T810	/workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.1776078712	Apr 30 02:20:25 PM PDT 24	Apr 30 02:21:45 PM PDT 24	1087098888 ps
T811	/workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.145973237	Apr 30 02:20:19 PM PDT 24	Apr 30 02:23:23 PM PDT 24	4367958271 ps
T812	/workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.1668334550	Apr 30 02:20:18 PM PDT 24	Apr 30 02:20:25 PM PDT 24	144702580 ps
T184	/workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.2887791016	Apr 30 02:20:49 PM PDT 24	Apr 30 02:21:26 PM PDT 24	1173746674 ps
T813	/workspace/coverage/cover_reg_top/34.alert_handler_intr_test.2685979221	Apr 30 02:20:50 PM PDT 24	Apr 30 02:20:51 PM PDT 24	7483632 ps
T814	/workspace/coverage/cover_reg_top/15.alert_handler_intr_test.233335182	Apr 30 02:20:45 PM PDT 24	Apr 30 02:20:47 PM PDT 24	7258130 ps
T59	/workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.4019689947	Apr 30 02:20:43 PM PDT 24	Apr 30 02:23:49 PM PDT 24	6273787207 ps
T815	/workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.1307241601	Apr 30 02:20:45 PM PDT 24	Apr 30 02:21:10 PM PDT 24	171877303 ps
T173	/workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.2275879325	Apr 30 02:20:27 PM PDT 24	Apr 30 02:22:05 PM PDT 24	732339014 ps
T187	/workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.2958484354	Apr 30 02:20:47 PM PDT 24	Apr 30 02:20:53 PM PDT 24	93231968 ps
T816	/workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.1130872112	Apr 30 02:20:47 PM PDT 24	Apr 30 02:20:54 PM PDT 24	38604001 ps
T817	/workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.897442149	Apr 30 02:20:45 PM PDT 24	Apr 30 02:20:58 PM PDT 24	175608297 ps
T818	/workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.2227946966	Apr 30 02:20:20 PM PDT 24	Apr 30 02:21:43 PM PDT 24	572330469 ps
T175	/workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.3897453381	Apr 30 02:20:18 PM PDT 24	Apr 30 02:28:00 PM PDT 24	12698470547 ps
T819	/workspace/coverage/cover_reg_top/41.alert_handler_intr_test.2673158915	Apr 30 02:20:52 PM PDT 24	Apr 30 02:20:54 PM PDT 24	11022198 ps
T176	/workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.3024489159	Apr 30 02:20:35 PM PDT 24	Apr 30 02:28:01 PM PDT 24	6427223282 ps
T820	/workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.2338755918	Apr 30 02:20:19 PM PDT 24	Apr 30 02:27:18 PM PDT 24	11444586795 ps
T821	/workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.4036787327	Apr 30 02:20:26 PM PDT 24	Apr 30 02:20:49 PM PDT 24	1909717118 ps
T822	/workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.1716669868	Apr 30 02:20:19 PM PDT 24	Apr 30 02:20:24 PM PDT 24	107708480 ps
T823	/workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.2264840691	Apr 30 02:20:35 PM PDT 24	Apr 30 02:20:41 PM PDT 24	237522866 ps
T155	/workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.2654259068	Apr 30 02:20:48 PM PDT 24	Apr 30 02:33:54 PM PDT 24	5570201533 ps
T824	/workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.1949089804	Apr 30 02:20:48 PM PDT 24	Apr 30 02:20:54 PM PDT 24	95590043 ps
T199	/workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.799188588	Apr 30 02:20:47 PM PDT 24	Apr 30 02:20:50 PM PDT 24	57131866 ps
T825	/workspace/coverage/cover_reg_top/47.alert_handler_intr_test.2444066800	Apr 30 02:20:52 PM PDT 24	Apr 30 02:20:54 PM PDT 24	8089161 ps
T186	/workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.3937761136	Apr 30 02:20:27 PM PDT 24	Apr 30 02:20:31 PM PDT 24	102176202 ps
T198	/workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.4089923265	Apr 30 02:20:45 PM PDT 24	Apr 30 02:20:49 PM PDT 24	168268263 ps
T174	/workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.3191083486	Apr 30 02:20:46 PM PDT 24	Apr 30 02:26:32 PM PDT 24	4790199928 ps
T188	/workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.2780489899	Apr 30 02:20:46 PM PDT 24	Apr 30 02:20:49 PM PDT 24	95964947 ps
T185	/workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1703686163	Apr 30 02:20:42 PM PDT 24	Apr 30 02:20:44 PM PDT 24	64687966 ps
T826	/workspace/coverage/cover_reg_top/42.alert_handler_intr_test.1847876155	Apr 30 02:20:51 PM PDT 24	Apr 30 02:20:53 PM PDT 24	16675922 ps
T827	/workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.3657823704	Apr 30 02:20:18 PM PDT 24	Apr 30 02:20:28 PM PDT 24	838266767 ps
T828	/workspace/coverage/cover_reg_top/38.alert_handler_intr_test.191651578	Apr 30 02:20:52 PM PDT 24	Apr 30 02:20:55 PM PDT 24	7604093 ps
T829	/workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.3318690703	Apr 30 02:20:49 PM PDT 24	Apr 30 02:21:01 PM PDT 24	248611804 ps
T197	/workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.1617166093	Apr 30 02:20:38 PM PDT 24	Apr 30 02:20:41 PM PDT 24	27270557 ps

Test location	/workspace/coverage/default/40.alert_handler_lpg_stub_clk.3951222712
Short name	T7
Test name
Test status
Simulation time	285650840175 ps
CPU time	2975.18 seconds
Started	Apr 30 02:23:30 PM PDT 24
Finished	Apr 30 03:13:06 PM PDT 24
Peak memory	289216 kb
Host	smart-b4ed9936-def8-4603-a0fc-2fbba126f121
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3951222712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.3951222712
Directory	/workspace/40.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.671688132
Short name	T4
Test name
Test status
Simulation time	531132353884 ps
CPU time	2257.32 seconds
Started	Apr 30 02:21:44 PM PDT 24
Finished	Apr 30 02:59:22 PM PDT 24
Peak memory	289804 kb
Host	smart-4e736570-3af0-48ae-a461-068c577027f0
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671688132 -assert nopostproc +UVM_TESTNAME=alert _handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.671688132
Directory	/workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.2961951478
Short name	T18
Test name
Test status
Simulation time	67170422291 ps
CPU time	1106.77 seconds
Started	Apr 30 02:21:50 PM PDT 24
Finished	Apr 30 02:40:17 PM PDT 24
Peak memory	283880 kb
Host	smart-0866fce7-9f48-4b57-baf8-a686bb8e0b28
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961951478 -assert nopostproc +UVM_TESTNAME=aler t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.2961951478
Directory	/workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/13.alert_handler_stress_all.1893175355
Short name	T65
Test name
Test status
Simulation time	70271659417 ps
CPU time	2326.11 seconds
Started	Apr 30 02:21:45 PM PDT 24
Finished	Apr 30 03:00:32 PM PDT 24
Peak memory	289104 kb
Host	smart-0ff88e70-2bc1-4f4c-9983-376c69e541cb
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893175355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha ndler_stress_all.1893175355
Directory	/workspace/13.alert_handler_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.3596652667
Short name	T177
Test name
Test status
Simulation time	2108220895 ps
CPU time	39.38 seconds
Started	Apr 30 02:20:28 PM PDT 24
Finished	Apr 30 02:21:08 PM PDT 24
Peak memory	239904 kb
Host	smart-5668eacb-2212-42be-9d48-9d573aa7c348
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3596652667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.3596652667
Directory	/workspace/8.alert_handler_tl_intg_err/latest

Test location	/workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.134340641
Short name	T35
Test name
Test status
Simulation time	113321188861 ps
CPU time	2214.27 seconds
Started	Apr 30 02:22:44 PM PDT 24
Finished	Apr 30 02:59:40 PM PDT 24
Peak memory	306176 kb
Host	smart-546d7a5c-66f5-4317-b646-34afdb026096
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134340641 -assert nopostproc +UVM_TESTNAME=alert _handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.134340641
Directory	/workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/2.alert_handler_lpg.1450907001
Short name	T8
Test name
Test status
Simulation time	47202770092 ps
CPU time	2597.12 seconds
Started	Apr 30 02:21:31 PM PDT 24
Finished	Apr 30 03:04:49 PM PDT 24
Peak memory	288720 kb
Host	smart-52c037ad-f0fe-431c-b83c-1f11a605759a
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1450907001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.1450907001
Directory	/workspace/2.alert_handler_lpg/latest

Test location	/workspace/coverage/default/25.alert_handler_stress_all.105492527
Short name	T43
Test name
Test status
Simulation time	45106482359 ps
CPU time	2471.1 seconds
Started	Apr 30 02:22:25 PM PDT 24
Finished	Apr 30 03:03:37 PM PDT 24
Peak memory	289340 kb
Host	smart-633d0971-1bbc-4934-a0cf-d4f609b1c974
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105492527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_han dler_stress_all.105492527
Directory	/workspace/25.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/46.alert_handler_stress_all.4132306640
Short name	T552
Test name
Test status
Simulation time	17115733458 ps
CPU time	1646.96 seconds
Started	Apr 30 02:24:04 PM PDT 24
Finished	Apr 30 02:51:31 PM PDT 24
Peak memory	297880 kb
Host	smart-893abe4a-ea5f-4833-8ef1-47c7c030f1ce
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132306640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha ndler_stress_all.4132306640
Directory	/workspace/46.alert_handler_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.391368962
Short name	T141
Test name
Test status
Simulation time	115430182809 ps
CPU time	1075.06 seconds
Started	Apr 30 02:20:20 PM PDT 24
Finished	Apr 30 02:38:16 PM PDT 24
Peak memory	265696 kb
Host	smart-96841a18-901d-44ba-b2b4-a117b681fa14
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391368962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM _TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.391368962
Directory	/workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.555159002
Short name	T30
Test name
Test status
Simulation time	256121747682 ps
CPU time	3057.36 seconds
Started	Apr 30 02:22:39 PM PDT 24
Finished	Apr 30 03:13:37 PM PDT 24
Peak memory	287992 kb
Host	smart-a490934a-de9a-4e5d-9b2e-2c49b6b7f5e9
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555159002 -assert nopostproc +UVM_TESTNAME=alert _handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.555159002
Directory	/workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.2388736392
Short name	T157
Test name
Test status
Simulation time	5535728214 ps
CPU time	412.29 seconds
Started	Apr 30 02:20:26 PM PDT 24
Finished	Apr 30 02:27:19 PM PDT 24
Peak memory	265656 kb
Host	smart-e08bf991-234b-4814-b717-fc1ddb342bb5
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2388736392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro rs.2388736392
Directory	/workspace/7.alert_handler_shadow_reg_errors/latest

Test location	/workspace/coverage/default/35.alert_handler_entropy.2069558455
Short name	T40
Test name
Test status
Simulation time	715125922882 ps
CPU time	2508.46 seconds
Started	Apr 30 02:23:00 PM PDT 24
Finished	Apr 30 03:04:49 PM PDT 24
Peak memory	289452 kb
Host	smart-81732635-674a-420f-8624-5410824b4b0d
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2069558455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.2069558455
Directory	/workspace/35.alert_handler_entropy/latest

Test location	/workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.1167585245
Short name	T151
Test name
Test status
Simulation time	8818467970 ps
CPU time	673.33 seconds
Started	Apr 30 02:20:47 PM PDT 24
Finished	Apr 30 02:32:01 PM PDT 24
Peak memory	272832 kb
Host	smart-38f12a9a-460c-4885-bc6b-615e1215e5ca
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167585245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.1167585245
Directory	/workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.1372349002
Short name	T166
Test name
Test status
Simulation time	13139425957 ps
CPU time	1043.94 seconds
Started	Apr 30 02:20:19 PM PDT 24
Finished	Apr 30 02:37:44 PM PDT 24
Peak memory	272784 kb
Host	smart-223a1316-64dc-41c8-bf55-6a343301a39d
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372349002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.1372349002
Directory	/workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/default/42.alert_handler_lpg_stub_clk.1528233691
Short name	T21
Test name
Test status
Simulation time	126129382678 ps
CPU time	3370.96 seconds
Started	Apr 30 02:23:34 PM PDT 24
Finished	Apr 30 03:19:45 PM PDT 24
Peak memory	289324 kb
Host	smart-697aa4c0-3e2f-4f24-a8ad-6cdb28f6107d
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1528233691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.1528233691
Directory	/workspace/42.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/11.alert_handler_lpg.2294412252
Short name	T68
Test name
Test status
Simulation time	36561815298 ps
CPU time	2001.82 seconds
Started	Apr 30 02:21:46 PM PDT 24
Finished	Apr 30 02:55:08 PM PDT 24
Peak memory	273376 kb
Host	smart-513707e5-50ae-47e7-aceb-5e8baae9e41c
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2294412252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.2294412252
Directory	/workspace/11.alert_handler_lpg/latest

Test location	/workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.2972227305
Short name	T83
Test name
Test status
Simulation time	66825109592 ps
CPU time	4546.92 seconds
Started	Apr 30 02:22:51 PM PDT 24
Finished	Apr 30 03:38:39 PM PDT 24
Peak memory	304752 kb
Host	smart-ffaef5c5-0e49-41ff-8e26-f3e6a4d88ef8
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972227305 -assert nopostproc +UVM_TESTNAME=aler t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.2972227305
Directory	/workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.971278851
Short name	T145
Test name
Test status
Simulation time	6786501496 ps
CPU time	242.73 seconds
Started	Apr 30 02:20:41 PM PDT 24
Finished	Apr 30 02:24:44 PM PDT 24
Peak memory	265708 kb
Host	smart-5f5b69de-c396-4cad-9991-805ebc95fda8
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=971278851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_error s.971278851
Directory	/workspace/9.alert_handler_shadow_reg_errors/latest

Test location	/workspace/coverage/default/6.alert_handler_ping_timeout.3388546619
Short name	T76
Test name
Test status
Simulation time	18827998602 ps
CPU time	584.86 seconds
Started	Apr 30 02:21:39 PM PDT 24
Finished	Apr 30 02:31:25 PM PDT 24
Peak memory	247024 kb
Host	smart-fb5e492f-9d11-4381-807a-fbe892009c12
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3388546619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.3388546619
Directory	/workspace/6.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/cover_reg_top/29.alert_handler_intr_test.1933831594
Short name	T372
Test name
Test status
Simulation time	8373260 ps
CPU time	1.55 seconds
Started	Apr 30 02:20:51 PM PDT 24
Finished	Apr 30 02:20:53 PM PDT 24
Peak memory	236312 kb
Host	smart-dd393e86-6ff3-47c8-9bac-cdddef22d8d1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1933831594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.1933831594
Directory	/workspace/29.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1916761560
Short name	T150
Test name
Test status
Simulation time	7207714511 ps
CPU time	851.4 seconds
Started	Apr 30 02:20:47 PM PDT 24
Finished	Apr 30 02:34:59 PM PDT 24
Peak memory	272096 kb
Host	smart-9a82b440-3629-49bb-b995-55bb248480bc
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916761560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.1916761560
Directory	/workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/default/31.alert_handler_stress_all.4273426853
Short name	T27
Test name
Test status
Simulation time	15148831186 ps
CPU time	424.72 seconds
Started	Apr 30 02:22:55 PM PDT 24
Finished	Apr 30 02:30:00 PM PDT 24
Peak memory	256804 kb
Host	smart-11835930-269d-4531-937a-0181f6e51a30
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273426853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha ndler_stress_all.4273426853
Directory	/workspace/31.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/43.alert_handler_lpg.1235115471
Short name	T117
Test name
Test status
Simulation time	25757530061 ps
CPU time	1470.51 seconds
Started	Apr 30 02:23:38 PM PDT 24
Finished	Apr 30 02:48:09 PM PDT 24
Peak memory	273332 kb
Host	smart-897f4d5a-a07d-46ba-bd91-a9796fbbe7be
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1235115471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.1235115471
Directory	/workspace/43.alert_handler_lpg/latest

Test location	/workspace/coverage/default/2.alert_handler_ping_timeout.94410332
Short name	T55
Test name
Test status
Simulation time	10799236988 ps
CPU time	470.55 seconds
Started	Apr 30 02:21:29 PM PDT 24
Finished	Apr 30 02:29:20 PM PDT 24
Peak memory	254868 kb
Host	smart-e315647b-c552-470c-9865-182dc1d455c7
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=94410332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.94410332
Directory	/workspace/2.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/0.alert_handler_stress_all.3208478177
Short name	T24
Test name
Test status
Simulation time	20725378590 ps
CPU time	1871.63 seconds
Started	Apr 30 02:21:31 PM PDT 24
Finished	Apr 30 02:52:43 PM PDT 24
Peak memory	305384 kb
Host	smart-91ce37f7-e433-4dbf-bc19-fa86302d2d83
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208478177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han dler_stress_all.3208478177
Directory	/workspace/0.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/46.alert_handler_lpg.1285395779
Short name	T364
Test name
Test status
Simulation time	37662919980 ps
CPU time	2138.11 seconds
Started	Apr 30 02:24:04 PM PDT 24
Finished	Apr 30 02:59:43 PM PDT 24
Peak memory	270216 kb
Host	smart-edbe81ca-685d-426a-a878-fef8e22f84ea
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1285395779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.1285395779
Directory	/workspace/46.alert_handler_lpg/latest

Test location	/workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.3394323511
Short name	T170
Test name
Test status
Simulation time	1584851630 ps
CPU time	214.94 seconds
Started	Apr 30 02:20:18 PM PDT 24
Finished	Apr 30 02:23:53 PM PDT 24
Peak memory	265596 kb
Host	smart-71b2ee83-b904-4ef3-bb34-7076f53a312e
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3394323511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro rs.3394323511
Directory	/workspace/3.alert_handler_shadow_reg_errors/latest

Test location	/workspace/coverage/default/25.alert_handler_ping_timeout.2751728606
Short name	T336
Test name
Test status
Simulation time	13156837711 ps
CPU time	567.25 seconds
Started	Apr 30 02:22:22 PM PDT 24
Finished	Apr 30 02:31:50 PM PDT 24
Peak memory	246884 kb
Host	smart-a1d305bb-3180-4fbb-b3fe-e5f9d44a822c
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2751728606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.2751728606
Directory	/workspace/25.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/19.alert_handler_stress_all.15871232
Short name	T273
Test name
Test status
Simulation time	50577633716 ps
CPU time	2710.85 seconds
Started	Apr 30 02:22:17 PM PDT 24
Finished	Apr 30 03:07:29 PM PDT 24
Peak memory	298532 kb
Host	smart-ba666285-fc62-47d3-9018-3cd7e82764b3
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15871232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_hand ler_stress_all.15871232
Directory	/workspace/19.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/19.alert_handler_entropy.545959900
Short name	T22
Test name
Test status
Simulation time	99801552083 ps
CPU time	1716.56 seconds
Started	Apr 30 02:22:15 PM PDT 24
Finished	Apr 30 02:50:52 PM PDT 24
Peak memory	289132 kb
Host	smart-55f79755-a355-44c2-8ff9-ecb29d96c454
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=545959900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.545959900
Directory	/workspace/19.alert_handler_entropy/latest

Test location	/workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.1671751215
Short name	T172
Test name
Test status
Simulation time	18665356190 ps
CPU time	660.48 seconds
Started	Apr 30 02:20:49 PM PDT 24
Finished	Apr 30 02:31:51 PM PDT 24
Peak memory	265776 kb
Host	smart-d55a7e35-5417-46fe-8a81-d70824ee606e
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671751215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.1671751215
Directory	/workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.2323398956
Short name	T213
Test name
Test status
Simulation time	37411664 ps
CPU time	7.33 seconds
Started	Apr 30 02:20:49 PM PDT 24
Finished	Apr 30 02:20:57 PM PDT 24
Peak memory	240592 kb
Host	smart-3ddacfd1-7370-43ec-bccc-8ae7cb35b1fb
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2323398956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.2323398956
Directory	/workspace/18.alert_handler_csr_rw/latest

Test location	/workspace/coverage/default/10.alert_handler_lpg.2911100943
Short name	T348
Test name
Test status
Simulation time	196038197655 ps
CPU time	2908.06 seconds
Started	Apr 30 02:22:03 PM PDT 24
Finished	Apr 30 03:10:31 PM PDT 24
Peak memory	286688 kb
Host	smart-b2c95fad-1e8b-4219-af99-218eb022a427
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2911100943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.2911100943
Directory	/workspace/10.alert_handler_lpg/latest

Test location	/workspace/coverage/default/11.alert_handler_ping_timeout.262056238
Short name	T324
Test name
Test status
Simulation time	120191912559 ps
CPU time	385.51 seconds
Started	Apr 30 02:21:48 PM PDT 24
Finished	Apr 30 02:28:14 PM PDT 24
Peak memory	247768 kb
Host	smart-b3038f2d-c857-46e3-bfc1-ee70bcd5dda3
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=262056238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.262056238
Directory	/workspace/11.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.2878646307
Short name	T118
Test name
Test status
Simulation time	130295321106 ps
CPU time	1947.21 seconds
Started	Apr 30 02:23:02 PM PDT 24
Finished	Apr 30 02:55:30 PM PDT 24
Peak memory	289860 kb
Host	smart-3a533f13-43f4-41b8-9d7f-877cb9a5c43f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878646307 -assert nopostproc +UVM_TESTNAME=aler t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.2878646307
Directory	/workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/33.alert_handler_stress_all.551158436
Short name	T92
Test name
Test status
Simulation time	22387525695 ps
CPU time	1808.16 seconds
Started	Apr 30 02:22:52 PM PDT 24
Finished	Apr 30 02:53:01 PM PDT 24
Peak memory	297916 kb
Host	smart-fb11b9a8-1f2f-41d8-876a-36fc27be0949
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551158436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_han dler_stress_all.551158436
Directory	/workspace/33.alert_handler_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/48.alert_handler_intr_test.2434067880
Short name	T181
Test name
Test status
Simulation time	31550402 ps
CPU time	1.31 seconds
Started	Apr 30 02:20:49 PM PDT 24
Finished	Apr 30 02:20:51 PM PDT 24
Peak memory	237052 kb
Host	smart-5b2c012d-94bb-4e97-80ea-b67690e076dd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2434067880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.2434067880
Directory	/workspace/48.alert_handler_intr_test/latest

Test location	/workspace/coverage/default/4.alert_handler_ping_timeout.1609491326
Short name	T346
Test name
Test status
Simulation time	13356358471 ps
CPU time	564.6 seconds
Started	Apr 30 02:21:38 PM PDT 24
Finished	Apr 30 02:31:04 PM PDT 24
Peak memory	254904 kb
Host	smart-b13ae3af-b531-40df-b128-ba17679cbeee
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1609491326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.1609491326
Directory	/workspace/4.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.1924394123
Short name	T121
Test name
Test status
Simulation time	75224049124 ps
CPU time	5639.39 seconds
Started	Apr 30 02:21:40 PM PDT 24
Finished	Apr 30 03:55:40 PM PDT 24
Peak memory	338248 kb
Host	smart-e55945dd-5cff-4ca0-9a9c-307cbce46664
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924394123 -assert nopostproc +UVM_TESTNAME=aler t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.1924394123
Directory	/workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.37270940
Short name	T167
Test name
Test status
Simulation time	8486304260 ps
CPU time	130.57 seconds
Started	Apr 30 02:20:47 PM PDT 24
Finished	Apr 30 02:22:58 PM PDT 24
Peak memory	265708 kb
Host	smart-b1189416-e083-4737-b5d7-e76a1651de85
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=37270940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_error s.37270940
Directory	/workspace/15.alert_handler_shadow_reg_errors/latest

Test location	/workspace/coverage/default/1.alert_handler_random_classes.1891987864
Short name	T2
Test name
Test status
Simulation time	504489479 ps
CPU time	17.68 seconds
Started	Apr 30 02:21:31 PM PDT 24
Finished	Apr 30 02:21:49 PM PDT 24
Peak memory	255692 kb
Host	smart-691e9705-568b-4c9d-bb1b-241f08ec74c8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18919 87864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.1891987864
Directory	/workspace/1.alert_handler_random_classes/latest

Test location	/workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.3191083486
Short name	T174
Test name
Test status
Simulation time	4790199928 ps
CPU time	346.17 seconds
Started	Apr 30 02:20:46 PM PDT 24
Finished	Apr 30 02:26:32 PM PDT 24
Peak memory	265736 kb
Host	smart-cca593d9-7046-4e4c-8a8a-a20621ab6c11
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3191083486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err ors.3191083486
Directory	/workspace/16.alert_handler_shadow_reg_errors/latest

Test location	/workspace/coverage/default/6.alert_handler_stress_all.2792810665
Short name	T46
Test name
Test status
Simulation time	46916457466 ps
CPU time	2619.36 seconds
Started	Apr 30 02:21:38 PM PDT 24
Finished	Apr 30 03:05:19 PM PDT 24
Peak memory	299288 kb
Host	smart-ccf0b485-b132-4629-a038-d7113c549ca9
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792810665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han dler_stress_all.2792810665
Directory	/workspace/6.alert_handler_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.1624220547
Short name	T162
Test name
Test status
Simulation time	8561878811 ps
CPU time	633 seconds
Started	Apr 30 02:20:45 PM PDT 24
Finished	Apr 30 02:31:18 PM PDT 24
Peak memory	269372 kb
Host	smart-4bd8e083-635b-446b-9b47-471612af0a75
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624220547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.1624220547
Directory	/workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/default/15.alert_handler_lpg.2912317143
Short name	T358
Test name
Test status
Simulation time	25048023958 ps
CPU time	1465.54 seconds
Started	Apr 30 02:21:58 PM PDT 24
Finished	Apr 30 02:46:25 PM PDT 24
Peak memory	272488 kb
Host	smart-d9988ada-ee1b-46d3-8413-47e62ee71920
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2912317143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.2912317143
Directory	/workspace/15.alert_handler_lpg/latest

Test location	/workspace/coverage/default/21.alert_handler_lpg.3873442922
Short name	T321
Test name
Test status
Simulation time	33358031831 ps
CPU time	1499.09 seconds
Started	Apr 30 02:21:59 PM PDT 24
Finished	Apr 30 02:46:59 PM PDT 24
Peak memory	273348 kb
Host	smart-67f0784e-6672-42a1-915f-4f4bc4e215b9
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3873442922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.3873442922
Directory	/workspace/21.alert_handler_lpg/latest

Test location	/workspace/coverage/default/49.alert_handler_stress_all.846453772
Short name	T48
Test name
Test status
Simulation time	24060653128 ps
CPU time	1110.57 seconds
Started	Apr 30 02:24:18 PM PDT 24
Finished	Apr 30 02:42:49 PM PDT 24
Peak memory	284912 kb
Host	smart-358df6f8-a4ba-44f0-8367-bc9c01dddd78
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846453772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_han dler_stress_all.846453772
Directory	/workspace/49.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/28.alert_handler_stress_all.2384128954
Short name	T80
Test name
Test status
Simulation time	61544975538 ps
CPU time	1518.91 seconds
Started	Apr 30 02:22:41 PM PDT 24
Finished	Apr 30 02:48:00 PM PDT 24
Peak memory	289288 kb
Host	smart-7e30dea0-bca9-4859-99e3-b27225708181
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384128954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha ndler_stress_all.2384128954
Directory	/workspace/28.alert_handler_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/6.alert_handler_intr_test.2429038035
Short name	T375
Test name
Test status
Simulation time	11605082 ps
CPU time	1.39 seconds
Started	Apr 30 02:20:27 PM PDT 24
Finished	Apr 30 02:20:29 PM PDT 24
Peak memory	235268 kb
Host	smart-c395d460-5408-4459-9e02-3d063539b724
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2429038035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.2429038035
Directory	/workspace/6.alert_handler_intr_test/latest

Test location	/workspace/coverage/default/20.alert_handler_stress_all.2511126895
Short name	T110
Test name
Test status
Simulation time	229255351065 ps
CPU time	3557.28 seconds
Started	Apr 30 02:22:05 PM PDT 24
Finished	Apr 30 03:21:23 PM PDT 24
Peak memory	305436 kb
Host	smart-ce59373a-a96d-496f-8e82-7fa7997b6e1e
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511126895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha ndler_stress_all.2511126895
Directory	/workspace/20.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/3.alert_handler_lpg.402924747
Short name	T320
Test name
Test status
Simulation time	38029366499 ps
CPU time	1112.33 seconds
Started	Apr 30 02:21:40 PM PDT 24
Finished	Apr 30 02:40:13 PM PDT 24
Peak memory	265168 kb
Host	smart-77391d9b-9bf3-4497-8628-d7e4d1f59dea
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=402924747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.402924747
Directory	/workspace/3.alert_handler_lpg/latest

Test location	/workspace/coverage/default/30.alert_handler_ping_timeout.3535210267
Short name	T330
Test name
Test status
Simulation time	34945462056 ps
CPU time	535.87 seconds
Started	Apr 30 02:22:55 PM PDT 24
Finished	Apr 30 02:31:51 PM PDT 24
Peak memory	247940 kb
Host	smart-5fa11ee6-4b45-482f-946b-cb5f3fbef102
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3535210267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.3535210267
Directory	/workspace/30.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/34.alert_handler_stress_all.2755959528
Short name	T283
Test name
Test status
Simulation time	31327579450 ps
CPU time	885.74 seconds
Started	Apr 30 02:22:59 PM PDT 24
Finished	Apr 30 02:37:45 PM PDT 24
Peak memory	273340 kb
Host	smart-a5297a8b-1f49-45d8-95ef-1abeadc02488
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755959528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha ndler_stress_all.2755959528
Directory	/workspace/34.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.4016031244
Short name	T267
Test name
Test status
Simulation time	36092276627 ps
CPU time	2331.56 seconds
Started	Apr 30 02:21:46 PM PDT 24
Finished	Apr 30 03:00:39 PM PDT 24
Peak memory	286024 kb
Host	smart-211940c5-cb81-4988-a360-f18f947f262c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016031244 -assert nopostproc +UVM_TESTNAME=aler t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.4016031244
Directory	/workspace/9.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.4223922846
Short name	T168
Test name
Test status
Simulation time	2906068896 ps
CPU time	180.53 seconds
Started	Apr 30 02:20:50 PM PDT 24
Finished	Apr 30 02:23:51 PM PDT 24
Peak memory	270716 kb
Host	smart-ef5b6102-3599-4281-b6d0-6f665a3916e8
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4223922846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err ors.4223922846
Directory	/workspace/13.alert_handler_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.1322591393
Short name	T58
Test name
Test status
Simulation time	24016555456 ps
CPU time	493.38 seconds
Started	Apr 30 02:20:27 PM PDT 24
Finished	Apr 30 02:28:41 PM PDT 24
Peak memory	265656 kb
Host	smart-05d79e75-62e8-4c59-9ffd-c3097f6abeb1
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322591393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.1322591393
Directory	/workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.2602902663
Short name	T190
Test name
Test status
Simulation time	92624133 ps
CPU time	3.96 seconds
Started	Apr 30 02:20:35 PM PDT 24
Finished	Apr 30 02:20:39 PM PDT 24
Peak memory	237596 kb
Host	smart-fb5171df-c572-4038-ad3d-1e4860f516d7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2602902663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.2602902663
Directory	/workspace/10.alert_handler_tl_intg_err/latest

Test location	/workspace/coverage/default/0.alert_handler_alert_accum_saturation.1284475728
Short name	T237
Test name
Test status
Simulation time	157261620 ps
CPU time	3.75 seconds
Started	Apr 30 02:21:29 PM PDT 24
Finished	Apr 30 02:21:33 PM PDT 24
Peak memory	248912 kb
Host	smart-7ba7ae04-06e0-4010-9136-86818c102539
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1284475728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.1284475728
Directory	/workspace/0.alert_handler_alert_accum_saturation/latest

Test location	/workspace/coverage/default/1.alert_handler_alert_accum_saturation.2971051924
Short name	T238
Test name
Test status
Simulation time	87868309 ps
CPU time	4.19 seconds
Started	Apr 30 02:21:29 PM PDT 24
Finished	Apr 30 02:21:34 PM PDT 24
Peak memory	248928 kb
Host	smart-d559b253-4575-4aab-bb03-fac60e5f68b6
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2971051924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.2971051924
Directory	/workspace/1.alert_handler_alert_accum_saturation/latest

Test location	/workspace/coverage/default/11.alert_handler_alert_accum_saturation.1580764709
Short name	T252
Test name
Test status
Simulation time	71107193 ps
CPU time	3.57 seconds
Started	Apr 30 02:21:51 PM PDT 24
Finished	Apr 30 02:21:55 PM PDT 24
Peak memory	248864 kb
Host	smart-afafdfc3-d855-4ded-9dc8-004d83c44ee3
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1580764709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.1580764709
Directory	/workspace/11.alert_handler_alert_accum_saturation/latest

Test location	/workspace/coverage/default/19.alert_handler_alert_accum_saturation.1162459020
Short name	T235
Test name
Test status
Simulation time	89033231 ps
CPU time	4.08 seconds
Started	Apr 30 02:22:03 PM PDT 24
Finished	Apr 30 02:22:08 PM PDT 24
Peak memory	248912 kb
Host	smart-21d22672-349d-4df7-8152-810032354e51
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1162459020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.1162459020
Directory	/workspace/19.alert_handler_alert_accum_saturation/latest

Test location	/workspace/coverage/default/0.alert_handler_ping_timeout.3739826380
Short name	T334
Test name
Test status
Simulation time	24041283650 ps
CPU time	523.21 seconds
Started	Apr 30 02:21:21 PM PDT 24
Finished	Apr 30 02:30:04 PM PDT 24
Peak memory	248832 kb
Host	smart-be09bfc9-7d7d-4cc3-b695-57af5d037881
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3739826380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.3739826380
Directory	/workspace/0.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/22.alert_handler_random_classes.53698239
Short name	T294
Test name
Test status
Simulation time	4653366884 ps
CPU time	46.82 seconds
Started	Apr 30 02:22:07 PM PDT 24
Finished	Apr 30 02:22:54 PM PDT 24
Peak memory	248736 kb
Host	smart-1e392258-9bec-4d73-9d20-a8658f04a674
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53698 239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.53698239
Directory	/workspace/22.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.3524366463
Short name	T269
Test name
Test status
Simulation time	56757176216 ps
CPU time	1507.32 seconds
Started	Apr 30 02:22:24 PM PDT 24
Finished	Apr 30 02:47:32 PM PDT 24
Peak memory	289468 kb
Host	smart-c68f82b2-3512-4e1e-b5cb-3bc345db2ae6
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524366463 -assert nopostproc +UVM_TESTNAME=aler t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.3524366463
Directory	/workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/4.alert_handler_lpg.118394328
Short name	T681
Test name
Test status
Simulation time	65218215355 ps
CPU time	1946.06 seconds
Started	Apr 30 02:21:39 PM PDT 24
Finished	Apr 30 02:54:06 PM PDT 24
Peak memory	281524 kb
Host	smart-c65df3c5-3c4d-4458-89f7-eebfab4063b4
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=118394328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.118394328
Directory	/workspace/4.alert_handler_lpg/latest

Test location	/workspace/coverage/default/17.alert_handler_stress_all.33238408
Short name	T138
Test name
Test status
Simulation time	29453640248 ps
CPU time	1335.99 seconds
Started	Apr 30 02:22:08 PM PDT 24
Finished	Apr 30 02:44:24 PM PDT 24
Peak memory	302252 kb
Host	smart-7c961200-96c4-4afc-8941-64b25d54a08e
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33238408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_hand ler_stress_all.33238408
Directory	/workspace/17.alert_handler_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.3817312291
Short name	T164
Test name
Test status
Simulation time	28794878773 ps
CPU time	558.36 seconds
Started	Apr 30 02:20:29 PM PDT 24
Finished	Apr 30 02:29:48 PM PDT 24
Peak memory	265672 kb
Host	smart-9b73c73d-152c-4918-84ac-3b1c59fb4121
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817312291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.3817312291
Directory	/workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.2256281908
Short name	T143
Test name
Test status
Simulation time	2213352461 ps
CPU time	336.12 seconds
Started	Apr 30 02:20:38 PM PDT 24
Finished	Apr 30 02:26:14 PM PDT 24
Peak memory	265644 kb
Host	smart-0ff519a4-786c-4624-986a-e2f641a06b7c
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256281908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.2256281908
Directory	/workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/default/47.alert_handler_esc_intr_timeout.2937812684
Short name	T79
Test name
Test status
Simulation time	1669296300 ps
CPU time	50.7 seconds
Started	Apr 30 02:24:00 PM PDT 24
Finished	Apr 30 02:24:51 PM PDT 24
Peak memory	248660 kb
Host	smart-0b93b7ec-b1e1-4004-9791-c7ede7d04cee
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29378 12684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.2937812684
Directory	/workspace/47.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/0.alert_handler_smoke.2957120229
Short name	T302
Test name
Test status
Simulation time	2307549570 ps
CPU time	32.77 seconds
Started	Apr 30 02:21:22 PM PDT 24
Finished	Apr 30 02:21:55 PM PDT 24
Peak memory	248792 kb
Host	smart-0b68471f-a307-4a8e-8891-d931ba40ffc6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29571 20229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.2957120229
Directory	/workspace/0.alert_handler_smoke/latest

Test location	/workspace/coverage/default/10.alert_handler_stress_all.3599194787
Short name	T77
Test name
Test status
Simulation time	1012886090 ps
CPU time	58.38 seconds
Started	Apr 30 02:21:57 PM PDT 24
Finished	Apr 30 02:22:56 PM PDT 24
Peak memory	255904 kb
Host	smart-df674bc8-31ba-4b36-b8f6-1d5d22f7b680
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599194787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha ndler_stress_all.3599194787
Directory	/workspace/10.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/12.alert_handler_random_classes.4049996510
Short name	T317
Test name
Test status
Simulation time	153121481 ps
CPU time	6.62 seconds
Started	Apr 30 02:21:52 PM PDT 24
Finished	Apr 30 02:21:59 PM PDT 24
Peak memory	252764 kb
Host	smart-544a2907-9cf0-42f3-a9c7-eb0ee2ac8c65
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40499 96510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.4049996510
Directory	/workspace/12.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/17.alert_handler_ping_timeout.2886417906
Short name	T343
Test name
Test status
Simulation time	55519285719 ps
CPU time	400.33 seconds
Started	Apr 30 02:21:54 PM PDT 24
Finished	Apr 30 02:28:36 PM PDT 24
Peak memory	248692 kb
Host	smart-fd65c9e9-e1cd-45f0-a75e-4f85d3662ff4
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2886417906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.2886417906
Directory	/workspace/17.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/23.alert_handler_ping_timeout.4018423070
Short name	T352
Test name
Test status
Simulation time	89964972597 ps
CPU time	246.48 seconds
Started	Apr 30 02:22:17 PM PDT 24
Finished	Apr 30 02:26:24 PM PDT 24
Peak memory	247844 kb
Host	smart-42de5a9b-c0be-419b-8fc3-b9d8ed2ce2f2
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4018423070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.4018423070
Directory	/workspace/23.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/24.alert_handler_stress_all.283706348
Short name	T274
Test name
Test status
Simulation time	145584558929 ps
CPU time	1785.25 seconds
Started	Apr 30 02:22:24 PM PDT 24
Finished	Apr 30 02:52:10 PM PDT 24
Peak memory	289052 kb
Host	smart-0f87eab9-a629-41ce-92e9-b7906d376980
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283706348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_han dler_stress_all.283706348
Directory	/workspace/24.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/29.alert_handler_stress_all.2546968736
Short name	T298
Test name
Test status
Simulation time	102462150355 ps
CPU time	2888.66 seconds
Started	Apr 30 02:22:43 PM PDT 24
Finished	Apr 30 03:10:52 PM PDT 24
Peak memory	289160 kb
Host	smart-7da7cab2-b0de-4c73-8522-3ea6e029476b
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546968736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha ndler_stress_all.2546968736
Directory	/workspace/29.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/34.alert_handler_lpg.3262789683
Short name	T359
Test name
Test status
Simulation time	79741920906 ps
CPU time	1242.19 seconds
Started	Apr 30 02:22:59 PM PDT 24
Finished	Apr 30 02:43:42 PM PDT 24
Peak memory	272636 kb
Host	smart-8a1b7c85-967a-46ec-a1ad-2b6d0fa1bb09
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3262789683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.3262789683
Directory	/workspace/34.alert_handler_lpg/latest

Test location	/workspace/coverage/default/36.alert_handler_stress_all.76072034
Short name	T288
Test name
Test status
Simulation time	210466490436 ps
CPU time	1264.69 seconds
Started	Apr 30 02:23:04 PM PDT 24
Finished	Apr 30 02:44:09 PM PDT 24
Peak memory	289176 kb
Host	smart-786630f0-d0b0-4b8b-bf0d-a051655318a1
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76072034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_hand ler_stress_all.76072034
Directory	/workspace/36.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/4.alert_handler_sig_int_fail.3747531551
Short name	T23
Test name
Test status
Simulation time	109658035 ps
CPU time	8.11 seconds
Started	Apr 30 02:21:39 PM PDT 24
Finished	Apr 30 02:21:48 PM PDT 24
Peak memory	250676 kb
Host	smart-d3d68599-15b7-49bb-ae60-bb8f837d3bf6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37475 31551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.3747531551
Directory	/workspace/4.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/45.alert_handler_lpg_stub_clk.2806081603
Short name	T290
Test name
Test status
Simulation time	74595063199 ps
CPU time	1436.23 seconds
Started	Apr 30 02:23:47 PM PDT 24
Finished	Apr 30 02:47:44 PM PDT 24
Peak memory	273348 kb
Host	smart-7d47ae28-6d37-4031-9ee8-bc508d0ec275
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2806081603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.2806081603
Directory	/workspace/45.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/0.alert_handler_entropy.1638847410
Short name	T14
Test name
Test status
Simulation time	108858921614 ps
CPU time	3094.47 seconds
Started	Apr 30 02:21:28 PM PDT 24
Finished	Apr 30 03:13:03 PM PDT 24
Peak memory	289108 kb
Host	smart-8cffa1cd-4356-4695-a443-bdcb0926ae6e
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1638847410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.1638847410
Directory	/workspace/0.alert_handler_entropy/latest

Test location	/workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.3108311220
Short name	T142
Test name
Test status
Simulation time	3703394363 ps
CPU time	131.39 seconds
Started	Apr 30 02:20:19 PM PDT 24
Finished	Apr 30 02:22:31 PM PDT 24
Peak memory	265656 kb
Host	smart-81141e34-b34a-4d92-8214-7ecb52c7c7be
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3108311220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro rs.3108311220
Directory	/workspace/2.alert_handler_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.2919670618
Short name	T165
Test name
Test status
Simulation time	8856139500 ps
CPU time	177.24 seconds
Started	Apr 30 02:20:26 PM PDT 24
Finished	Apr 30 02:23:25 PM PDT 24
Peak memory	265660 kb
Host	smart-1c9549ee-1b22-4b53-972f-3db074da2ca5
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2919670618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro rs.2919670618
Directory	/workspace/4.alert_handler_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.3937761136
Short name	T186
Test name
Test status
Simulation time	102176202 ps
CPU time	3.07 seconds
Started	Apr 30 02:20:27 PM PDT 24
Finished	Apr 30 02:20:31 PM PDT 24
Peak memory	237172 kb
Host	smart-fee3c35c-5cc9-4b51-ba93-c023048a98c3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3937761136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.3937761136
Directory	/workspace/4.alert_handler_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.3648580682
Short name	T183
Test name
Test status
Simulation time	663078496 ps
CPU time	28.43 seconds
Started	Apr 30 02:20:26 PM PDT 24
Finished	Apr 30 02:20:56 PM PDT 24
Peak memory	239852 kb
Host	smart-37b6261d-eff3-4299-a488-c08b4015f41b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3648580682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.3648580682
Directory	/workspace/7.alert_handler_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.3079499556
Short name	T189
Test name
Test status
Simulation time	121418390 ps
CPU time	4.51 seconds
Started	Apr 30 02:20:18 PM PDT 24
Finished	Apr 30 02:20:24 PM PDT 24
Peak memory	237524 kb
Host	smart-a0e2c880-f17a-4f43-90c9-c12cc4b5d991
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3079499556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.3079499556
Directory	/workspace/2.alert_handler_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1703686163
Short name	T185
Test name
Test status
Simulation time	64687966 ps
CPU time	2.3 seconds
Started	Apr 30 02:20:42 PM PDT 24
Finished	Apr 30 02:20:44 PM PDT 24
Peak memory	237612 kb
Host	smart-50d1537e-3697-490a-a0b0-95303032dcac
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1703686163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.1703686163
Directory	/workspace/11.alert_handler_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.3020010445
Short name	T192
Test name
Test status
Simulation time	61641844 ps
CPU time	3.44 seconds
Started	Apr 30 02:20:36 PM PDT 24
Finished	Apr 30 02:20:40 PM PDT 24
Peak memory	236260 kb
Host	smart-191a340b-1ead-4c93-894f-99edafca31ab
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3020010445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.3020010445
Directory	/workspace/12.alert_handler_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.4019689947
Short name	T59
Test name
Test status
Simulation time	6273787207 ps
CPU time	185.57 seconds
Started	Apr 30 02:20:43 PM PDT 24
Finished	Apr 30 02:23:49 PM PDT 24
Peak memory	273440 kb
Host	smart-c4d298a9-b761-481a-831c-e3f5140156e2
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=4019689947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err ors.4019689947
Directory	/workspace/14.alert_handler_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.3316378949
Short name	T178
Test name
Test status
Simulation time	695511156 ps
CPU time	42.75 seconds
Started	Apr 30 02:20:43 PM PDT 24
Finished	Apr 30 02:21:26 PM PDT 24
Peak memory	237368 kb
Host	smart-8dd68c40-a57e-4cc4-9d20-eb36f2e67b3c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3316378949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.3316378949
Directory	/workspace/15.alert_handler_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.2958484354
Short name	T187
Test name
Test status
Simulation time	93231968 ps
CPU time	5.26 seconds
Started	Apr 30 02:20:47 PM PDT 24
Finished	Apr 30 02:20:53 PM PDT 24
Peak memory	237608 kb
Host	smart-b8b7a879-f7b5-4821-ae7b-a988f6665ffb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2958484354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.2958484354
Directory	/workspace/16.alert_handler_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.2887791016
Short name	T184
Test name
Test status
Simulation time	1173746674 ps
CPU time	36.41 seconds
Started	Apr 30 02:20:49 PM PDT 24
Finished	Apr 30 02:21:26 PM PDT 24
Peak memory	245516 kb
Host	smart-af9adb30-e150-45a9-a347-a819c23db6b6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2887791016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.2887791016
Directory	/workspace/19.alert_handler_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.104675026
Short name	T193
Test name
Test status
Simulation time	1267255672 ps
CPU time	40.74 seconds
Started	Apr 30 02:20:28 PM PDT 24
Finished	Apr 30 02:21:10 PM PDT 24
Peak memory	248936 kb
Host	smart-3277b8bd-bf56-487c-92e3-320316c382e3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=104675026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.104675026
Directory	/workspace/5.alert_handler_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.2365113996
Short name	T191
Test name
Test status
Simulation time	938260189 ps
CPU time	35.62 seconds
Started	Apr 30 02:20:12 PM PDT 24
Finished	Apr 30 02:20:48 PM PDT 24
Peak memory	240104 kb
Host	smart-4bf5c115-8feb-44d2-8574-2ffdc54faf91
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2365113996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.2365113996
Directory	/workspace/0.alert_handler_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.2792927511
Short name	T200
Test name
Test status
Simulation time	118466316 ps
CPU time	4.36 seconds
Started	Apr 30 02:20:20 PM PDT 24
Finished	Apr 30 02:20:25 PM PDT 24
Peak memory	237188 kb
Host	smart-c8216e73-b00a-4088-8393-dd01dc540cce
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2792927511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.2792927511
Directory	/workspace/1.alert_handler_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.799188588
Short name	T199
Test name
Test status
Simulation time	57131866 ps
CPU time	2.86 seconds
Started	Apr 30 02:20:47 PM PDT 24
Finished	Apr 30 02:20:50 PM PDT 24
Peak memory	236336 kb
Host	smart-8a3a932e-cddd-4412-b407-42d51bd9e7ad
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=799188588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.799188588
Directory	/workspace/13.alert_handler_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.2780489899
Short name	T188
Test name
Test status
Simulation time	95964947 ps
CPU time	2.52 seconds
Started	Apr 30 02:20:46 PM PDT 24
Finished	Apr 30 02:20:49 PM PDT 24
Peak memory	237560 kb
Host	smart-7c1d3784-b98e-4082-a766-56b0002e7750
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2780489899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.2780489899
Directory	/workspace/17.alert_handler_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.3534052700
Short name	T744
Test name
Test status
Simulation time	3750358851 ps
CPU time	74.52 seconds
Started	Apr 30 02:20:12 PM PDT 24
Finished	Apr 30 02:21:27 PM PDT 24
Peak memory	237220 kb
Host	smart-91ad5895-a967-4a2a-87e4-13a3b1c313c7
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3534052700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.3534052700
Directory	/workspace/0.alert_handler_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.96898448
Short name	T229
Test name
Test status
Simulation time	3043568702 ps
CPU time	205.83 seconds
Started	Apr 30 02:20:16 PM PDT 24
Finished	Apr 30 02:23:42 PM PDT 24
Peak memory	240784 kb
Host	smart-c1fa132f-ae8a-40d2-a79d-5b8adea8e8cb
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=96898448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.96898448
Directory	/workspace/0.alert_handler_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.298872351
Short name	T804
Test name
Test status
Simulation time	247429027 ps
CPU time	9.97 seconds
Started	Apr 30 02:20:11 PM PDT 24
Finished	Apr 30 02:20:22 PM PDT 24
Peak memory	240652 kb
Host	smart-cf2ae47f-899b-49a2-89fa-fe6fc4736c79
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=298872351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.298872351
Directory	/workspace/0.alert_handler_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.2203820554
Short name	T717
Test name
Test status
Simulation time	34222936 ps
CPU time	5.49 seconds
Started	Apr 30 02:20:11 PM PDT 24
Finished	Apr 30 02:20:17 PM PDT 24
Peak memory	257132 kb
Host	smart-4e2b525d-5e37-4bf1-aa28-17e28c1c98f4
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203820554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 0.alert_handler_csr_mem_rw_with_rand_reset.2203820554
Directory	/workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.974135413
Short name	T790
Test name
Test status
Simulation time	116964094 ps
CPU time	5.03 seconds
Started	Apr 30 02:20:10 PM PDT 24
Finished	Apr 30 02:20:15 PM PDT 24
Peak memory	240728 kb
Host	smart-eebf9aff-94ed-4b84-97d7-0996c251968c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=974135413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.974135413
Directory	/workspace/0.alert_handler_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.alert_handler_intr_test.888061167
Short name	T723
Test name
Test status
Simulation time	8725907 ps
CPU time	1.56 seconds
Started	Apr 30 02:20:11 PM PDT 24
Finished	Apr 30 02:20:13 PM PDT 24
Peak memory	236304 kb
Host	smart-cdfdb6c7-fefa-43bf-8cb1-90666b5a8117
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=888061167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.888061167
Directory	/workspace/0.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.2730191852
Short name	T761
Test name
Test status
Simulation time	171201213 ps
CPU time	15.27 seconds
Started	Apr 30 02:20:11 PM PDT 24
Finished	Apr 30 02:20:27 PM PDT 24
Peak memory	248932 kb
Host	smart-a3baf1bc-55b2-4ab5-acc8-e24d6be23fa5
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2730191852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out standing.2730191852
Directory	/workspace/0.alert_handler_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.3674227233
Short name	T146
Test name
Test status
Simulation time	4429897282 ps
CPU time	173 seconds
Started	Apr 30 02:20:15 PM PDT 24
Finished	Apr 30 02:23:08 PM PDT 24
Peak memory	265668 kb
Host	smart-6b9aeb21-8ec3-4ca9-9b8a-ca03ada23efc
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3674227233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro rs.3674227233
Directory	/workspace/0.alert_handler_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.2321139764
Short name	T153
Test name
Test status
Simulation time	17677831468 ps
CPU time	644.07 seconds
Started	Apr 30 02:20:09 PM PDT 24
Finished	Apr 30 02:30:54 PM PDT 24
Peak memory	265676 kb
Host	smart-b390558a-18ba-48cc-83bf-0f7fcf14b69c
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321139764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.2321139764
Directory	/workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.4092579223
Short name	T799
Test name
Test status
Simulation time	682326975 ps
CPU time	23.23 seconds
Started	Apr 30 02:20:12 PM PDT 24
Finished	Apr 30 02:20:36 PM PDT 24
Peak memory	248716 kb
Host	smart-2b34d5ec-1089-40ee-9e7a-9d4275306265
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4092579223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.4092579223
Directory	/workspace/0.alert_handler_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.2227946966
Short name	T818
Test name
Test status
Simulation time	572330469 ps
CPU time	82.71 seconds
Started	Apr 30 02:20:20 PM PDT 24
Finished	Apr 30 02:21:43 PM PDT 24
Peak memory	237116 kb
Host	smart-8c854753-1390-47c4-a42b-8f7b7d9ca1b8
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2227946966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.2227946966
Directory	/workspace/1.alert_handler_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.1081344813
Short name	T787
Test name
Test status
Simulation time	3948619092 ps
CPU time	237.09 seconds
Started	Apr 30 02:20:18 PM PDT 24
Finished	Apr 30 02:24:15 PM PDT 24
Peak memory	240660 kb
Host	smart-9d19a1da-62c7-4c7b-b3cb-7e09cf9e720a
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1081344813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.1081344813
Directory	/workspace/1.alert_handler_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.1668334550
Short name	T812
Test name
Test status
Simulation time	144702580 ps
CPU time	6.65 seconds
Started	Apr 30 02:20:18 PM PDT 24
Finished	Apr 30 02:20:25 PM PDT 24
Peak memory	240728 kb
Host	smart-37308795-067e-4c45-90ff-65f72536ec4e
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1668334550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.1668334550
Directory	/workspace/1.alert_handler_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.3657823704
Short name	T827
Test name
Test status
Simulation time	838266767 ps
CPU time	10.09 seconds
Started	Apr 30 02:20:18 PM PDT 24
Finished	Apr 30 02:20:28 PM PDT 24
Peak memory	240880 kb
Host	smart-a44ed577-e6f5-42b2-93ad-5f57fc43ce28
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657823704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 1.alert_handler_csr_mem_rw_with_rand_reset.3657823704
Directory	/workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.3902345162
Short name	T735
Test name
Test status
Simulation time	190175342 ps
CPU time	7.29 seconds
Started	Apr 30 02:20:20 PM PDT 24
Finished	Apr 30 02:20:28 PM PDT 24
Peak memory	236232 kb
Host	smart-1d7b85d7-3dcb-49ec-a3b7-c890ad576b39
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3902345162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.3902345162
Directory	/workspace/1.alert_handler_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.alert_handler_intr_test.423467912
Short name	T756
Test name
Test status
Simulation time	15590904 ps
CPU time	1.47 seconds
Started	Apr 30 02:20:18 PM PDT 24
Finished	Apr 30 02:20:20 PM PDT 24
Peak memory	236276 kb
Host	smart-548fd690-db50-422d-bd2a-ca88eb1228bb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=423467912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.423467912
Directory	/workspace/1.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1897133617
Short name	T794
Test name
Test status
Simulation time	1032776363 ps
CPU time	21.16 seconds
Started	Apr 30 02:20:17 PM PDT 24
Finished	Apr 30 02:20:39 PM PDT 24
Peak memory	244452 kb
Host	smart-a21e9b53-5f50-4e3d-ad18-c58c6f5fb945
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1897133617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out standing.1897133617
Directory	/workspace/1.alert_handler_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.1817783757
Short name	T154
Test name
Test status
Simulation time	16242411885 ps
CPU time	352.27 seconds
Started	Apr 30 02:20:19 PM PDT 24
Finished	Apr 30 02:26:12 PM PDT 24
Peak memory	265692 kb
Host	smart-1c4d5b15-c304-4acf-87f3-273bb636aabe
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1817783757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro rs.1817783757
Directory	/workspace/1.alert_handler_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.4251821312
Short name	T751
Test name
Test status
Simulation time	117127874 ps
CPU time	6.64 seconds
Started	Apr 30 02:20:23 PM PDT 24
Finished	Apr 30 02:20:30 PM PDT 24
Peak memory	249024 kb
Host	smart-99452503-0706-4b89-9f4b-b2c458d3ab99
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4251821312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.4251821312
Directory	/workspace/1.alert_handler_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.2643379080
Short name	T788
Test name
Test status
Simulation time	50271698 ps
CPU time	5.26 seconds
Started	Apr 30 02:20:36 PM PDT 24
Finished	Apr 30 02:20:42 PM PDT 24
Peak memory	239452 kb
Host	smart-9c99cfd9-0caa-4c6c-8b97-529f80ae827e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643379080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 10.alert_handler_csr_mem_rw_with_rand_reset.2643379080
Directory	/workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.1532788159
Short name	T382
Test name
Test status
Simulation time	178297493 ps
CPU time	9.1 seconds
Started	Apr 30 02:20:35 PM PDT 24
Finished	Apr 30 02:20:45 PM PDT 24
Peak memory	237212 kb
Host	smart-a1085973-aaab-49f0-a793-e200009f5b40
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1532788159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.1532788159
Directory	/workspace/10.alert_handler_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.alert_handler_intr_test.1383914024
Short name	T784
Test name
Test status
Simulation time	9640385 ps
CPU time	1.55 seconds
Started	Apr 30 02:20:40 PM PDT 24
Finished	Apr 30 02:20:42 PM PDT 24
Peak memory	237264 kb
Host	smart-25e14bc7-a217-4b13-8bf9-8ae7964672ba
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1383914024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.1383914024
Directory	/workspace/10.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.3067417498
Short name	T774
Test name
Test status
Simulation time	2211474233 ps
CPU time	40.1 seconds
Started	Apr 30 02:20:34 PM PDT 24
Finished	Apr 30 02:21:15 PM PDT 24
Peak memory	244504 kb
Host	smart-3a0a0fb7-701e-4d7e-9dd3-2dfab51f0490
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3067417498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou tstanding.3067417498
Directory	/workspace/10.alert_handler_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.3543927783
Short name	T152
Test name
Test status
Simulation time	1503869193 ps
CPU time	105.16 seconds
Started	Apr 30 02:20:35 PM PDT 24
Finished	Apr 30 02:22:21 PM PDT 24
Peak memory	265584 kb
Host	smart-299a76e5-1966-4f91-8c16-59311d892ac7
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3543927783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err ors.3543927783
Directory	/workspace/10.alert_handler_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.3554220511
Short name	T383
Test name
Test status
Simulation time	28204315014 ps
CPU time	537.38 seconds
Started	Apr 30 02:20:37 PM PDT 24
Finished	Apr 30 02:29:35 PM PDT 24
Peak memory	269420 kb
Host	smart-3f282333-62e3-460f-912d-4de512065076
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554220511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.3554220511
Directory	/workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.3647524023
Short name	T764
Test name
Test status
Simulation time	260730152 ps
CPU time	9.94 seconds
Started	Apr 30 02:20:34 PM PDT 24
Finished	Apr 30 02:20:45 PM PDT 24
Peak memory	248300 kb
Host	smart-bfc55113-d5df-4c6b-b0b6-30cf24c662a1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3647524023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.3647524023
Directory	/workspace/10.alert_handler_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.1961243
Short name	T797
Test name
Test status
Simulation time	725312275 ps
CPU time	12.66 seconds
Started	Apr 30 02:20:38 PM PDT 24
Finished	Apr 30 02:20:51 PM PDT 24
Peak memory	243876 kb
Host	smart-444c4cf6-345c-4c8d-a7fd-47be19b1dc39
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 11.alert_handler_csr_mem_rw_with_rand_reset.1961243
Directory	/workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.1039374404
Short name	T731
Test name
Test status
Simulation time	67693522 ps
CPU time	3.71 seconds
Started	Apr 30 02:20:36 PM PDT 24
Finished	Apr 30 02:20:41 PM PDT 24
Peak memory	236112 kb
Host	smart-1924cb4e-d2f3-4041-b020-36298c289552
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1039374404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.1039374404
Directory	/workspace/11.alert_handler_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.alert_handler_intr_test.2485472925
Short name	T803
Test name
Test status
Simulation time	14869780 ps
CPU time	1.49 seconds
Started	Apr 30 02:20:40 PM PDT 24
Finished	Apr 30 02:20:42 PM PDT 24
Peak memory	236372 kb
Host	smart-572ccdb7-d018-4888-8ae6-158d25dc5478
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2485472925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.2485472925
Directory	/workspace/11.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.1729106394
Short name	T798
Test name
Test status
Simulation time	1031733064 ps
CPU time	21.86 seconds
Started	Apr 30 02:20:38 PM PDT 24
Finished	Apr 30 02:21:01 PM PDT 24
Peak memory	248948 kb
Host	smart-53d5ae08-be3a-4460-b301-555212ece4a5
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1729106394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou tstanding.1729106394
Directory	/workspace/11.alert_handler_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.915738619
Short name	T149
Test name
Test status
Simulation time	916687975 ps
CPU time	93.96 seconds
Started	Apr 30 02:20:36 PM PDT 24
Finished	Apr 30 02:22:10 PM PDT 24
Peak memory	257364 kb
Host	smart-148d1f42-d4b9-4d23-8164-beeccf68f7eb
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=915738619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_erro rs.915738619
Directory	/workspace/11.alert_handler_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.934136518
Short name	T712
Test name
Test status
Simulation time	70233703 ps
CPU time	8.49 seconds
Started	Apr 30 02:20:36 PM PDT 24
Finished	Apr 30 02:20:45 PM PDT 24
Peak memory	248896 kb
Host	smart-8a8133f8-c105-4262-921d-07988ca3eb85
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=934136518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.934136518
Directory	/workspace/11.alert_handler_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.1295287146
Short name	T807
Test name
Test status
Simulation time	75715162 ps
CPU time	5.58 seconds
Started	Apr 30 02:20:48 PM PDT 24
Finished	Apr 30 02:20:54 PM PDT 24
Peak memory	238240 kb
Host	smart-46a87109-ac23-47d0-9a21-8235129dcc18
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295287146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 12.alert_handler_csr_mem_rw_with_rand_reset.1295287146
Directory	/workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.2264840691
Short name	T823
Test name
Test status
Simulation time	237522866 ps
CPU time	5.52 seconds
Started	Apr 30 02:20:35 PM PDT 24
Finished	Apr 30 02:20:41 PM PDT 24
Peak memory	237176 kb
Host	smart-739f515f-bb43-4adb-9489-7ed6ba26af39
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2264840691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.2264840691
Directory	/workspace/12.alert_handler_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.alert_handler_intr_test.3961320919
Short name	T182
Test name
Test status
Simulation time	9829153 ps
CPU time	1.56 seconds
Started	Apr 30 02:20:35 PM PDT 24
Finished	Apr 30 02:20:37 PM PDT 24
Peak memory	236320 kb
Host	smart-78e4d10b-c3f9-46c4-b8b0-20fc54334c97
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3961320919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.3961320919
Directory	/workspace/12.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.2751714956
Short name	T217
Test name
Test status
Simulation time	358906291 ps
CPU time	21.02 seconds
Started	Apr 30 02:20:49 PM PDT 24
Finished	Apr 30 02:21:10 PM PDT 24
Peak memory	245424 kb
Host	smart-1b4266d5-4fd6-456f-b2d9-260fbdb3361f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2751714956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou tstanding.2751714956
Directory	/workspace/12.alert_handler_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.667322371
Short name	T148
Test name
Test status
Simulation time	6838448415 ps
CPU time	212.06 seconds
Started	Apr 30 02:20:39 PM PDT 24
Finished	Apr 30 02:24:11 PM PDT 24
Peak memory	265476 kb
Host	smart-1665534a-1150-41ce-864b-c050d2fa8ebe
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=667322371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_erro rs.667322371
Directory	/workspace/12.alert_handler_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.2893204518
Short name	T160
Test name
Test status
Simulation time	14011263149 ps
CPU time	501.06 seconds
Started	Apr 30 02:20:35 PM PDT 24
Finished	Apr 30 02:28:57 PM PDT 24
Peak memory	270924 kb
Host	smart-d580cc81-631c-461e-9239-6ff017e69670
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893204518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.2893204518
Directory	/workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.3836983993
Short name	T716
Test name
Test status
Simulation time	728379085 ps
CPU time	12.8 seconds
Started	Apr 30 02:20:40 PM PDT 24
Finished	Apr 30 02:20:53 PM PDT 24
Peak memory	248604 kb
Host	smart-183e9c9f-5422-4ae9-a9ca-db7163a4e6c7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3836983993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.3836983993
Directory	/workspace/12.alert_handler_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.3757170391
Short name	T194
Test name
Test status
Simulation time	126649548 ps
CPU time	6.81 seconds
Started	Apr 30 02:20:48 PM PDT 24
Finished	Apr 30 02:20:56 PM PDT 24
Peak memory	248908 kb
Host	smart-0278bec5-0c4d-4382-bd85-cae46887835b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757170391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 13.alert_handler_csr_mem_rw_with_rand_reset.3757170391
Directory	/workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.1949089804
Short name	T824
Test name
Test status
Simulation time	95590043 ps
CPU time	4.72 seconds
Started	Apr 30 02:20:48 PM PDT 24
Finished	Apr 30 02:20:54 PM PDT 24
Peak memory	237184 kb
Host	smart-cc0f27c1-21cf-448a-a703-1fabe5a70bc6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1949089804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.1949089804
Directory	/workspace/13.alert_handler_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.alert_handler_intr_test.2994690611
Short name	T805
Test name
Test status
Simulation time	10546783 ps
CPU time	1.44 seconds
Started	Apr 30 02:20:49 PM PDT 24
Finished	Apr 30 02:20:52 PM PDT 24
Peak memory	236332 kb
Host	smart-d14e7494-3b6b-493c-b0d8-6a2459dd78c8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2994690611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.2994690611
Directory	/workspace/13.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.1307241601
Short name	T815
Test name
Test status
Simulation time	171877303 ps
CPU time	24.69 seconds
Started	Apr 30 02:20:45 PM PDT 24
Finished	Apr 30 02:21:10 PM PDT 24
Peak memory	248996 kb
Host	smart-74dc7021-eb43-46cb-aa10-bc463b85e5ce
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1307241601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou tstanding.1307241601
Directory	/workspace/13.alert_handler_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.2654259068
Short name	T155
Test name
Test status
Simulation time	5570201533 ps
CPU time	784.41 seconds
Started	Apr 30 02:20:48 PM PDT 24
Finished	Apr 30 02:33:54 PM PDT 24
Peak memory	272032 kb
Host	smart-13fb27c6-ff32-4030-8ce1-0c3c9f9cd80e
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654259068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.2654259068
Directory	/workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.3401228085
Short name	T791
Test name
Test status
Simulation time	30339176 ps
CPU time	4.82 seconds
Started	Apr 30 02:20:43 PM PDT 24
Finished	Apr 30 02:20:48 PM PDT 24
Peak memory	250712 kb
Host	smart-bc080d8b-abcf-4a8a-8fb0-b3014b84d7aa
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3401228085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.3401228085
Directory	/workspace/13.alert_handler_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.1130872112
Short name	T816
Test name
Test status
Simulation time	38604001 ps
CPU time	6.58 seconds
Started	Apr 30 02:20:47 PM PDT 24
Finished	Apr 30 02:20:54 PM PDT 24
Peak memory	257152 kb
Host	smart-63d77247-cff6-41bd-8e97-80b392e711cf
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130872112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 14.alert_handler_csr_mem_rw_with_rand_reset.1130872112
Directory	/workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.2452577133
Short name	T743
Test name
Test status
Simulation time	66747388 ps
CPU time	5.37 seconds
Started	Apr 30 02:20:46 PM PDT 24
Finished	Apr 30 02:20:52 PM PDT 24
Peak memory	237136 kb
Host	smart-3758c223-343a-4d9a-b54f-3fcb4eb3138f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2452577133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.2452577133
Directory	/workspace/14.alert_handler_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.alert_handler_intr_test.4277360050
Short name	T771
Test name
Test status
Simulation time	13904008 ps
CPU time	1.71 seconds
Started	Apr 30 02:20:46 PM PDT 24
Finished	Apr 30 02:20:48 PM PDT 24
Peak memory	237272 kb
Host	smart-472467ae-ccf7-48b4-a96d-3f65a60214e6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4277360050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.4277360050
Directory	/workspace/14.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.3113553161
Short name	T778
Test name
Test status
Simulation time	642528174 ps
CPU time	42.68 seconds
Started	Apr 30 02:20:46 PM PDT 24
Finished	Apr 30 02:21:29 PM PDT 24
Peak memory	245416 kb
Host	smart-d8738e60-9fef-48cc-a88e-bbd63dd7c559
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3113553161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou tstanding.3113553161
Directory	/workspace/14.alert_handler_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.3839102579
Short name	T732
Test name
Test status
Simulation time	802949278 ps
CPU time	13.11 seconds
Started	Apr 30 02:20:49 PM PDT 24
Finished	Apr 30 02:21:03 PM PDT 24
Peak memory	249200 kb
Host	smart-d5474af0-fc37-4744-a698-24c9d4d06e96
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3839102579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.3839102579
Directory	/workspace/14.alert_handler_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.110538836
Short name	T231
Test name
Test status
Simulation time	82183273 ps
CPU time	2.7 seconds
Started	Apr 30 02:20:47 PM PDT 24
Finished	Apr 30 02:20:50 PM PDT 24
Peak memory	237336 kb
Host	smart-d05bb80b-d936-4ffd-90f4-7350fce55f81
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=110538836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.110538836
Directory	/workspace/14.alert_handler_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.3821916930
Short name	T232
Test name
Test status
Simulation time	66789452 ps
CPU time	10.11 seconds
Started	Apr 30 02:20:44 PM PDT 24
Finished	Apr 30 02:20:54 PM PDT 24
Peak memory	253016 kb
Host	smart-8a9c0f2a-de51-4985-a6ff-d10fcae2af15
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821916930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 15.alert_handler_csr_mem_rw_with_rand_reset.3821916930
Directory	/workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.3318690703
Short name	T829
Test name
Test status
Simulation time	248611804 ps
CPU time	11.04 seconds
Started	Apr 30 02:20:49 PM PDT 24
Finished	Apr 30 02:21:01 PM PDT 24
Peak memory	240684 kb
Host	smart-77e2a04c-8232-4fef-af69-e2fd2c98495a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3318690703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.3318690703
Directory	/workspace/15.alert_handler_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.alert_handler_intr_test.233335182
Short name	T814
Test name
Test status
Simulation time	7258130 ps
CPU time	1.32 seconds
Started	Apr 30 02:20:45 PM PDT 24
Finished	Apr 30 02:20:47 PM PDT 24
Peak memory	237268 kb
Host	smart-16e1aaaf-48b7-4ce5-b9c7-de46272f8abf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=233335182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.233335182
Directory	/workspace/15.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.3774098035
Short name	T738
Test name
Test status
Simulation time	882267765 ps
CPU time	22.17 seconds
Started	Apr 30 02:20:43 PM PDT 24
Finished	Apr 30 02:21:06 PM PDT 24
Peak memory	244492 kb
Host	smart-9b1c7c3a-bb27-4b35-b90d-a1517811bbb5
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3774098035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou tstanding.3774098035
Directory	/workspace/15.alert_handler_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.3702507673
Short name	T755
Test name
Test status
Simulation time	253270037 ps
CPU time	18.6 seconds
Started	Apr 30 02:20:43 PM PDT 24
Finished	Apr 30 02:21:02 PM PDT 24
Peak memory	248200 kb
Host	smart-d5731cb5-bf8d-406c-b363-ee6b9b25a022
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3702507673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.3702507673
Directory	/workspace/15.alert_handler_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.764861402
Short name	T757
Test name
Test status
Simulation time	558321162 ps
CPU time	12.96 seconds
Started	Apr 30 02:20:45 PM PDT 24
Finished	Apr 30 02:20:59 PM PDT 24
Peak memory	251308 kb
Host	smart-fc3f431d-478d-49b3-9568-fc7c439b987d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764861402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 16.alert_handler_csr_mem_rw_with_rand_reset.764861402
Directory	/workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.3189068630
Short name	T779
Test name
Test status
Simulation time	69987353 ps
CPU time	3.83 seconds
Started	Apr 30 02:20:42 PM PDT 24
Finished	Apr 30 02:20:46 PM PDT 24
Peak memory	239856 kb
Host	smart-488fe4cd-279d-4212-9723-199c4b78ea80
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3189068630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.3189068630
Directory	/workspace/16.alert_handler_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.alert_handler_intr_test.1522214944
Short name	T772
Test name
Test status
Simulation time	26735811 ps
CPU time	1.48 seconds
Started	Apr 30 02:20:46 PM PDT 24
Finished	Apr 30 02:20:48 PM PDT 24
Peak memory	237260 kb
Host	smart-f7b442ce-b2bc-4a8e-a1f1-067bc6335dd8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1522214944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.1522214944
Directory	/workspace/16.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.897442149
Short name	T817
Test name
Test status
Simulation time	175608297 ps
CPU time	12.58 seconds
Started	Apr 30 02:20:45 PM PDT 24
Finished	Apr 30 02:20:58 PM PDT 24
Peak memory	245388 kb
Host	smart-485cdd7d-c9c5-4750-9ffc-1b9e9de58e34
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=897442149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_out standing.897442149
Directory	/workspace/16.alert_handler_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.3932381210
Short name	T57
Test name
Test status
Simulation time	3482742575 ps
CPU time	412.27 seconds
Started	Apr 30 02:20:49 PM PDT 24
Finished	Apr 30 02:27:42 PM PDT 24
Peak memory	265656 kb
Host	smart-42d57365-d717-4a17-a7f2-7ee6b5b770db
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932381210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.3932381210
Directory	/workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.2836624187
Short name	T752
Test name
Test status
Simulation time	73163753 ps
CPU time	10.1 seconds
Started	Apr 30 02:20:45 PM PDT 24
Finished	Apr 30 02:20:56 PM PDT 24
Peak memory	248980 kb
Host	smart-390f6e87-8a99-4db1-b642-594e8ba8dee5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2836624187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.2836624187
Directory	/workspace/16.alert_handler_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.319961926
Short name	T747
Test name
Test status
Simulation time	79728327 ps
CPU time	6.53 seconds
Started	Apr 30 02:20:48 PM PDT 24
Finished	Apr 30 02:20:56 PM PDT 24
Peak memory	255764 kb
Host	smart-3dfe2cc1-c3c2-48d6-81a1-7163999c291f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319961926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 17.alert_handler_csr_mem_rw_with_rand_reset.319961926
Directory	/workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.2737876499
Short name	T719
Test name
Test status
Simulation time	522729739 ps
CPU time	9.46 seconds
Started	Apr 30 02:20:48 PM PDT 24
Finished	Apr 30 02:20:59 PM PDT 24
Peak memory	240736 kb
Host	smart-41ec198c-fb01-4c34-9177-06de888d27cd
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2737876499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.2737876499
Directory	/workspace/17.alert_handler_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.alert_handler_intr_test.3291825370
Short name	T730
Test name
Test status
Simulation time	12297805 ps
CPU time	1.57 seconds
Started	Apr 30 02:20:46 PM PDT 24
Finished	Apr 30 02:20:48 PM PDT 24
Peak memory	237240 kb
Host	smart-5bb2d676-2237-400f-99bc-c26f391b9060
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3291825370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.3291825370
Directory	/workspace/17.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.891894194
Short name	T789
Test name
Test status
Simulation time	188013377 ps
CPU time	25.08 seconds
Started	Apr 30 02:20:50 PM PDT 24
Finished	Apr 30 02:21:16 PM PDT 24
Peak memory	249016 kb
Host	smart-34f6ba7c-3d79-489c-9e2f-2857c5ff59be
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=891894194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_out standing.891894194
Directory	/workspace/17.alert_handler_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.146476058
Short name	T159
Test name
Test status
Simulation time	24916361596 ps
CPU time	334.15 seconds
Started	Apr 30 02:20:44 PM PDT 24
Finished	Apr 30 02:26:18 PM PDT 24
Peak memory	265644 kb
Host	smart-8517a430-5aa5-41e0-beaa-e31c14de52f8
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=146476058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_erro rs.146476058
Directory	/workspace/17.alert_handler_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.2799103874
Short name	T725
Test name
Test status
Simulation time	76569391 ps
CPU time	5.6 seconds
Started	Apr 30 02:20:45 PM PDT 24
Finished	Apr 30 02:20:51 PM PDT 24
Peak memory	253052 kb
Host	smart-60ab4112-33e7-485a-b8f4-cfc081c226ff
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2799103874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.2799103874
Directory	/workspace/17.alert_handler_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.3398305606
Short name	T739
Test name
Test status
Simulation time	219029816 ps
CPU time	6.55 seconds
Started	Apr 30 02:20:49 PM PDT 24
Finished	Apr 30 02:20:56 PM PDT 24
Peak memory	251400 kb
Host	smart-25e6315a-798d-4518-9a6d-e93a5df58c88
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398305606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 18.alert_handler_csr_mem_rw_with_rand_reset.3398305606
Directory	/workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.alert_handler_intr_test.2671661730
Short name	T785
Test name
Test status
Simulation time	28539823 ps
CPU time	1.66 seconds
Started	Apr 30 02:20:48 PM PDT 24
Finished	Apr 30 02:20:51 PM PDT 24
Peak memory	237204 kb
Host	smart-d073e785-0c78-4188-8190-44af0235c1b8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2671661730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.2671661730
Directory	/workspace/18.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.742659264
Short name	T753
Test name
Test status
Simulation time	500990851 ps
CPU time	18.66 seconds
Started	Apr 30 02:20:49 PM PDT 24
Finished	Apr 30 02:21:08 PM PDT 24
Peak memory	240744 kb
Host	smart-dc2ff037-e05f-4e54-975e-7719f0e6c912
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=742659264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_out standing.742659264
Directory	/workspace/18.alert_handler_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.2953129009
Short name	T171
Test name
Test status
Simulation time	15424264625 ps
CPU time	193.98 seconds
Started	Apr 30 02:20:46 PM PDT 24
Finished	Apr 30 02:24:01 PM PDT 24
Peak memory	265624 kb
Host	smart-66af42b5-51c8-424a-aaa8-9f3661883ff1
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2953129009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err ors.2953129009
Directory	/workspace/18.alert_handler_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.662788692
Short name	T734
Test name
Test status
Simulation time	258619845 ps
CPU time	19.81 seconds
Started	Apr 30 02:20:48 PM PDT 24
Finished	Apr 30 02:21:09 PM PDT 24
Peak memory	249036 kb
Host	smart-9e638472-d47d-40bb-86aa-79f965a1ed57
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=662788692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.662788692
Directory	/workspace/18.alert_handler_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.4089923265
Short name	T198
Test name
Test status
Simulation time	168268263 ps
CPU time	3.63 seconds
Started	Apr 30 02:20:45 PM PDT 24
Finished	Apr 30 02:20:49 PM PDT 24
Peak memory	237240 kb
Host	smart-f8cff00d-e6fa-4930-ab72-df9c092d05d1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=4089923265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.4089923265
Directory	/workspace/18.alert_handler_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.2563496164
Short name	T381
Test name
Test status
Simulation time	32096700 ps
CPU time	6.33 seconds
Started	Apr 30 02:20:49 PM PDT 24
Finished	Apr 30 02:20:56 PM PDT 24
Peak memory	240952 kb
Host	smart-2b9998d2-4feb-4a21-a946-f1e6d65f27fc
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563496164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 19.alert_handler_csr_mem_rw_with_rand_reset.2563496164
Directory	/workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.641233227
Short name	T745
Test name
Test status
Simulation time	68077312 ps
CPU time	5.2 seconds
Started	Apr 30 02:20:44 PM PDT 24
Finished	Apr 30 02:20:50 PM PDT 24
Peak memory	237080 kb
Host	smart-e6200c5e-53d9-4281-89e4-9264191e9294
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=641233227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.641233227
Directory	/workspace/19.alert_handler_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.alert_handler_intr_test.3113505143
Short name	T781
Test name
Test status
Simulation time	9993773 ps
CPU time	1.23 seconds
Started	Apr 30 02:20:44 PM PDT 24
Finished	Apr 30 02:20:45 PM PDT 24
Peak memory	237240 kb
Host	smart-065b663d-742c-43fe-a98e-71d0630b63ca
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3113505143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.3113505143
Directory	/workspace/19.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.2851375832
Short name	T766
Test name
Test status
Simulation time	3903359265 ps
CPU time	52.01 seconds
Started	Apr 30 02:20:47 PM PDT 24
Finished	Apr 30 02:21:39 PM PDT 24
Peak memory	245424 kb
Host	smart-cdfaea9b-1b04-4f12-8e0a-42cd55abd8da
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2851375832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou tstanding.2851375832
Directory	/workspace/19.alert_handler_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.2742812608
Short name	T156
Test name
Test status
Simulation time	1195479739 ps
CPU time	106.92 seconds
Started	Apr 30 02:20:49 PM PDT 24
Finished	Apr 30 02:22:37 PM PDT 24
Peak memory	265576 kb
Host	smart-4ab40ac2-e560-4935-b107-2f1d568c92ea
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2742812608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err ors.2742812608
Directory	/workspace/19.alert_handler_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.4238703539
Short name	T169
Test name
Test status
Simulation time	7852293815 ps
CPU time	355.29 seconds
Started	Apr 30 02:20:46 PM PDT 24
Finished	Apr 30 02:26:42 PM PDT 24
Peak memory	268104 kb
Host	smart-b0f0ad37-2461-43dc-9f8d-6be21ae0bd73
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238703539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.4238703539
Directory	/workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.2882803244
Short name	T711
Test name
Test status
Simulation time	411149438 ps
CPU time	14.29 seconds
Started	Apr 30 02:20:50 PM PDT 24
Finished	Apr 30 02:21:05 PM PDT 24
Peak memory	249064 kb
Host	smart-7d5aafa7-5f70-49eb-bfe2-6482b43f4de8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2882803244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.2882803244
Directory	/workspace/19.alert_handler_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.145973237
Short name	T811
Test name
Test status
Simulation time	4367958271 ps
CPU time	184.07 seconds
Started	Apr 30 02:20:19 PM PDT 24
Finished	Apr 30 02:23:23 PM PDT 24
Peak memory	240812 kb
Host	smart-3255d2f8-aa6d-4029-9509-36139fa630aa
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=145973237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.145973237
Directory	/workspace/2.alert_handler_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.2338755918
Short name	T820
Test name
Test status
Simulation time	11444586795 ps
CPU time	418.52 seconds
Started	Apr 30 02:20:19 PM PDT 24
Finished	Apr 30 02:27:18 PM PDT 24
Peak memory	237188 kb
Host	smart-2ed9a70b-092a-4a67-9c5f-d5edc104e9e2
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2338755918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.2338755918
Directory	/workspace/2.alert_handler_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.1930987294
Short name	T214
Test name
Test status
Simulation time	537795578 ps
CPU time	12.1 seconds
Started	Apr 30 02:20:21 PM PDT 24
Finished	Apr 30 02:20:34 PM PDT 24
Peak memory	240608 kb
Host	smart-a323f7d0-e2cc-4794-8787-276822ef0167
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1930987294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.1930987294
Directory	/workspace/2.alert_handler_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.1716669868
Short name	T822
Test name
Test status
Simulation time	107708480 ps
CPU time	4.64 seconds
Started	Apr 30 02:20:19 PM PDT 24
Finished	Apr 30 02:20:24 PM PDT 24
Peak memory	240720 kb
Host	smart-abc56175-5e7d-483d-9ad6-2cdc7a2736f0
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716669868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 2.alert_handler_csr_mem_rw_with_rand_reset.1716669868
Directory	/workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.628117635
Short name	T773
Test name
Test status
Simulation time	19622989 ps
CPU time	4.5 seconds
Started	Apr 30 02:20:21 PM PDT 24
Finished	Apr 30 02:20:26 PM PDT 24
Peak memory	239796 kb
Host	smart-a6ad1088-ab43-4fcd-a64a-63548868cbb0
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=628117635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.628117635
Directory	/workspace/2.alert_handler_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.alert_handler_intr_test.2402096078
Short name	T720
Test name
Test status
Simulation time	13155099 ps
CPU time	1.36 seconds
Started	Apr 30 02:20:24 PM PDT 24
Finished	Apr 30 02:20:26 PM PDT 24
Peak memory	237228 kb
Host	smart-8310df51-92ae-43a3-ae9e-a6475a4dc54f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2402096078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.2402096078
Directory	/workspace/2.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.1452775740
Short name	T758
Test name
Test status
Simulation time	1516597074 ps
CPU time	36.78 seconds
Started	Apr 30 02:20:20 PM PDT 24
Finished	Apr 30 02:20:57 PM PDT 24
Peak memory	244524 kb
Host	smart-544f3d81-c4d9-4ea3-9e9f-2b9c62bbd819
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1452775740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out standing.1452775740
Directory	/workspace/2.alert_handler_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.2828010110
Short name	T718
Test name
Test status
Simulation time	90279432 ps
CPU time	8.26 seconds
Started	Apr 30 02:20:20 PM PDT 24
Finished	Apr 30 02:20:29 PM PDT 24
Peak memory	249104 kb
Host	smart-dcba057f-fbe8-46f6-89e2-cf6fb9f5abd8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2828010110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.2828010110
Directory	/workspace/2.alert_handler_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/20.alert_handler_intr_test.3235283792
Short name	T373
Test name
Test status
Simulation time	6783807 ps
CPU time	1.46 seconds
Started	Apr 30 02:20:48 PM PDT 24
Finished	Apr 30 02:20:50 PM PDT 24
Peak memory	237172 kb
Host	smart-7f85d5ac-7113-4a02-996d-68d813731ba6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3235283792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.3235283792
Directory	/workspace/20.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.alert_handler_intr_test.4107619938
Short name	T763
Test name
Test status
Simulation time	7356547 ps
CPU time	1.4 seconds
Started	Apr 30 02:20:50 PM PDT 24
Finished	Apr 30 02:20:52 PM PDT 24
Peak memory	237268 kb
Host	smart-4e8d937e-80b6-4f53-ac80-1a2c894b9725
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4107619938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.4107619938
Directory	/workspace/21.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.alert_handler_intr_test.2061140199
Short name	T754
Test name
Test status
Simulation time	12245994 ps
CPU time	1.25 seconds
Started	Apr 30 02:20:49 PM PDT 24
Finished	Apr 30 02:20:51 PM PDT 24
Peak memory	235252 kb
Host	smart-19da9fe4-3cdb-48b9-90d9-868fcde58083
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2061140199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.2061140199
Directory	/workspace/22.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1782300344
Short name	T748
Test name
Test status
Simulation time	8586811 ps
CPU time	1.55 seconds
Started	Apr 30 02:20:51 PM PDT 24
Finished	Apr 30 02:20:54 PM PDT 24
Peak memory	237288 kb
Host	smart-c042ae2e-4a54-458e-a112-a17d6666fa11
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1782300344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.1782300344
Directory	/workspace/23.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.alert_handler_intr_test.1404212896
Short name	T769
Test name
Test status
Simulation time	6865102 ps
CPU time	1.46 seconds
Started	Apr 30 02:20:50 PM PDT 24
Finished	Apr 30 02:20:52 PM PDT 24
Peak memory	237208 kb
Host	smart-bad9e375-9acc-477e-b1cd-13f4efeb3c31
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1404212896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.1404212896
Directory	/workspace/24.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.alert_handler_intr_test.837062930
Short name	T768
Test name
Test status
Simulation time	9791702 ps
CPU time	1.6 seconds
Started	Apr 30 02:20:52 PM PDT 24
Finished	Apr 30 02:20:54 PM PDT 24
Peak memory	236348 kb
Host	smart-48590b50-6cf0-444d-a56c-d20dbd4196e8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=837062930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.837062930
Directory	/workspace/25.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.alert_handler_intr_test.2396216550
Short name	T728
Test name
Test status
Simulation time	7710093 ps
CPU time	1.56 seconds
Started	Apr 30 02:20:52 PM PDT 24
Finished	Apr 30 02:20:54 PM PDT 24
Peak memory	235268 kb
Host	smart-df9510f7-15e5-424d-bc24-c60dda4f0ff9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2396216550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.2396216550
Directory	/workspace/26.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.alert_handler_intr_test.1454323198
Short name	T180
Test name
Test status
Simulation time	7747460 ps
CPU time	1.41 seconds
Started	Apr 30 02:20:51 PM PDT 24
Finished	Apr 30 02:20:54 PM PDT 24
Peak memory	237192 kb
Host	smart-d3f0810e-666d-431c-a42d-500208724338
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1454323198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.1454323198
Directory	/workspace/27.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.alert_handler_intr_test.558133738
Short name	T806
Test name
Test status
Simulation time	6312901 ps
CPU time	1.43 seconds
Started	Apr 30 02:20:51 PM PDT 24
Finished	Apr 30 02:20:53 PM PDT 24
Peak memory	237260 kb
Host	smart-3cd35df5-d653-45bf-a1a9-0b9fba8885e1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=558133738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.558133738
Directory	/workspace/28.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.314860930
Short name	T727
Test name
Test status
Simulation time	13476990298 ps
CPU time	255.83 seconds
Started	Apr 30 02:20:30 PM PDT 24
Finished	Apr 30 02:24:46 PM PDT 24
Peak memory	240724 kb
Host	smart-46f3a010-a538-4079-b12a-b53e86dc3076
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=314860930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.314860930
Directory	/workspace/3.alert_handler_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.3477839643
Short name	T741
Test name
Test status
Simulation time	17823054308 ps
CPU time	257.26 seconds
Started	Apr 30 02:20:28 PM PDT 24
Finished	Apr 30 02:24:46 PM PDT 24
Peak memory	240760 kb
Host	smart-babfbeba-a49a-4d22-8759-bbe13f47842e
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3477839643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.3477839643
Directory	/workspace/3.alert_handler_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.545520588
Short name	T742
Test name
Test status
Simulation time	271465099 ps
CPU time	11.96 seconds
Started	Apr 30 02:20:26 PM PDT 24
Finished	Apr 30 02:20:39 PM PDT 24
Peak memory	240984 kb
Host	smart-381f2895-f301-425a-99a3-ad1e70049cac
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=545520588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.545520588
Directory	/workspace/3.alert_handler_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.393468690
Short name	T775
Test name
Test status
Simulation time	37047702 ps
CPU time	5.45 seconds
Started	Apr 30 02:20:27 PM PDT 24
Finished	Apr 30 02:20:34 PM PDT 24
Peak memory	248996 kb
Host	smart-2a9bed77-b87c-45ef-9617-9c80828c9652
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393468690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 3.alert_handler_csr_mem_rw_with_rand_reset.393468690
Directory	/workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.3353998987
Short name	T215
Test name
Test status
Simulation time	38176006 ps
CPU time	6.87 seconds
Started	Apr 30 02:20:26 PM PDT 24
Finished	Apr 30 02:20:34 PM PDT 24
Peak memory	240488 kb
Host	smart-8e460a62-9cad-4e2e-96ec-cfe7426bf5ac
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3353998987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.3353998987
Directory	/workspace/3.alert_handler_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.alert_handler_intr_test.2870993681
Short name	T796
Test name
Test status
Simulation time	6690430 ps
CPU time	1.43 seconds
Started	Apr 30 02:20:24 PM PDT 24
Finished	Apr 30 02:20:26 PM PDT 24
Peak memory	235200 kb
Host	smart-80393437-19c4-4230-b843-a99103aeb5be
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2870993681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.2870993681
Directory	/workspace/3.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.2445638265
Short name	T216
Test name
Test status
Simulation time	2576188732 ps
CPU time	47.46 seconds
Started	Apr 30 02:20:29 PM PDT 24
Finished	Apr 30 02:21:17 PM PDT 24
Peak memory	248968 kb
Host	smart-927178cf-bff4-4d85-820b-27f0793c6c87
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2445638265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out standing.2445638265
Directory	/workspace/3.alert_handler_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.3897453381
Short name	T175
Test name
Test status
Simulation time	12698470547 ps
CPU time	460.23 seconds
Started	Apr 30 02:20:18 PM PDT 24
Finished	Apr 30 02:28:00 PM PDT 24
Peak memory	269652 kb
Host	smart-46e57d27-865e-4c39-bb0a-c8e4e7676b87
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897453381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.3897453381
Directory	/workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.3813497128
Short name	T783
Test name
Test status
Simulation time	327568315 ps
CPU time	15.72 seconds
Started	Apr 30 02:20:18 PM PDT 24
Finished	Apr 30 02:20:34 PM PDT 24
Peak memory	248984 kb
Host	smart-58097849-0af6-4e20-bb8b-673c63fdbba1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3813497128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.3813497128
Directory	/workspace/3.alert_handler_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.2949038493
Short name	T179
Test name
Test status
Simulation time	4094632310 ps
CPU time	34.55 seconds
Started	Apr 30 02:20:27 PM PDT 24
Finished	Apr 30 02:21:03 PM PDT 24
Peak memory	237472 kb
Host	smart-617cb9a2-9bbf-49c4-8aff-7f8e4526150f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2949038493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.2949038493
Directory	/workspace/3.alert_handler_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.alert_handler_intr_test.285212220
Short name	T809
Test name
Test status
Simulation time	6800433 ps
CPU time	1.57 seconds
Started	Apr 30 02:20:51 PM PDT 24
Finished	Apr 30 02:20:53 PM PDT 24
Peak memory	236280 kb
Host	smart-542a81ec-8361-4af9-989b-cd455bfcec01
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=285212220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.285212220
Directory	/workspace/30.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.alert_handler_intr_test.3335747588
Short name	T782
Test name
Test status
Simulation time	24720260 ps
CPU time	1.36 seconds
Started	Apr 30 02:20:49 PM PDT 24
Finished	Apr 30 02:20:51 PM PDT 24
Peak memory	235248 kb
Host	smart-1b669398-d7e9-4172-baf2-c404dc69041a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3335747588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.3335747588
Directory	/workspace/31.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.alert_handler_intr_test.638810737
Short name	T801
Test name
Test status
Simulation time	24900038 ps
CPU time	1.44 seconds
Started	Apr 30 02:20:52 PM PDT 24
Finished	Apr 30 02:20:55 PM PDT 24
Peak memory	237172 kb
Host	smart-4d5538d7-2a38-45f5-9472-b27038801e00
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=638810737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.638810737
Directory	/workspace/32.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.alert_handler_intr_test.2424712672
Short name	T776
Test name
Test status
Simulation time	27146363 ps
CPU time	1.47 seconds
Started	Apr 30 02:20:52 PM PDT 24
Finished	Apr 30 02:20:54 PM PDT 24
Peak memory	236320 kb
Host	smart-674e3d2e-4bbc-40e2-b8b4-d7378060edc0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2424712672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.2424712672
Directory	/workspace/33.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.alert_handler_intr_test.2685979221
Short name	T813
Test name
Test status
Simulation time	7483632 ps
CPU time	1.29 seconds
Started	Apr 30 02:20:50 PM PDT 24
Finished	Apr 30 02:20:51 PM PDT 24
Peak memory	236324 kb
Host	smart-ec2105cb-db99-4985-a16f-6c935da0b57c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2685979221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.2685979221
Directory	/workspace/34.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.alert_handler_intr_test.2218510676
Short name	T760
Test name
Test status
Simulation time	21281098 ps
CPU time	1.49 seconds
Started	Apr 30 02:20:51 PM PDT 24
Finished	Apr 30 02:20:53 PM PDT 24
Peak memory	236376 kb
Host	smart-9540e5a6-17ca-4eb5-9a2a-c6c9da17bc70
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2218510676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.2218510676
Directory	/workspace/35.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.alert_handler_intr_test.1987305502
Short name	T793
Test name
Test status
Simulation time	8009541 ps
CPU time	1.52 seconds
Started	Apr 30 02:20:51 PM PDT 24
Finished	Apr 30 02:20:53 PM PDT 24
Peak memory	236324 kb
Host	smart-6b36a0c8-1b51-4be4-b6bf-f7d1bfcb25a9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1987305502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.1987305502
Directory	/workspace/36.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.alert_handler_intr_test.1327919979
Short name	T722
Test name
Test status
Simulation time	7935738 ps
CPU time	1.43 seconds
Started	Apr 30 02:20:50 PM PDT 24
Finished	Apr 30 02:20:52 PM PDT 24
Peak memory	237244 kb
Host	smart-7f1d1c84-a8e5-4f0a-85be-688b353441fb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1327919979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.1327919979
Directory	/workspace/37.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.alert_handler_intr_test.191651578
Short name	T828
Test name
Test status
Simulation time	7604093 ps
CPU time	1.57 seconds
Started	Apr 30 02:20:52 PM PDT 24
Finished	Apr 30 02:20:55 PM PDT 24
Peak memory	237280 kb
Host	smart-0773c77f-5cca-4761-83f0-50d35b10324d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=191651578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.191651578
Directory	/workspace/38.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.alert_handler_intr_test.218109876
Short name	T750
Test name
Test status
Simulation time	20920564 ps
CPU time	1.45 seconds
Started	Apr 30 02:20:51 PM PDT 24
Finished	Apr 30 02:20:54 PM PDT 24
Peak memory	237196 kb
Host	smart-98f5a6a8-d16c-4480-98fe-bb24e083f5cd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=218109876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.218109876
Directory	/workspace/39.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.1776078712
Short name	T810
Test name
Test status
Simulation time	1087098888 ps
CPU time	78.85 seconds
Started	Apr 30 02:20:25 PM PDT 24
Finished	Apr 30 02:21:45 PM PDT 24
Peak memory	240684 kb
Host	smart-97d9e7fa-183b-48cf-ade8-5acf38b56cd5
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1776078712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.1776078712
Directory	/workspace/4.alert_handler_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.4216000846
Short name	T380
Test name
Test status
Simulation time	9010307940 ps
CPU time	546.36 seconds
Started	Apr 30 02:20:26 PM PDT 24
Finished	Apr 30 02:29:34 PM PDT 24
Peak memory	237232 kb
Host	smart-1bb31a6e-68d5-40c3-9785-ac1cff13bd69
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=4216000846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.4216000846
Directory	/workspace/4.alert_handler_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.3163741492
Short name	T713
Test name
Test status
Simulation time	133578730 ps
CPU time	5.81 seconds
Started	Apr 30 02:20:26 PM PDT 24
Finished	Apr 30 02:20:32 PM PDT 24
Peak memory	240648 kb
Host	smart-164b457d-5ec4-4695-a340-09efda150e98
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3163741492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.3163741492
Directory	/workspace/4.alert_handler_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.2486031796
Short name	T746
Test name
Test status
Simulation time	36560226 ps
CPU time	5.49 seconds
Started	Apr 30 02:20:23 PM PDT 24
Finished	Apr 30 02:20:29 PM PDT 24
Peak memory	240812 kb
Host	smart-e74166ea-6038-4f53-a3b9-cc48554fc11c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486031796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 4.alert_handler_csr_mem_rw_with_rand_reset.2486031796
Directory	/workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.3491984848
Short name	T780
Test name
Test status
Simulation time	292242544 ps
CPU time	5.13 seconds
Started	Apr 30 02:20:27 PM PDT 24
Finished	Apr 30 02:20:33 PM PDT 24
Peak memory	237156 kb
Host	smart-99356baa-4f45-4ea8-8ccb-7d8730df4252
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3491984848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.3491984848
Directory	/workspace/4.alert_handler_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.alert_handler_intr_test.3576729944
Short name	T726
Test name
Test status
Simulation time	9155960 ps
CPU time	1.42 seconds
Started	Apr 30 02:20:26 PM PDT 24
Finished	Apr 30 02:20:28 PM PDT 24
Peak memory	235332 kb
Host	smart-1127b1fc-63f0-4eaa-ac0b-f18d171c1c79
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3576729944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.3576729944
Directory	/workspace/4.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.2178198304
Short name	T770
Test name
Test status
Simulation time	3729265525 ps
CPU time	40.37 seconds
Started	Apr 30 02:20:24 PM PDT 24
Finished	Apr 30 02:21:05 PM PDT 24
Peak memory	244520 kb
Host	smart-b2c81c20-6612-48d1-8d0a-53e100cf548e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2178198304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out standing.2178198304
Directory	/workspace/4.alert_handler_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.4036787327
Short name	T821
Test name
Test status
Simulation time	1909717118 ps
CPU time	21.78 seconds
Started	Apr 30 02:20:26 PM PDT 24
Finished	Apr 30 02:20:49 PM PDT 24
Peak memory	253544 kb
Host	smart-7c92d593-23d7-45a2-9b65-291e8de9d2eb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4036787327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.4036787327
Directory	/workspace/4.alert_handler_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/40.alert_handler_intr_test.26846491
Short name	T374
Test name
Test status
Simulation time	20863771 ps
CPU time	1.39 seconds
Started	Apr 30 02:20:53 PM PDT 24
Finished	Apr 30 02:20:55 PM PDT 24
Peak memory	235188 kb
Host	smart-312bcf1b-11b9-4713-aa11-09c2a5060d25
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=26846491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.26846491
Directory	/workspace/40.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.alert_handler_intr_test.2673158915
Short name	T819
Test name
Test status
Simulation time	11022198 ps
CPU time	1.45 seconds
Started	Apr 30 02:20:52 PM PDT 24
Finished	Apr 30 02:20:54 PM PDT 24
Peak memory	235368 kb
Host	smart-4591e80c-de67-4ba4-a965-8552612d3153
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2673158915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.2673158915
Directory	/workspace/41.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.alert_handler_intr_test.1847876155
Short name	T826
Test name
Test status
Simulation time	16675922 ps
CPU time	1.43 seconds
Started	Apr 30 02:20:51 PM PDT 24
Finished	Apr 30 02:20:53 PM PDT 24
Peak memory	236332 kb
Host	smart-2e3303bd-7343-463a-a9fd-e468eea617b3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1847876155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.1847876155
Directory	/workspace/42.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.alert_handler_intr_test.2556425506
Short name	T377
Test name
Test status
Simulation time	14846007 ps
CPU time	1.55 seconds
Started	Apr 30 02:20:51 PM PDT 24
Finished	Apr 30 02:20:53 PM PDT 24
Peak memory	236280 kb
Host	smart-060964a1-a654-499c-9043-7ee38cdb6dd8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2556425506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.2556425506
Directory	/workspace/43.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.alert_handler_intr_test.3476482195
Short name	T376
Test name
Test status
Simulation time	19693799 ps
CPU time	1.31 seconds
Started	Apr 30 02:20:52 PM PDT 24
Finished	Apr 30 02:20:54 PM PDT 24
Peak memory	237076 kb
Host	smart-493db652-19b3-434b-a612-b9270d5cbc49
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3476482195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.3476482195
Directory	/workspace/44.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.alert_handler_intr_test.1764608671
Short name	T736
Test name
Test status
Simulation time	23072384 ps
CPU time	1.31 seconds
Started	Apr 30 02:20:51 PM PDT 24
Finished	Apr 30 02:20:54 PM PDT 24
Peak memory	236360 kb
Host	smart-b1c78b74-2e5c-47e4-bbc9-5964dbde3847
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1764608671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.1764608671
Directory	/workspace/45.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.alert_handler_intr_test.3968760542
Short name	T800
Test name
Test status
Simulation time	6365045 ps
CPU time	1.51 seconds
Started	Apr 30 02:20:53 PM PDT 24
Finished	Apr 30 02:20:55 PM PDT 24
Peak memory	237280 kb
Host	smart-f888db2a-420e-4bc8-b568-2c6318a67269
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3968760542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.3968760542
Directory	/workspace/46.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.alert_handler_intr_test.2444066800
Short name	T825
Test name
Test status
Simulation time	8089161 ps
CPU time	1.35 seconds
Started	Apr 30 02:20:52 PM PDT 24
Finished	Apr 30 02:20:54 PM PDT 24
Peak memory	236340 kb
Host	smart-4c003498-486e-414c-a538-32fa5278b8e9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2444066800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.2444066800
Directory	/workspace/47.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.alert_handler_intr_test.1426010796
Short name	T371
Test name
Test status
Simulation time	11187496 ps
CPU time	1.54 seconds
Started	Apr 30 02:20:52 PM PDT 24
Finished	Apr 30 02:20:55 PM PDT 24
Peak memory	237176 kb
Host	smart-a1f7ae94-cd3d-49e8-927c-5d3ce2df768a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1426010796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.1426010796
Directory	/workspace/49.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.2434277954
Short name	T740
Test name
Test status
Simulation time	103784734 ps
CPU time	8.57 seconds
Started	Apr 30 02:20:27 PM PDT 24
Finished	Apr 30 02:20:37 PM PDT 24
Peak memory	239344 kb
Host	smart-065a13ff-4191-4623-8906-078831f8ffbe
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434277954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 5.alert_handler_csr_mem_rw_with_rand_reset.2434277954
Directory	/workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.3385998295
Short name	T230
Test name
Test status
Simulation time	34166049 ps
CPU time	3.5 seconds
Started	Apr 30 02:20:26 PM PDT 24
Finished	Apr 30 02:20:31 PM PDT 24
Peak memory	239816 kb
Host	smart-29131e78-ff5f-4d9b-a864-cd774ca30002
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3385998295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.3385998295
Directory	/workspace/5.alert_handler_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.alert_handler_intr_test.406833719
Short name	T808
Test name
Test status
Simulation time	20342849 ps
CPU time	1.47 seconds
Started	Apr 30 02:20:30 PM PDT 24
Finished	Apr 30 02:20:31 PM PDT 24
Peak memory	237204 kb
Host	smart-a9a98402-f415-4504-9cbd-ca8f1046c099
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=406833719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.406833719
Directory	/workspace/5.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.1061965392
Short name	T759
Test name
Test status
Simulation time	176362007 ps
CPU time	12.18 seconds
Started	Apr 30 02:20:26 PM PDT 24
Finished	Apr 30 02:20:40 PM PDT 24
Peak memory	244536 kb
Host	smart-6479e3bd-d489-477d-b98a-953a69dcd26f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1061965392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out standing.1061965392
Directory	/workspace/5.alert_handler_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.3853476633
Short name	T144
Test name
Test status
Simulation time	14969971827 ps
CPU time	311.61 seconds
Started	Apr 30 02:20:25 PM PDT 24
Finished	Apr 30 02:25:38 PM PDT 24
Peak memory	265696 kb
Host	smart-19733c4c-8dce-4566-a36a-54f73355ea65
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=3853476633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro rs.3853476633
Directory	/workspace/5.alert_handler_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.2567056361
Short name	T147
Test name
Test status
Simulation time	26794298089 ps
CPU time	324.26 seconds
Started	Apr 30 02:20:26 PM PDT 24
Finished	Apr 30 02:25:51 PM PDT 24
Peak memory	265580 kb
Host	smart-da3152e5-0646-4547-b3ae-a15b6347d92d
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567056361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.2567056361
Directory	/workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.3454983297
Short name	T724
Test name
Test status
Simulation time	69936184 ps
CPU time	7.81 seconds
Started	Apr 30 02:20:24 PM PDT 24
Finished	Apr 30 02:20:32 PM PDT 24
Peak memory	248540 kb
Host	smart-e2cf4202-0c6d-472a-aa43-22702608ab2f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3454983297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.3454983297
Directory	/workspace/5.alert_handler_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.3078375644
Short name	T802
Test name
Test status
Simulation time	104063449 ps
CPU time	9.38 seconds
Started	Apr 30 02:20:25 PM PDT 24
Finished	Apr 30 02:20:35 PM PDT 24
Peak memory	240860 kb
Host	smart-a9210698-f7a8-41e7-b3c8-e648a14af169
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078375644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 6.alert_handler_csr_mem_rw_with_rand_reset.3078375644
Directory	/workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.392740221
Short name	T792
Test name
Test status
Simulation time	1212926216 ps
CPU time	9.68 seconds
Started	Apr 30 02:20:23 PM PDT 24
Finished	Apr 30 02:20:34 PM PDT 24
Peak memory	240720 kb
Host	smart-699b1c75-c589-4ba9-9003-d7adfdfe87b0
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=392740221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.392740221
Directory	/workspace/6.alert_handler_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.1403034733
Short name	T218
Test name
Test status
Simulation time	86098387 ps
CPU time	12.3 seconds
Started	Apr 30 02:20:25 PM PDT 24
Finished	Apr 30 02:20:37 PM PDT 24
Peak memory	240756 kb
Host	smart-271f2c85-af36-4d24-97c1-dcb8b4ad0e2a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1403034733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out standing.1403034733
Directory	/workspace/6.alert_handler_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.1134819227
Short name	T158
Test name
Test status
Simulation time	1304092338 ps
CPU time	128.79 seconds
Started	Apr 30 02:20:25 PM PDT 24
Finished	Apr 30 02:22:34 PM PDT 24
Peak memory	257200 kb
Host	smart-0a993c6f-a3c2-4b17-9166-85d2775005b9
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=1134819227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro rs.1134819227
Directory	/workspace/6.alert_handler_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.1066880725
Short name	T715
Test name
Test status
Simulation time	906040179 ps
CPU time	13.49 seconds
Started	Apr 30 02:20:27 PM PDT 24
Finished	Apr 30 02:20:42 PM PDT 24
Peak memory	248984 kb
Host	smart-daffa3ec-641d-488e-b40e-9923a2d24ec0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1066880725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.1066880725
Directory	/workspace/6.alert_handler_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.65542071
Short name	T721
Test name
Test status
Simulation time	7452868790 ps
CPU time	43.89 seconds
Started	Apr 30 02:20:27 PM PDT 24
Finished	Apr 30 02:21:12 PM PDT 24
Peak memory	237416 kb
Host	smart-daec2544-19ea-441d-9581-19e38fe3c4c2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=65542071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.65542071
Directory	/workspace/6.alert_handler_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.1174744417
Short name	T196
Test name
Test status
Simulation time	61658483 ps
CPU time	4.74 seconds
Started	Apr 30 02:20:25 PM PDT 24
Finished	Apr 30 02:20:30 PM PDT 24
Peak memory	241868 kb
Host	smart-be6fd08f-1a8b-4532-ba85-cb25c05a053d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174744417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 7.alert_handler_csr_mem_rw_with_rand_reset.1174744417
Directory	/workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.74137375
Short name	T765
Test name
Test status
Simulation time	31156530 ps
CPU time	3.38 seconds
Started	Apr 30 02:20:27 PM PDT 24
Finished	Apr 30 02:20:32 PM PDT 24
Peak memory	237124 kb
Host	smart-f3be4be1-34d8-4ac9-b71d-8478af5e7e23
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=74137375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.74137375
Directory	/workspace/7.alert_handler_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.alert_handler_intr_test.3280400101
Short name	T378
Test name
Test status
Simulation time	9863531 ps
CPU time	1.48 seconds
Started	Apr 30 02:20:29 PM PDT 24
Finished	Apr 30 02:20:31 PM PDT 24
Peak memory	236336 kb
Host	smart-79ee1ae2-f389-4129-b77d-84562ee5ee94
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3280400101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.3280400101
Directory	/workspace/7.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.2966478580
Short name	T786
Test name
Test status
Simulation time	173759631 ps
CPU time	20.71 seconds
Started	Apr 30 02:20:27 PM PDT 24
Finished	Apr 30 02:20:49 PM PDT 24
Peak memory	244540 kb
Host	smart-55c498ab-0b9e-4b90-ba1a-e354fcc057cd
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2966478580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out standing.2966478580
Directory	/workspace/7.alert_handler_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.4214669734
Short name	T161
Test name
Test status
Simulation time	12942924777 ps
CPU time	527.36 seconds
Started	Apr 30 02:20:27 PM PDT 24
Finished	Apr 30 02:29:16 PM PDT 24
Peak memory	265908 kb
Host	smart-e1d768f1-267f-4781-b3ef-f2a49e55c6fa
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214669734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.4214669734
Directory	/workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.3963828347
Short name	T762
Test name
Test status
Simulation time	298366543 ps
CPU time	24.62 seconds
Started	Apr 30 02:20:26 PM PDT 24
Finished	Apr 30 02:20:52 PM PDT 24
Peak memory	249032 kb
Host	smart-f9bd8993-8a30-43c7-b2ad-5a72d54dd4bb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3963828347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.3963828347
Directory	/workspace/7.alert_handler_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.1304064959
Short name	T777
Test name
Test status
Simulation time	424369705 ps
CPU time	9.06 seconds
Started	Apr 30 02:20:41 PM PDT 24
Finished	Apr 30 02:20:50 PM PDT 24
Peak memory	252676 kb
Host	smart-c87b5dbc-5c69-4836-b535-9c72336598c3
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304064959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 8.alert_handler_csr_mem_rw_with_rand_reset.1304064959
Directory	/workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.3837597146
Short name	T749
Test name
Test status
Simulation time	69133348 ps
CPU time	5.73 seconds
Started	Apr 30 02:20:35 PM PDT 24
Finished	Apr 30 02:20:41 PM PDT 24
Peak memory	237084 kb
Host	smart-8cb92eed-2e5a-4cba-993f-45557858e7eb
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3837597146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.3837597146
Directory	/workspace/8.alert_handler_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.alert_handler_intr_test.3190960410
Short name	T729
Test name
Test status
Simulation time	24616980 ps
CPU time	1.62 seconds
Started	Apr 30 02:20:38 PM PDT 24
Finished	Apr 30 02:20:40 PM PDT 24
Peak memory	237280 kb
Host	smart-b644ee60-ae10-4b43-ad8b-b30fc3154bf3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3190960410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.3190960410
Directory	/workspace/8.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.922519419
Short name	T195
Test name
Test status
Simulation time	664052337 ps
CPU time	43.66 seconds
Started	Apr 30 02:20:37 PM PDT 24
Finished	Apr 30 02:21:21 PM PDT 24
Peak memory	248980 kb
Host	smart-a21f6331-e574-4693-9ad5-d0997c7d3c59
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=922519419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_outs tanding.922519419
Directory	/workspace/8.alert_handler_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.2275879325
Short name	T173
Test name
Test status
Simulation time	732339014 ps
CPU time	96.18 seconds
Started	Apr 30 02:20:27 PM PDT 24
Finished	Apr 30 02:22:05 PM PDT 24
Peak memory	257408 kb
Host	smart-dd82b131-f37f-4bf9-9fce-f2aa8cad2d81
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/ dv/tools/sim.tcl +ntb_random_seed=2275879325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro rs.2275879325
Directory	/workspace/8.alert_handler_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.2091837478
Short name	T163
Test name
Test status
Simulation time	8668464677 ps
CPU time	572.44 seconds
Started	Apr 30 02:20:28 PM PDT 24
Finished	Apr 30 02:30:01 PM PDT 24
Peak memory	265620 kb
Host	smart-3f26c22c-0473-400e-b40c-46b167104e2f
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091837478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.2091837478
Directory	/workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.1989149168
Short name	T714
Test name
Test status
Simulation time	241735162 ps
CPU time	20.56 seconds
Started	Apr 30 02:20:29 PM PDT 24
Finished	Apr 30 02:20:50 PM PDT 24
Peak memory	253224 kb
Host	smart-30a7df0e-7dec-42bf-a903-8233a503e0d2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1989149168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.1989149168
Directory	/workspace/8.alert_handler_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.3026534494
Short name	T767
Test name
Test status
Simulation time	322052479 ps
CPU time	7.19 seconds
Started	Apr 30 02:20:36 PM PDT 24
Finished	Apr 30 02:20:43 PM PDT 24
Peak memory	240916 kb
Host	smart-c1d1723f-3c9a-4603-91e4-bc75d7165273
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026534494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c m_name 9.alert_handler_csr_mem_rw_with_rand_reset.3026534494
Directory	/workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.3939526126
Short name	T379
Test name
Test status
Simulation time	370574436 ps
CPU time	8.99 seconds
Started	Apr 30 02:20:38 PM PDT 24
Finished	Apr 30 02:20:48 PM PDT 24
Peak memory	240700 kb
Host	smart-be32e463-6551-4823-9321-2c2b298990fd
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3939526126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.3939526126
Directory	/workspace/9.alert_handler_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.alert_handler_intr_test.3633307291
Short name	T737
Test name
Test status
Simulation time	11835885 ps
CPU time	1.35 seconds
Started	Apr 30 02:20:37 PM PDT 24
Finished	Apr 30 02:20:39 PM PDT 24
Peak memory	237196 kb
Host	smart-0991991c-b855-401e-9e86-cb4c1452c4c8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3633307291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.3633307291
Directory	/workspace/9.alert_handler_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.3882109125
Short name	T795
Test name
Test status
Simulation time	575581363 ps
CPU time	19.63 seconds
Started	Apr 30 02:20:37 PM PDT 24
Finished	Apr 30 02:20:57 PM PDT 24
Peak memory	248936 kb
Host	smart-4e32f5c7-3a1c-4836-bcdd-ad8ee9c1c0cf
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3882109125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out standing.3882109125
Directory	/workspace/9.alert_handler_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.3024489159
Short name	T176
Test name
Test status
Simulation time	6427223282 ps
CPU time	445.29 seconds
Started	Apr 30 02:20:35 PM PDT 24
Finished	Apr 30 02:28:01 PM PDT 24
Peak memory	268868 kb
Host	smart-02c9c9bb-b663-4d8b-940e-a08453e4a0be
User	root
Command	/workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024489159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.3024489159
Directory	/workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.2402931740
Short name	T733
Test name
Test status
Simulation time	83291049 ps
CPU time	7.66 seconds
Started	Apr 30 02:20:35 PM PDT 24
Finished	Apr 30 02:20:43 PM PDT 24
Peak memory	240616 kb
Host	smart-9a107c03-b395-41e5-80c7-b24b32bbf090
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2402931740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.2402931740
Directory	/workspace/9.alert_handler_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.1617166093
Short name	T197
Test name
Test status
Simulation time	27270557 ps
CPU time	2.62 seconds
Started	Apr 30 02:20:38 PM PDT 24
Finished	Apr 30 02:20:41 PM PDT 24
Peak memory	237208 kb
Host	smart-e3fcaf2e-9901-4534-8d86-8778877a046e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1617166093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.1617166093
Directory	/workspace/9.alert_handler_tl_intg_err/latest

Test location	/workspace/coverage/default/0.alert_handler_entropy_stress.3497038598
Short name	T403
Test name
Test status
Simulation time	1917150662 ps
CPU time	21.86 seconds
Started	Apr 30 02:21:31 PM PDT 24
Finished	Apr 30 02:21:53 PM PDT 24
Peak memory	248724 kb
Host	smart-704152b4-a502-487a-8edb-cbe14b8af4f0
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3497038598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.3497038598
Directory	/workspace/0.alert_handler_entropy_stress/latest

Test location	/workspace/coverage/default/0.alert_handler_esc_alert_accum.198339673
Short name	T505
Test name
Test status
Simulation time	3995162598 ps
CPU time	28.58 seconds
Started	Apr 30 02:21:18 PM PDT 24
Finished	Apr 30 02:21:47 PM PDT 24
Peak memory	249092 kb
Host	smart-2a930c57-01bf-480b-a0af-6f0879b312b8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19833 9673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.198339673
Directory	/workspace/0.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/0.alert_handler_esc_intr_timeout.1221007079
Short name	T518
Test name
Test status
Simulation time	824584275 ps
CPU time	12.66 seconds
Started	Apr 30 02:21:22 PM PDT 24
Finished	Apr 30 02:21:35 PM PDT 24
Peak memory	255388 kb
Host	smart-c9f63251-8007-4c08-b002-f1a448cd9d58
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12210 07079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.1221007079
Directory	/workspace/0.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/0.alert_handler_lpg.3083887288
Short name	T328
Test name
Test status
Simulation time	91212020893 ps
CPU time	1420.91 seconds
Started	Apr 30 02:21:20 PM PDT 24
Finished	Apr 30 02:45:01 PM PDT 24
Peak memory	269212 kb
Host	smart-ddc46e26-3530-4919-ac2f-83f5c05fac55
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3083887288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.3083887288
Directory	/workspace/0.alert_handler_lpg/latest

Test location	/workspace/coverage/default/0.alert_handler_lpg_stub_clk.3717369217
Short name	T254
Test name
Test status
Simulation time	46418078110 ps
CPU time	2626.93 seconds
Started	Apr 30 02:21:28 PM PDT 24
Finished	Apr 30 03:05:16 PM PDT 24
Peak memory	284416 kb
Host	smart-0295f62b-4213-4ad9-b7ee-9a5ba5583b4d
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3717369217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.3717369217
Directory	/workspace/0.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/0.alert_handler_random_alerts.117188214
Short name	T515
Test name
Test status
Simulation time	325468657 ps
CPU time	25.47 seconds
Started	Apr 30 02:21:21 PM PDT 24
Finished	Apr 30 02:21:47 PM PDT 24
Peak memory	248648 kb
Host	smart-f1ab7872-28f1-48b9-b143-f7207a328e2b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11718 8214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.117188214
Directory	/workspace/0.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/0.alert_handler_random_classes.426443065
Short name	T259
Test name
Test status
Simulation time	171658800 ps
CPU time	17.37 seconds
Started	Apr 30 02:21:23 PM PDT 24
Finished	Apr 30 02:21:40 PM PDT 24
Peak memory	247396 kb
Host	smart-ff8c36a2-e8fb-4614-8ce0-9be39c8b5dbe
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42644 3065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.426443065
Directory	/workspace/0.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/0.alert_handler_sig_int_fail.843329250
Short name	T42
Test name
Test status
Simulation time	2511792154 ps
CPU time	42.77 seconds
Started	Apr 30 02:21:28 PM PDT 24
Finished	Apr 30 02:22:12 PM PDT 24
Peak memory	248508 kb
Host	smart-f00e8044-b5a6-460e-b000-7c0a70915f7c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84332 9250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.843329250
Directory	/workspace/0.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/1.alert_handler_entropy.3180749580
Short name	T123
Test name
Test status
Simulation time	14533271585 ps
CPU time	1232.02 seconds
Started	Apr 30 02:21:32 PM PDT 24
Finished	Apr 30 02:42:05 PM PDT 24
Peak memory	273372 kb
Host	smart-df30cda9-07a4-4071-8209-b5868a3e8410
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3180749580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.3180749580
Directory	/workspace/1.alert_handler_entropy/latest

Test location	/workspace/coverage/default/1.alert_handler_entropy_stress.1602010597
Short name	T6
Test name
Test status
Simulation time	1435224387 ps
CPU time	17.27 seconds
Started	Apr 30 02:21:31 PM PDT 24
Finished	Apr 30 02:21:49 PM PDT 24
Peak memory	248700 kb
Host	smart-989927b1-54e9-4895-bffb-b4eccbbd41c2
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1602010597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.1602010597
Directory	/workspace/1.alert_handler_entropy_stress/latest

Test location	/workspace/coverage/default/1.alert_handler_esc_alert_accum.1015782522
Short name	T414
Test name
Test status
Simulation time	18043436472 ps
CPU time	148.82 seconds
Started	Apr 30 02:21:31 PM PDT 24
Finished	Apr 30 02:24:00 PM PDT 24
Peak memory	250144 kb
Host	smart-8da0168b-d50c-4ff8-be7f-a351ec117bf0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10157 82522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.1015782522
Directory	/workspace/1.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/1.alert_handler_esc_intr_timeout.3462786687
Short name	T491
Test name
Test status
Simulation time	1351879559 ps
CPU time	16.42 seconds
Started	Apr 30 02:21:31 PM PDT 24
Finished	Apr 30 02:21:48 PM PDT 24
Peak memory	255424 kb
Host	smart-943613a1-b44f-4bba-a022-8bd5e5a40630
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34627 86687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.3462786687
Directory	/workspace/1.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/1.alert_handler_lpg.4000754490
Short name	T327
Test name
Test status
Simulation time	184948645560 ps
CPU time	1614.42 seconds
Started	Apr 30 02:21:32 PM PDT 24
Finished	Apr 30 02:48:27 PM PDT 24
Peak memory	265188 kb
Host	smart-ce4cc260-2a9e-440d-8443-08156320f915
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4000754490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.4000754490
Directory	/workspace/1.alert_handler_lpg/latest

Test location	/workspace/coverage/default/1.alert_handler_lpg_stub_clk.3592938891
Short name	T427
Test name
Test status
Simulation time	32972985954 ps
CPU time	1853.76 seconds
Started	Apr 30 02:21:28 PM PDT 24
Finished	Apr 30 02:52:23 PM PDT 24
Peak memory	281564 kb
Host	smart-e1826ca4-effb-4791-a0fd-46c399f8abc4
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3592938891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.3592938891
Directory	/workspace/1.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/1.alert_handler_ping_timeout.1958398783
Short name	T350
Test name
Test status
Simulation time	17204045561 ps
CPU time	178.89 seconds
Started	Apr 30 02:21:30 PM PDT 24
Finished	Apr 30 02:24:29 PM PDT 24
Peak memory	248112 kb
Host	smart-0731d3af-69d8-4c7a-bb49-1a2cabfadbd7
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1958398783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.1958398783
Directory	/workspace/1.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/1.alert_handler_random_alerts.4261573214
Short name	T385
Test name
Test status
Simulation time	2362868196 ps
CPU time	42.34 seconds
Started	Apr 30 02:21:30 PM PDT 24
Finished	Apr 30 02:22:13 PM PDT 24
Peak memory	256004 kb
Host	smart-11c6d52b-7dba-425e-9323-6faab4b073f6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42615 73214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.4261573214
Directory	/workspace/1.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/1.alert_handler_sig_int_fail.3379525216
Short name	T637
Test name
Test status
Simulation time	987527058 ps
CPU time	57.18 seconds
Started	Apr 30 02:21:31 PM PDT 24
Finished	Apr 30 02:22:29 PM PDT 24
Peak memory	248676 kb
Host	smart-0be26a6f-66a1-4608-a59f-9e4e244f768f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33795 25216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.3379525216
Directory	/workspace/1.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/1.alert_handler_smoke.5388323
Short name	T513
Test name
Test status
Simulation time	1653068978 ps
CPU time	47.46 seconds
Started	Apr 30 02:21:27 PM PDT 24
Finished	Apr 30 02:22:15 PM PDT 24
Peak memory	248680 kb
Host	smart-9ed69306-e538-46eb-a7cc-336b043a1ee0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53883 23 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.5388323
Directory	/workspace/1.alert_handler_smoke/latest

Test location	/workspace/coverage/default/1.alert_handler_stress_all.1259598799
Short name	T525
Test name
Test status
Simulation time	32646413870 ps
CPU time	2155.24 seconds
Started	Apr 30 02:21:32 PM PDT 24
Finished	Apr 30 02:57:28 PM PDT 24
Peak memory	288584 kb
Host	smart-61d0f39b-4356-4d94-aefd-4ec20c622fa0
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259598799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han dler_stress_all.1259598799
Directory	/workspace/1.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.265707913
Short name	T264
Test name
Test status
Simulation time	45553810537 ps
CPU time	628 seconds
Started	Apr 30 02:21:28 PM PDT 24
Finished	Apr 30 02:31:56 PM PDT 24
Peak memory	270656 kb
Host	smart-abeb4900-f470-481e-bd94-23f50ca711c0
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265707913 -assert nopostproc +UVM_TESTNAME=alert _handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.265707913
Directory	/workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/10.alert_handler_alert_accum_saturation.4245400128
Short name	T244
Test name
Test status
Simulation time	14747108 ps
CPU time	2.54 seconds
Started	Apr 30 02:21:46 PM PDT 24
Finished	Apr 30 02:21:49 PM PDT 24
Peak memory	248876 kb
Host	smart-9bab8ea3-1750-479f-ae62-6d03ae308805
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=4245400128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.4245400128
Directory	/workspace/10.alert_handler_alert_accum_saturation/latest

Test location	/workspace/coverage/default/10.alert_handler_entropy.2423271297
Short name	T555
Test name
Test status
Simulation time	112195773067 ps
CPU time	1647.05 seconds
Started	Apr 30 02:21:56 PM PDT 24
Finished	Apr 30 02:49:24 PM PDT 24
Peak memory	269408 kb
Host	smart-13738fdc-2016-43e6-9a64-0ca1c46b15c6
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2423271297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.2423271297
Directory	/workspace/10.alert_handler_entropy/latest

Test location	/workspace/coverage/default/10.alert_handler_entropy_stress.2190298802
Short name	T540
Test name
Test status
Simulation time	212216806 ps
CPU time	11.44 seconds
Started	Apr 30 02:21:47 PM PDT 24
Finished	Apr 30 02:21:59 PM PDT 24
Peak memory	248660 kb
Host	smart-3eb4af0c-865e-417a-b088-b0f132f334ce
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2190298802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.2190298802
Directory	/workspace/10.alert_handler_entropy_stress/latest

Test location	/workspace/coverage/default/10.alert_handler_esc_alert_accum.3908754790
Short name	T467
Test name
Test status
Simulation time	6114395861 ps
CPU time	191.78 seconds
Started	Apr 30 02:21:54 PM PDT 24
Finished	Apr 30 02:25:07 PM PDT 24
Peak memory	249748 kb
Host	smart-4f7b6781-9360-4f74-8ae5-d652fa7dfe28
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39087 54790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.3908754790
Directory	/workspace/10.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/10.alert_handler_esc_intr_timeout.2041306402
Short name	T438
Test name
Test status
Simulation time	291345461 ps
CPU time	25.55 seconds
Started	Apr 30 02:21:51 PM PDT 24
Finished	Apr 30 02:22:17 PM PDT 24
Peak memory	255924 kb
Host	smart-6422d425-73e0-4e46-9626-37ee567bb238
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20413 06402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.2041306402
Directory	/workspace/10.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/10.alert_handler_lpg_stub_clk.1500322956
Short name	T654
Test name
Test status
Simulation time	152479594549 ps
CPU time	2069.29 seconds
Started	Apr 30 02:21:47 PM PDT 24
Finished	Apr 30 02:56:18 PM PDT 24
Peak memory	273280 kb
Host	smart-767121e5-1d19-4a31-b482-489bf7790e41
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1500322956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.1500322956
Directory	/workspace/10.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/10.alert_handler_ping_timeout.3846895076
Short name	T477
Test name
Test status
Simulation time	33676214389 ps
CPU time	308.21 seconds
Started	Apr 30 02:21:46 PM PDT 24
Finished	Apr 30 02:26:55 PM PDT 24
Peak memory	247892 kb
Host	smart-026bc8dc-5baf-48c9-ace5-58cda5b1a5c2
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3846895076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.3846895076
Directory	/workspace/10.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/10.alert_handler_random_alerts.2358487038
Short name	T476
Test name
Test status
Simulation time	620057414 ps
CPU time	30.56 seconds
Started	Apr 30 02:21:50 PM PDT 24
Finished	Apr 30 02:22:21 PM PDT 24
Peak memory	256028 kb
Host	smart-b01ae164-5dd8-4ce5-ad52-41d086e54aae
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23584 87038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.2358487038
Directory	/workspace/10.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/10.alert_handler_random_classes.383099440
Short name	T407
Test name
Test status
Simulation time	642897520 ps
CPU time	46.66 seconds
Started	Apr 30 02:21:49 PM PDT 24
Finished	Apr 30 02:22:36 PM PDT 24
Peak memory	248980 kb
Host	smart-2f6257ef-3d55-465c-9ed0-0f4ca3a204be
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38309 9440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.383099440
Directory	/workspace/10.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/10.alert_handler_sig_int_fail.2111112285
Short name	T632
Test name
Test status
Simulation time	1602182527 ps
CPU time	24.68 seconds
Started	Apr 30 02:21:48 PM PDT 24
Finished	Apr 30 02:22:14 PM PDT 24
Peak memory	249140 kb
Host	smart-b5e375de-d3ea-4b9c-bb8b-7f60b5116372
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21111 12285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.2111112285
Directory	/workspace/10.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/10.alert_handler_smoke.3082095904
Short name	T665
Test name
Test status
Simulation time	369516292 ps
CPU time	14.47 seconds
Started	Apr 30 02:21:45 PM PDT 24
Finished	Apr 30 02:22:00 PM PDT 24
Peak memory	248968 kb
Host	smart-f983d99c-eac4-4c0b-b4f1-39f758d568f0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30820 95904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.3082095904
Directory	/workspace/10.alert_handler_smoke/latest

Test location	/workspace/coverage/default/11.alert_handler_entropy.212890591
Short name	T683
Test name
Test status
Simulation time	138823107765 ps
CPU time	1726.95 seconds
Started	Apr 30 02:21:46 PM PDT 24
Finished	Apr 30 02:50:34 PM PDT 24
Peak memory	288672 kb
Host	smart-a4179f8e-9a32-413f-b5c3-68d4bc22972f
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=212890591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.212890591
Directory	/workspace/11.alert_handler_entropy/latest

Test location	/workspace/coverage/default/11.alert_handler_entropy_stress.1250810640
Short name	T60
Test name
Test status
Simulation time	389600392 ps
CPU time	10.95 seconds
Started	Apr 30 02:22:02 PM PDT 24
Finished	Apr 30 02:22:13 PM PDT 24
Peak memory	248708 kb
Host	smart-58acb560-8ca0-4030-a0df-e179c3b9dd4c
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1250810640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.1250810640
Directory	/workspace/11.alert_handler_entropy_stress/latest

Test location	/workspace/coverage/default/11.alert_handler_esc_alert_accum.3628964328
Short name	T694
Test name
Test status
Simulation time	4408715812 ps
CPU time	258.14 seconds
Started	Apr 30 02:21:48 PM PDT 24
Finished	Apr 30 02:26:07 PM PDT 24
Peak memory	256920 kb
Host	smart-e993d5e1-47f8-4dab-8031-46718f10ebc6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36289 64328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.3628964328
Directory	/workspace/11.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/11.alert_handler_esc_intr_timeout.797554825
Short name	T109
Test name
Test status
Simulation time	1841817358 ps
CPU time	28.75 seconds
Started	Apr 30 02:21:45 PM PDT 24
Finished	Apr 30 02:22:15 PM PDT 24
Peak memory	255364 kb
Host	smart-9957ef54-eb9f-4ca0-b8c2-4cd2324ebd0e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79755 4825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.797554825
Directory	/workspace/11.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/11.alert_handler_lpg_stub_clk.1423799647
Short name	T226
Test name
Test status
Simulation time	52465403583 ps
CPU time	1634.56 seconds
Started	Apr 30 02:21:45 PM PDT 24
Finished	Apr 30 02:49:00 PM PDT 24
Peak memory	273268 kb
Host	smart-4d6c7e59-c642-4340-b5fc-789127983d41
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1423799647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.1423799647
Directory	/workspace/11.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/11.alert_handler_random_alerts.1903530087
Short name	T503
Test name
Test status
Simulation time	1542344497 ps
CPU time	28.38 seconds
Started	Apr 30 02:21:46 PM PDT 24
Finished	Apr 30 02:22:15 PM PDT 24
Peak memory	248728 kb
Host	smart-c45a6f6d-03d1-44e4-bc52-37cded023933
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19035 30087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.1903530087
Directory	/workspace/11.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/11.alert_handler_random_classes.1917150682
Short name	T434
Test name
Test status
Simulation time	30086488 ps
CPU time	3.23 seconds
Started	Apr 30 02:21:45 PM PDT 24
Finished	Apr 30 02:21:49 PM PDT 24
Peak memory	240444 kb
Host	smart-0dd0d351-bbde-45ad-a822-121d8ce9ad4a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19171 50682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.1917150682
Directory	/workspace/11.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/11.alert_handler_sig_int_fail.2010474254
Short name	T225
Test name
Test status
Simulation time	262763486 ps
CPU time	33.89 seconds
Started	Apr 30 02:21:44 PM PDT 24
Finished	Apr 30 02:22:18 PM PDT 24
Peak memory	248704 kb
Host	smart-b8bca0ab-c292-46ce-9469-d70918d80264
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20104 74254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.2010474254
Directory	/workspace/11.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/11.alert_handler_smoke.1143871634
Short name	T309
Test name
Test status
Simulation time	858852472 ps
CPU time	58.85 seconds
Started	Apr 30 02:21:46 PM PDT 24
Finished	Apr 30 02:22:46 PM PDT 24
Peak memory	248872 kb
Host	smart-d4638349-60d3-4ae1-9a56-466c7d57d62a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11438 71634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.1143871634
Directory	/workspace/11.alert_handler_smoke/latest

Test location	/workspace/coverage/default/11.alert_handler_stress_all.1112684433
Short name	T45
Test name
Test status
Simulation time	44816264583 ps
CPU time	2458.57 seconds
Started	Apr 30 02:21:46 PM PDT 24
Finished	Apr 30 03:02:45 PM PDT 24
Peak memory	289624 kb
Host	smart-cbc3f5b2-5a27-44cf-bcf2-11fa972794b0
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112684433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha ndler_stress_all.1112684433
Directory	/workspace/11.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.621379007
Short name	T313
Test name
Test status
Simulation time	22570785188 ps
CPU time	2433.61 seconds
Started	Apr 30 02:21:48 PM PDT 24
Finished	Apr 30 03:02:23 PM PDT 24
Peak memory	305568 kb
Host	smart-f15a7706-f384-42f0-beea-75e4342726a7
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621379007 -assert nopostproc +UVM_TESTNAME=alert _handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.621379007
Directory	/workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/12.alert_handler_alert_accum_saturation.1155453694
Short name	T243
Test name
Test status
Simulation time	12508129 ps
CPU time	2.34 seconds
Started	Apr 30 02:21:54 PM PDT 24
Finished	Apr 30 02:21:57 PM PDT 24
Peak memory	248884 kb
Host	smart-93d269bd-a82c-406d-99ec-c47d04bfd4a7
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1155453694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.1155453694
Directory	/workspace/12.alert_handler_alert_accum_saturation/latest

Test location	/workspace/coverage/default/12.alert_handler_entropy.3140020782
Short name	T494
Test name
Test status
Simulation time	112191943041 ps
CPU time	1791.32 seconds
Started	Apr 30 02:21:55 PM PDT 24
Finished	Apr 30 02:51:47 PM PDT 24
Peak memory	273380 kb
Host	smart-7aa1d14d-4d5b-4864-85e0-c0c35b4dafff
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3140020782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.3140020782
Directory	/workspace/12.alert_handler_entropy/latest

Test location	/workspace/coverage/default/12.alert_handler_entropy_stress.3032754227
Short name	T647
Test name
Test status
Simulation time	185477086 ps
CPU time	11.79 seconds
Started	Apr 30 02:21:48 PM PDT 24
Finished	Apr 30 02:22:00 PM PDT 24
Peak memory	240552 kb
Host	smart-ec9afe01-3cc2-4a58-8000-edab026901c4
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3032754227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.3032754227
Directory	/workspace/12.alert_handler_entropy_stress/latest

Test location	/workspace/coverage/default/12.alert_handler_esc_alert_accum.1233891797
Short name	T315
Test name
Test status
Simulation time	6629783747 ps
CPU time	141.46 seconds
Started	Apr 30 02:21:45 PM PDT 24
Finished	Apr 30 02:24:07 PM PDT 24
Peak memory	251196 kb
Host	smart-4590095d-ee01-4662-8ad1-1bf37bc5e5e8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12338 91797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.1233891797
Directory	/workspace/12.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/12.alert_handler_esc_intr_timeout.2253677808
Short name	T551
Test name
Test status
Simulation time	844899580 ps
CPU time	24.69 seconds
Started	Apr 30 02:21:46 PM PDT 24
Finished	Apr 30 02:22:11 PM PDT 24
Peak memory	249156 kb
Host	smart-db6c4405-df37-4903-af26-d426ea754457
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22536 77808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.2253677808
Directory	/workspace/12.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/12.alert_handler_lpg.48934447
Short name	T368
Test name
Test status
Simulation time	14814514024 ps
CPU time	1336.08 seconds
Started	Apr 30 02:21:45 PM PDT 24
Finished	Apr 30 02:44:02 PM PDT 24
Peak memory	288812 kb
Host	smart-26bc1a56-879f-4e03-b0dc-390ef29fb930
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=48934447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.48934447
Directory	/workspace/12.alert_handler_lpg/latest

Test location	/workspace/coverage/default/12.alert_handler_lpg_stub_clk.4052498782
Short name	T66
Test name
Test status
Simulation time	98452940094 ps
CPU time	2538.54 seconds
Started	Apr 30 02:21:48 PM PDT 24
Finished	Apr 30 03:04:08 PM PDT 24
Peak memory	289064 kb
Host	smart-2bf08581-5710-4867-87ed-f9503ce555d9
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4052498782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.4052498782
Directory	/workspace/12.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/12.alert_handler_ping_timeout.3129109252
Short name	T695
Test name
Test status
Simulation time	12026352405 ps
CPU time	239.52 seconds
Started	Apr 30 02:21:46 PM PDT 24
Finished	Apr 30 02:25:46 PM PDT 24
Peak memory	247864 kb
Host	smart-1962f73d-74a6-49f9-9d14-b3d4592f68ce
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3129109252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.3129109252
Directory	/workspace/12.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/12.alert_handler_random_alerts.705522398
Short name	T114
Test name
Test status
Simulation time	220529892 ps
CPU time	26.44 seconds
Started	Apr 30 02:21:49 PM PDT 24
Finished	Apr 30 02:22:16 PM PDT 24
Peak memory	248644 kb
Host	smart-2150c15f-6132-43bc-8301-e79ff59345a1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70552 2398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.705522398
Directory	/workspace/12.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/12.alert_handler_sig_int_fail.3091430670
Short name	T462
Test name
Test status
Simulation time	1952172747 ps
CPU time	31.26 seconds
Started	Apr 30 02:21:46 PM PDT 24
Finished	Apr 30 02:22:18 PM PDT 24
Peak memory	248700 kb
Host	smart-c258673a-1ace-48cf-8e4c-5d9e87d99719
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30914 30670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.3091430670
Directory	/workspace/12.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/12.alert_handler_smoke.1442235853
Short name	T616
Test name
Test status
Simulation time	323612597 ps
CPU time	27.33 seconds
Started	Apr 30 02:21:54 PM PDT 24
Finished	Apr 30 02:22:22 PM PDT 24
Peak memory	248824 kb
Host	smart-8275522a-ccba-4a40-b376-1d3c7c2a09e2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14422 35853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.1442235853
Directory	/workspace/12.alert_handler_smoke/latest

Test location	/workspace/coverage/default/12.alert_handler_stress_all.3162033294
Short name	T94
Test name
Test status
Simulation time	40794292818 ps
CPU time	2662.52 seconds
Started	Apr 30 02:21:57 PM PDT 24
Finished	Apr 30 03:06:20 PM PDT 24
Peak memory	289472 kb
Host	smart-47135757-82a9-498f-a8a8-7b16638ccfc0
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162033294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha ndler_stress_all.3162033294
Directory	/workspace/12.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/13.alert_handler_alert_accum_saturation.1154192083
Short name	T248
Test name
Test status
Simulation time	38638428 ps
CPU time	3.97 seconds
Started	Apr 30 02:21:49 PM PDT 24
Finished	Apr 30 02:21:54 PM PDT 24
Peak memory	248848 kb
Host	smart-6288cf15-c371-474b-a935-c5006b4dbb40
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1154192083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.1154192083
Directory	/workspace/13.alert_handler_alert_accum_saturation/latest

Test location	/workspace/coverage/default/13.alert_handler_entropy.504834392
Short name	T640
Test name
Test status
Simulation time	54136119136 ps
CPU time	3080.52 seconds
Started	Apr 30 02:21:50 PM PDT 24
Finished	Apr 30 03:13:11 PM PDT 24
Peak memory	289140 kb
Host	smart-370ea2d5-b3ec-4a07-af3a-82a3201e2e29
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=504834392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.504834392
Directory	/workspace/13.alert_handler_entropy/latest

Test location	/workspace/coverage/default/13.alert_handler_entropy_stress.3065373222
Short name	T633
Test name
Test status
Simulation time	100143531 ps
CPU time	7.27 seconds
Started	Apr 30 02:21:51 PM PDT 24
Finished	Apr 30 02:21:58 PM PDT 24
Peak memory	240484 kb
Host	smart-4d229aed-069e-46ae-96d0-fbb8fae82ddd
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3065373222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.3065373222
Directory	/workspace/13.alert_handler_entropy_stress/latest

Test location	/workspace/coverage/default/13.alert_handler_esc_alert_accum.178506328
Short name	T448
Test name
Test status
Simulation time	84000765 ps
CPU time	2.97 seconds
Started	Apr 30 02:21:52 PM PDT 24
Finished	Apr 30 02:21:55 PM PDT 24
Peak memory	240488 kb
Host	smart-1dc19c21-a5d8-453d-9c71-7d3b8d2fb9fe
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17850 6328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.178506328
Directory	/workspace/13.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/13.alert_handler_esc_intr_timeout.2821033735
Short name	T631
Test name
Test status
Simulation time	4098056745 ps
CPU time	58.34 seconds
Started	Apr 30 02:22:02 PM PDT 24
Finished	Apr 30 02:23:01 PM PDT 24
Peak memory	256156 kb
Host	smart-03cf542c-0f18-4fec-9618-c8f0dbdb7736
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28210 33735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.2821033735
Directory	/workspace/13.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/13.alert_handler_lpg.3489951349
Short name	T256
Test name
Test status
Simulation time	43461202338 ps
CPU time	1023.88 seconds
Started	Apr 30 02:21:53 PM PDT 24
Finished	Apr 30 02:38:58 PM PDT 24
Peak memory	282380 kb
Host	smart-fbf42c54-02c1-4776-9a8e-0fbb3cf94241
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3489951349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.3489951349
Directory	/workspace/13.alert_handler_lpg/latest

Test location	/workspace/coverage/default/13.alert_handler_lpg_stub_clk.2772324889
Short name	T481
Test name
Test status
Simulation time	25644667941 ps
CPU time	1652.08 seconds
Started	Apr 30 02:21:50 PM PDT 24
Finished	Apr 30 02:49:23 PM PDT 24
Peak memory	273300 kb
Host	smart-3c3cc1a9-3782-40af-b128-5e41890998e0
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2772324889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.2772324889
Directory	/workspace/13.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/13.alert_handler_ping_timeout.813953634
Short name	T345
Test name
Test status
Simulation time	47449839680 ps
CPU time	477.19 seconds
Started	Apr 30 02:21:56 PM PDT 24
Finished	Apr 30 02:29:53 PM PDT 24
Peak memory	247856 kb
Host	smart-0e7917fa-3b21-45d2-945b-b3ff6bfe129a
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=813953634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.813953634
Directory	/workspace/13.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/13.alert_handler_random_alerts.2107734531
Short name	T710
Test name
Test status
Simulation time	2149680493 ps
CPU time	21.22 seconds
Started	Apr 30 02:22:01 PM PDT 24
Finished	Apr 30 02:22:23 PM PDT 24
Peak memory	248704 kb
Host	smart-6006d481-aacc-4be8-823e-e2dbb866d4ea
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21077 34531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.2107734531
Directory	/workspace/13.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/13.alert_handler_random_classes.1313759770
Short name	T429
Test name
Test status
Simulation time	1769708443 ps
CPU time	27.07 seconds
Started	Apr 30 02:21:51 PM PDT 24
Finished	Apr 30 02:22:19 PM PDT 24
Peak memory	255960 kb
Host	smart-de660520-6974-42d3-bee0-18f17d458311
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13137 59770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.1313759770
Directory	/workspace/13.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/13.alert_handler_sig_int_fail.3690977813
Short name	T11
Test name
Test status
Simulation time	110254808 ps
CPU time	14.46 seconds
Started	Apr 30 02:21:50 PM PDT 24
Finished	Apr 30 02:22:05 PM PDT 24
Peak memory	248652 kb
Host	smart-f38a0382-50b3-4102-90cd-92365bf1acfa
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36909 77813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.3690977813
Directory	/workspace/13.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/13.alert_handler_smoke.2963698566
Short name	T100
Test name
Test status
Simulation time	1538308452 ps
CPU time	43.85 seconds
Started	Apr 30 02:21:48 PM PDT 24
Finished	Apr 30 02:22:33 PM PDT 24
Peak memory	256060 kb
Host	smart-3822abfb-fb5b-4642-aa95-34442e96d2f0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29636 98566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.2963698566
Directory	/workspace/13.alert_handler_smoke/latest

Test location	/workspace/coverage/default/14.alert_handler_alert_accum_saturation.1950568011
Short name	T236
Test name
Test status
Simulation time	255233078 ps
CPU time	3.74 seconds
Started	Apr 30 02:21:49 PM PDT 24
Finished	Apr 30 02:21:53 PM PDT 24
Peak memory	248872 kb
Host	smart-be3ee4f1-7a64-4749-ba90-d79edbe186d8
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1950568011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.1950568011
Directory	/workspace/14.alert_handler_alert_accum_saturation/latest

Test location	/workspace/coverage/default/14.alert_handler_entropy.3150139167
Short name	T657
Test name
Test status
Simulation time	59326867686 ps
CPU time	2944.33 seconds
Started	Apr 30 02:22:03 PM PDT 24
Finished	Apr 30 03:11:08 PM PDT 24
Peak memory	289384 kb
Host	smart-7c265a80-2d35-42bd-b8bb-53d0d47e927c
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3150139167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.3150139167
Directory	/workspace/14.alert_handler_entropy/latest

Test location	/workspace/coverage/default/14.alert_handler_entropy_stress.1296213209
Short name	T602
Test name
Test status
Simulation time	345747750 ps
CPU time	16.91 seconds
Started	Apr 30 02:22:08 PM PDT 24
Finished	Apr 30 02:22:25 PM PDT 24
Peak memory	248668 kb
Host	smart-14a4aeaa-bc68-4430-8f00-fdccbac3f1b9
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1296213209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.1296213209
Directory	/workspace/14.alert_handler_entropy_stress/latest

Test location	/workspace/coverage/default/14.alert_handler_esc_alert_accum.3349828087
Short name	T593
Test name
Test status
Simulation time	220214388 ps
CPU time	13.87 seconds
Started	Apr 30 02:21:58 PM PDT 24
Finished	Apr 30 02:22:12 PM PDT 24
Peak memory	249068 kb
Host	smart-6497da62-33dc-4d27-bdaa-8f470d096cbd
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33498 28087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.3349828087
Directory	/workspace/14.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/14.alert_handler_esc_intr_timeout.3318776847
Short name	T207
Test name
Test status
Simulation time	966283103 ps
CPU time	31.39 seconds
Started	Apr 30 02:21:47 PM PDT 24
Finished	Apr 30 02:22:19 PM PDT 24
Peak memory	255888 kb
Host	smart-3c0d8a1a-c5f0-4fff-afe9-bf5ec266574a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33187 76847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.3318776847
Directory	/workspace/14.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/14.alert_handler_lpg.258463814
Short name	T357
Test name
Test status
Simulation time	29899586960 ps
CPU time	1552.96 seconds
Started	Apr 30 02:21:49 PM PDT 24
Finished	Apr 30 02:47:43 PM PDT 24
Peak memory	272748 kb
Host	smart-91e2b2c6-ee27-44b9-8bd4-2d81445db6e9
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=258463814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.258463814
Directory	/workspace/14.alert_handler_lpg/latest

Test location	/workspace/coverage/default/14.alert_handler_lpg_stub_clk.330005260
Short name	T550
Test name
Test status
Simulation time	13503532205 ps
CPU time	1136.02 seconds
Started	Apr 30 02:21:58 PM PDT 24
Finished	Apr 30 02:40:55 PM PDT 24
Peak memory	288592 kb
Host	smart-c88ef1c1-cb77-4d53-bbaf-daf8ac99b514
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=330005260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.330005260
Directory	/workspace/14.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/14.alert_handler_ping_timeout.731382913
Short name	T1
Test name
Test status
Simulation time	6803365242 ps
CPU time	145.12 seconds
Started	Apr 30 02:22:04 PM PDT 24
Finished	Apr 30 02:24:30 PM PDT 24
Peak memory	253636 kb
Host	smart-b2fcab15-0095-4fd1-bb45-937914c0685d
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=731382913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.731382913
Directory	/workspace/14.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/14.alert_handler_random_alerts.3954564537
Short name	T222
Test name
Test status
Simulation time	249765444 ps
CPU time	12.81 seconds
Started	Apr 30 02:21:45 PM PDT 24
Finished	Apr 30 02:21:58 PM PDT 24
Peak memory	248680 kb
Host	smart-69d07bc2-1e7d-4957-bdc4-1b8eb304faaa
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39545 64537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.3954564537
Directory	/workspace/14.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/14.alert_handler_random_classes.206168103
Short name	T584
Test name
Test status
Simulation time	2330666436 ps
CPU time	57.26 seconds
Started	Apr 30 02:21:53 PM PDT 24
Finished	Apr 30 02:22:51 PM PDT 24
Peak memory	256116 kb
Host	smart-e9ad4bcb-60be-4ecc-83f4-439bbc735765
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20616 8103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.206168103
Directory	/workspace/14.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/14.alert_handler_sig_int_fail.1207601853
Short name	T402
Test name
Test status
Simulation time	586375567 ps
CPU time	32.7 seconds
Started	Apr 30 02:21:46 PM PDT 24
Finished	Apr 30 02:22:20 PM PDT 24
Peak memory	249004 kb
Host	smart-3bacce88-b9a9-4b9f-8508-221a04e60bf9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12076 01853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.1207601853
Directory	/workspace/14.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/14.alert_handler_smoke.2750003073
Short name	T202
Test name
Test status
Simulation time	1259407409 ps
CPU time	35.96 seconds
Started	Apr 30 02:21:48 PM PDT 24
Finished	Apr 30 02:22:25 PM PDT 24
Peak memory	256516 kb
Host	smart-172529d8-eb0e-4b5c-99c0-6d9ee3cbbc91
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27500 03073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.2750003073
Directory	/workspace/14.alert_handler_smoke/latest

Test location	/workspace/coverage/default/14.alert_handler_stress_all.2085602222
Short name	T203
Test name
Test status
Simulation time	587211049810 ps
CPU time	3906.12 seconds
Started	Apr 30 02:21:48 PM PDT 24
Finished	Apr 30 03:26:56 PM PDT 24
Peak memory	300908 kb
Host	smart-6b1290b6-f951-47cf-a296-f5295eded58a
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085602222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha ndler_stress_all.2085602222
Directory	/workspace/14.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/15.alert_handler_alert_accum_saturation.23943607
Short name	T247
Test name
Test status
Simulation time	98300332 ps
CPU time	3.68 seconds
Started	Apr 30 02:22:09 PM PDT 24
Finished	Apr 30 02:22:13 PM PDT 24
Peak memory	248916 kb
Host	smart-c3341adb-158a-4518-9a1e-13461e6b92a7
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=23943607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.23943607
Directory	/workspace/15.alert_handler_alert_accum_saturation/latest

Test location	/workspace/coverage/default/15.alert_handler_entropy.2786632869
Short name	T397
Test name
Test status
Simulation time	51439601051 ps
CPU time	2134.11 seconds
Started	Apr 30 02:21:58 PM PDT 24
Finished	Apr 30 02:57:33 PM PDT 24
Peak memory	273348 kb
Host	smart-dbb5f42d-7e80-4d05-9ae4-f2cd322fd46c
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2786632869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.2786632869
Directory	/workspace/15.alert_handler_entropy/latest

Test location	/workspace/coverage/default/15.alert_handler_entropy_stress.3377793569
Short name	T523
Test name
Test status
Simulation time	224086451 ps
CPU time	12.86 seconds
Started	Apr 30 02:21:52 PM PDT 24
Finished	Apr 30 02:22:05 PM PDT 24
Peak memory	248732 kb
Host	smart-79743caa-6ac7-4e4b-886e-bc26bfab750e
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3377793569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.3377793569
Directory	/workspace/15.alert_handler_entropy_stress/latest

Test location	/workspace/coverage/default/15.alert_handler_esc_alert_accum.1487620527
Short name	T442
Test name
Test status
Simulation time	22325428566 ps
CPU time	326.94 seconds
Started	Apr 30 02:21:51 PM PDT 24
Finished	Apr 30 02:27:18 PM PDT 24
Peak memory	256964 kb
Host	smart-3c4bb7b7-7213-44f1-87eb-3a3d30e211e3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14876 20527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.1487620527
Directory	/workspace/15.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/15.alert_handler_esc_intr_timeout.403335162
Short name	T592
Test name
Test status
Simulation time	117087252 ps
CPU time	10.62 seconds
Started	Apr 30 02:22:03 PM PDT 24
Finished	Apr 30 02:22:14 PM PDT 24
Peak memory	254656 kb
Host	smart-5088e32b-01c2-4fc5-bb5d-5dae822837bc
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40333 5162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.403335162
Directory	/workspace/15.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/15.alert_handler_lpg_stub_clk.3832665433
Short name	T262
Test name
Test status
Simulation time	41603550401 ps
CPU time	2620.35 seconds
Started	Apr 30 02:21:55 PM PDT 24
Finished	Apr 30 03:05:36 PM PDT 24
Peak memory	288908 kb
Host	smart-2ef6c406-fe9a-494f-8f1a-edeaf5a65efc
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3832665433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.3832665433
Directory	/workspace/15.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/15.alert_handler_ping_timeout.375384523
Short name	T54
Test name
Test status
Simulation time	2579663150 ps
CPU time	108.46 seconds
Started	Apr 30 02:21:54 PM PDT 24
Finished	Apr 30 02:23:43 PM PDT 24
Peak memory	247804 kb
Host	smart-be2bd507-9457-493e-916d-9640043efea4
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=375384523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.375384523
Directory	/workspace/15.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/15.alert_handler_random_alerts.153527614
Short name	T488
Test name
Test status
Simulation time	62809564 ps
CPU time	4.46 seconds
Started	Apr 30 02:21:56 PM PDT 24
Finished	Apr 30 02:22:01 PM PDT 24
Peak memory	240456 kb
Host	smart-a3e6b9d7-d3f8-44f9-8e64-969d5c23d3de
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15352 7614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.153527614
Directory	/workspace/15.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/15.alert_handler_random_classes.2668443202
Short name	T601
Test name
Test status
Simulation time	558691489 ps
CPU time	9.86 seconds
Started	Apr 30 02:21:52 PM PDT 24
Finished	Apr 30 02:22:02 PM PDT 24
Peak memory	248808 kb
Host	smart-5cec76d1-abcc-46f1-b2c0-3c67b55e4045
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26684 43202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.2668443202
Directory	/workspace/15.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/15.alert_handler_sig_int_fail.3565762661
Short name	T492
Test name
Test status
Simulation time	1038195800 ps
CPU time	28.58 seconds
Started	Apr 30 02:21:52 PM PDT 24
Finished	Apr 30 02:22:21 PM PDT 24
Peak memory	256632 kb
Host	smart-95896071-2c92-47f7-a7e4-567dfb758797
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35657 62661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.3565762661
Directory	/workspace/15.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/15.alert_handler_smoke.1571116327
Short name	T578
Test name
Test status
Simulation time	236804650 ps
CPU time	14.25 seconds
Started	Apr 30 02:21:57 PM PDT 24
Finished	Apr 30 02:22:12 PM PDT 24
Peak memory	254072 kb
Host	smart-23721dd1-29a0-49c6-82e0-b041bdbbe14b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15711 16327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.1571116327
Directory	/workspace/15.alert_handler_smoke/latest

Test location	/workspace/coverage/default/15.alert_handler_stress_all.96174334
Short name	T399
Test name
Test status
Simulation time	134864092645 ps
CPU time	1982.54 seconds
Started	Apr 30 02:21:53 PM PDT 24
Finished	Apr 30 02:54:56 PM PDT 24
Peak memory	289732 kb
Host	smart-1cc62532-f346-4f99-8704-2789acf79704
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96174334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_hand ler_stress_all.96174334
Directory	/workspace/15.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.356643772
Short name	T37
Test name
Test status
Simulation time	202856093918 ps
CPU time	2974.37 seconds
Started	Apr 30 02:21:56 PM PDT 24
Finished	Apr 30 03:11:31 PM PDT 24
Peak memory	285104 kb
Host	smart-f30bfffa-97e3-4a2f-99f0-f61f7001e5c9
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356643772 -assert nopostproc +UVM_TESTNAME=alert _handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.356643772
Directory	/workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/16.alert_handler_alert_accum_saturation.1301293564
Short name	T250
Test name
Test status
Simulation time	74708853 ps
CPU time	3.56 seconds
Started	Apr 30 02:21:52 PM PDT 24
Finished	Apr 30 02:21:56 PM PDT 24
Peak memory	248848 kb
Host	smart-bf9746cb-24d8-435d-a264-de6abb8de93c
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1301293564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.1301293564
Directory	/workspace/16.alert_handler_alert_accum_saturation/latest

Test location	/workspace/coverage/default/16.alert_handler_entropy.1452774559
Short name	T13
Test name
Test status
Simulation time	10951973856 ps
CPU time	1106.35 seconds
Started	Apr 30 02:22:10 PM PDT 24
Finished	Apr 30 02:40:37 PM PDT 24
Peak memory	283580 kb
Host	smart-60676cc1-0924-4941-892f-8f7445e93f9b
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1452774559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.1452774559
Directory	/workspace/16.alert_handler_entropy/latest

Test location	/workspace/coverage/default/16.alert_handler_entropy_stress.1559127695
Short name	T447
Test name
Test status
Simulation time	2061922931 ps
CPU time	15.48 seconds
Started	Apr 30 02:21:53 PM PDT 24
Finished	Apr 30 02:22:09 PM PDT 24
Peak memory	240464 kb
Host	smart-4c7ea452-b183-4a97-8cf2-8d92d6484ec8
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1559127695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.1559127695
Directory	/workspace/16.alert_handler_entropy_stress/latest

Test location	/workspace/coverage/default/16.alert_handler_esc_alert_accum.2514382957
Short name	T452
Test name
Test status
Simulation time	150774687 ps
CPU time	4.79 seconds
Started	Apr 30 02:22:02 PM PDT 24
Finished	Apr 30 02:22:07 PM PDT 24
Peak memory	240524 kb
Host	smart-bfaa9b22-a441-42a6-a887-e271ff416655
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25143 82957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.2514382957
Directory	/workspace/16.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/16.alert_handler_esc_intr_timeout.3808071779
Short name	T626
Test name
Test status
Simulation time	1161008167 ps
CPU time	68.15 seconds
Started	Apr 30 02:21:50 PM PDT 24
Finished	Apr 30 02:22:59 PM PDT 24
Peak memory	255964 kb
Host	smart-b8655f7f-f4a8-43d6-b8e1-aa99467eb49e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38080 71779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.3808071779
Directory	/workspace/16.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/16.alert_handler_lpg.2224284878
Short name	T367
Test name
Test status
Simulation time	19480878755 ps
CPU time	1231.16 seconds
Started	Apr 30 02:21:53 PM PDT 24
Finished	Apr 30 02:42:25 PM PDT 24
Peak memory	265220 kb
Host	smart-8889fce1-030c-4470-a04b-60de9f9575f5
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2224284878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.2224284878
Directory	/workspace/16.alert_handler_lpg/latest

Test location	/workspace/coverage/default/16.alert_handler_lpg_stub_clk.81155396
Short name	T679
Test name
Test status
Simulation time	14779485337 ps
CPU time	1178.72 seconds
Started	Apr 30 02:22:12 PM PDT 24
Finished	Apr 30 02:41:51 PM PDT 24
Peak memory	288720 kb
Host	smart-c7f644a7-f65a-40a6-ba56-85649b4c0cad
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=81155396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.81155396
Directory	/workspace/16.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/16.alert_handler_ping_timeout.2097594261
Short name	T353
Test name
Test status
Simulation time	26385752884 ps
CPU time	561.09 seconds
Started	Apr 30 02:21:57 PM PDT 24
Finished	Apr 30 02:31:19 PM PDT 24
Peak memory	247052 kb
Host	smart-855c558c-89db-48de-8197-401a3d4b43e4
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2097594261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.2097594261
Directory	/workspace/16.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/16.alert_handler_random_alerts.4267359659
Short name	T500
Test name
Test status
Simulation time	1265146605 ps
CPU time	33.07 seconds
Started	Apr 30 02:21:58 PM PDT 24
Finished	Apr 30 02:22:31 PM PDT 24
Peak memory	256852 kb
Host	smart-989eced0-9508-47c5-8858-ab2227a327a1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42673 59659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.4267359659
Directory	/workspace/16.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/16.alert_handler_random_classes.2347195858
Short name	T460
Test name
Test status
Simulation time	4820717994 ps
CPU time	49.29 seconds
Started	Apr 30 02:22:09 PM PDT 24
Finished	Apr 30 02:22:58 PM PDT 24
Peak memory	256964 kb
Host	smart-4e4672a5-ae7d-412a-ae14-e96d9e71682b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23471 95858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.2347195858
Directory	/workspace/16.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/16.alert_handler_sig_int_fail.2675725578
Short name	T272
Test name
Test status
Simulation time	585731837 ps
CPU time	17.4 seconds
Started	Apr 30 02:21:57 PM PDT 24
Finished	Apr 30 02:22:15 PM PDT 24
Peak memory	248704 kb
Host	smart-074924ae-5136-4898-bec3-a6babd57a4a2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26757 25578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.2675725578
Directory	/workspace/16.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/16.alert_handler_smoke.799141287
Short name	T384
Test name
Test status
Simulation time	188642101 ps
CPU time	3.97 seconds
Started	Apr 30 02:22:02 PM PDT 24
Finished	Apr 30 02:22:06 PM PDT 24
Peak memory	240456 kb
Host	smart-06b29c11-f70c-4079-a960-22f0ca6fd1d4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79914 1287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.799141287
Directory	/workspace/16.alert_handler_smoke/latest

Test location	/workspace/coverage/default/16.alert_handler_stress_all.3407869898
Short name	T560
Test name
Test status
Simulation time	19448866989 ps
CPU time	2031.39 seconds
Started	Apr 30 02:21:51 PM PDT 24
Finished	Apr 30 02:55:44 PM PDT 24
Peak memory	305804 kb
Host	smart-29670b37-21a6-46d3-a634-88501e92cbf7
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407869898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha ndler_stress_all.3407869898
Directory	/workspace/16.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.1918606863
Short name	T130
Test name
Test status
Simulation time	73576873788 ps
CPU time	6249.09 seconds
Started	Apr 30 02:21:56 PM PDT 24
Finished	Apr 30 04:06:06 PM PDT 24
Peak memory	330216 kb
Host	smart-88dbe7b4-a398-4ae9-81b5-6bd33291995f
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918606863 -assert nopostproc +UVM_TESTNAME=aler t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.1918606863
Directory	/workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/17.alert_handler_alert_accum_saturation.95853309
Short name	T245
Test name
Test status
Simulation time	264559435 ps
CPU time	3.53 seconds
Started	Apr 30 02:21:55 PM PDT 24
Finished	Apr 30 02:21:59 PM PDT 24
Peak memory	248924 kb
Host	smart-ac78a65c-7c26-4f06-9862-c39f0e28b508
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=95853309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.95853309
Directory	/workspace/17.alert_handler_alert_accum_saturation/latest

Test location	/workspace/coverage/default/17.alert_handler_entropy.3298299990
Short name	T406
Test name
Test status
Simulation time	132796709917 ps
CPU time	1907.55 seconds
Started	Apr 30 02:21:58 PM PDT 24
Finished	Apr 30 02:53:46 PM PDT 24
Peak memory	272660 kb
Host	smart-c9372e33-c00e-49f4-962e-fd1a5270d86e
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3298299990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.3298299990
Directory	/workspace/17.alert_handler_entropy/latest

Test location	/workspace/coverage/default/17.alert_handler_entropy_stress.1226975243
Short name	T535
Test name
Test status
Simulation time	1004639680 ps
CPU time	13.08 seconds
Started	Apr 30 02:21:54 PM PDT 24
Finished	Apr 30 02:22:08 PM PDT 24
Peak memory	248668 kb
Host	smart-c1ff5ca4-96a2-486c-88e3-3a84e29d8afc
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1226975243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.1226975243
Directory	/workspace/17.alert_handler_entropy_stress/latest

Test location	/workspace/coverage/default/17.alert_handler_esc_alert_accum.507894047
Short name	T261
Test name
Test status
Simulation time	3860898390 ps
CPU time	149.47 seconds
Started	Apr 30 02:21:53 PM PDT 24
Finished	Apr 30 02:24:23 PM PDT 24
Peak memory	256916 kb
Host	smart-a4a5ae63-447b-4729-9500-858bcd93199b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50789 4047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.507894047
Directory	/workspace/17.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/17.alert_handler_esc_intr_timeout.2470340544
Short name	T502
Test name
Test status
Simulation time	342623037 ps
CPU time	26.86 seconds
Started	Apr 30 02:21:56 PM PDT 24
Finished	Apr 30 02:22:23 PM PDT 24
Peak memory	255896 kb
Host	smart-784113a2-f6e9-4a1a-91cf-30a583ab3f0d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24703 40544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.2470340544
Directory	/workspace/17.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/17.alert_handler_lpg.3263804058
Short name	T361
Test name
Test status
Simulation time	10315234175 ps
CPU time	729.82 seconds
Started	Apr 30 02:21:57 PM PDT 24
Finished	Apr 30 02:34:07 PM PDT 24
Peak memory	265136 kb
Host	smart-64bfb480-a59f-40be-81ec-6ad2b20e282f
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3263804058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.3263804058
Directory	/workspace/17.alert_handler_lpg/latest

Test location	/workspace/coverage/default/17.alert_handler_lpg_stub_clk.225291714
Short name	T587
Test name
Test status
Simulation time	216188417571 ps
CPU time	2283.27 seconds
Started	Apr 30 02:21:51 PM PDT 24
Finished	Apr 30 02:59:55 PM PDT 24
Peak memory	287156 kb
Host	smart-c28fc1bd-f55d-4e37-b436-7ad36f40a653
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=225291714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.225291714
Directory	/workspace/17.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/17.alert_handler_random_alerts.689848955
Short name	T319
Test name
Test status
Simulation time	483394196 ps
CPU time	20.22 seconds
Started	Apr 30 02:21:50 PM PDT 24
Finished	Apr 30 02:22:11 PM PDT 24
Peak memory	248728 kb
Host	smart-df38abbd-6574-483d-9c70-c2e494bd6730
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68984 8955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.689848955
Directory	/workspace/17.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/17.alert_handler_random_classes.1530582300
Short name	T556
Test name
Test status
Simulation time	2172313720 ps
CPU time	29.27 seconds
Started	Apr 30 02:22:07 PM PDT 24
Finished	Apr 30 02:22:36 PM PDT 24
Peak memory	254160 kb
Host	smart-7bd1cf5c-3314-4ff8-91d5-87672d83986e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15305 82300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.1530582300
Directory	/workspace/17.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/17.alert_handler_sig_int_fail.3631849037
Short name	T570
Test name
Test status
Simulation time	641324861 ps
CPU time	31.91 seconds
Started	Apr 30 02:21:49 PM PDT 24
Finished	Apr 30 02:22:22 PM PDT 24
Peak memory	255424 kb
Host	smart-615e4a76-2fda-4c1e-bf39-b65bb83afc9a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36318 49037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.3631849037
Directory	/workspace/17.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/17.alert_handler_smoke.3755137917
Short name	T686
Test name
Test status
Simulation time	110439440 ps
CPU time	9.19 seconds
Started	Apr 30 02:22:04 PM PDT 24
Finished	Apr 30 02:22:13 PM PDT 24
Peak memory	248728 kb
Host	smart-055380dc-85e6-41fb-b2ac-aeb38b9e510c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37551 37917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.3755137917
Directory	/workspace/17.alert_handler_smoke/latest

Test location	/workspace/coverage/default/18.alert_handler_alert_accum_saturation.2333322087
Short name	T246
Test name
Test status
Simulation time	83992130 ps
CPU time	2.42 seconds
Started	Apr 30 02:22:06 PM PDT 24
Finished	Apr 30 02:22:09 PM PDT 24
Peak memory	248804 kb
Host	smart-fa8d1e63-1c80-4d8c-a5a1-a33ddb4dccbd
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2333322087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.2333322087
Directory	/workspace/18.alert_handler_alert_accum_saturation/latest

Test location	/workspace/coverage/default/18.alert_handler_entropy.2624710187
Short name	T700
Test name
Test status
Simulation time	56614143303 ps
CPU time	1556.88 seconds
Started	Apr 30 02:21:58 PM PDT 24
Finished	Apr 30 02:47:56 PM PDT 24
Peak memory	268200 kb
Host	smart-b3ceb5ed-37f5-4463-a17a-25d2a72d365a
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2624710187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.2624710187
Directory	/workspace/18.alert_handler_entropy/latest

Test location	/workspace/coverage/default/18.alert_handler_entropy_stress.3490187807
Short name	T401
Test name
Test status
Simulation time	16861331345 ps
CPU time	50.86 seconds
Started	Apr 30 02:21:58 PM PDT 24
Finished	Apr 30 02:22:49 PM PDT 24
Peak memory	248744 kb
Host	smart-0594df6d-c0ff-49d1-a66c-b778a74e81fa
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3490187807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.3490187807
Directory	/workspace/18.alert_handler_entropy_stress/latest

Test location	/workspace/coverage/default/18.alert_handler_esc_alert_accum.3793906750
Short name	T472
Test name
Test status
Simulation time	3237717365 ps
CPU time	45.87 seconds
Started	Apr 30 02:21:58 PM PDT 24
Finished	Apr 30 02:22:45 PM PDT 24
Peak memory	248832 kb
Host	smart-0559c007-69bf-469b-9f7b-7e3da37394a0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37939 06750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.3793906750
Directory	/workspace/18.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/18.alert_handler_esc_intr_timeout.4255224498
Short name	T16
Test name
Test status
Simulation time	1749466577 ps
CPU time	27.47 seconds
Started	Apr 30 02:21:53 PM PDT 24
Finished	Apr 30 02:22:21 PM PDT 24
Peak memory	256104 kb
Host	smart-83cce91e-2dc7-448c-b25a-3214773ea0b9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42552 24498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.4255224498
Directory	/workspace/18.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/18.alert_handler_lpg.3079085034
Short name	T347
Test name
Test status
Simulation time	166699698588 ps
CPU time	2189.57 seconds
Started	Apr 30 02:22:08 PM PDT 24
Finished	Apr 30 02:58:38 PM PDT 24
Peak memory	289200 kb
Host	smart-f345a2c0-20a0-41cc-9869-a12584412ee1
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3079085034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.3079085034
Directory	/workspace/18.alert_handler_lpg/latest

Test location	/workspace/coverage/default/18.alert_handler_lpg_stub_clk.1216397678
Short name	T642
Test name
Test status
Simulation time	22648892103 ps
CPU time	1424.53 seconds
Started	Apr 30 02:21:57 PM PDT 24
Finished	Apr 30 02:45:42 PM PDT 24
Peak memory	273296 kb
Host	smart-242e4a31-f152-49b7-8c4e-e64a7c8078a1
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1216397678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.1216397678
Directory	/workspace/18.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/18.alert_handler_ping_timeout.1395067554
Short name	T125
Test name
Test status
Simulation time	19277617847 ps
CPU time	218.32 seconds
Started	Apr 30 02:21:53 PM PDT 24
Finished	Apr 30 02:25:31 PM PDT 24
Peak memory	247776 kb
Host	smart-295b783a-4530-4e00-a063-84ddbb587d7b
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1395067554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.1395067554
Directory	/workspace/18.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/18.alert_handler_random_alerts.3791989044
Short name	T589
Test name
Test status
Simulation time	645789578 ps
CPU time	43.06 seconds
Started	Apr 30 02:21:58 PM PDT 24
Finished	Apr 30 02:22:42 PM PDT 24
Peak memory	248664 kb
Host	smart-792e413f-cd1b-46da-a342-2932fb28e3e5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37919 89044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.3791989044
Directory	/workspace/18.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/18.alert_handler_random_classes.2269701827
Short name	T420
Test name
Test status
Simulation time	53576037 ps
CPU time	6 seconds
Started	Apr 30 02:21:49 PM PDT 24
Finished	Apr 30 02:21:56 PM PDT 24
Peak memory	251968 kb
Host	smart-237d4475-450c-4ce6-acf7-e3daeb332c6f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22697 01827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.2269701827
Directory	/workspace/18.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/18.alert_handler_sig_int_fail.3016659157
Short name	T99
Test name
Test status
Simulation time	2504272704 ps
CPU time	37.56 seconds
Started	Apr 30 02:22:04 PM PDT 24
Finished	Apr 30 02:22:42 PM PDT 24
Peak memory	248756 kb
Host	smart-d6aac1c6-5e3c-489e-b7c7-b2d6b1fd0192
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30166 59157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.3016659157
Directory	/workspace/18.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/18.alert_handler_smoke.2933409471
Short name	T82
Test name
Test status
Simulation time	502732907 ps
CPU time	12.05 seconds
Started	Apr 30 02:22:10 PM PDT 24
Finished	Apr 30 02:22:22 PM PDT 24
Peak memory	248872 kb
Host	smart-6bf21dce-9c80-4010-9b30-c3dee395a1f0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29334 09471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.2933409471
Directory	/workspace/18.alert_handler_smoke/latest

Test location	/workspace/coverage/default/18.alert_handler_stress_all.877881747
Short name	T107
Test name
Test status
Simulation time	21195901709 ps
CPU time	1891.35 seconds
Started	Apr 30 02:22:07 PM PDT 24
Finished	Apr 30 02:53:39 PM PDT 24
Peak memory	305328 kb
Host	smart-49500d0d-a330-4f52-960e-b048cbf17384
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877881747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_han dler_stress_all.877881747
Directory	/workspace/18.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.2827029448
Short name	T89
Test name
Test status
Simulation time	937547823942 ps
CPU time	4568.65 seconds
Started	Apr 30 02:22:05 PM PDT 24
Finished	Apr 30 03:38:15 PM PDT 24
Peak memory	305440 kb
Host	smart-f39bfedc-44f0-4b5c-b968-cc8eb0033afa
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827029448 -assert nopostproc +UVM_TESTNAME=aler t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.2827029448
Directory	/workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/19.alert_handler_entropy_stress.2993503149
Short name	T258
Test name
Test status
Simulation time	216056735 ps
CPU time	8.62 seconds
Started	Apr 30 02:22:04 PM PDT 24
Finished	Apr 30 02:22:13 PM PDT 24
Peak memory	248732 kb
Host	smart-48a08c55-f043-4630-8911-d76c9077eb4c
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2993503149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.2993503149
Directory	/workspace/19.alert_handler_entropy_stress/latest

Test location	/workspace/coverage/default/19.alert_handler_esc_alert_accum.4147396630
Short name	T36
Test name
Test status
Simulation time	2077646489 ps
CPU time	117.65 seconds
Started	Apr 30 02:21:59 PM PDT 24
Finished	Apr 30 02:23:57 PM PDT 24
Peak memory	256656 kb
Host	smart-83a1b8e3-4b75-491c-9ea9-7823b4099d8f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41473 96630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.4147396630
Directory	/workspace/19.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/19.alert_handler_esc_intr_timeout.4203294231
Short name	T489
Test name
Test status
Simulation time	2130609095 ps
CPU time	19.84 seconds
Started	Apr 30 02:21:52 PM PDT 24
Finished	Apr 30 02:22:12 PM PDT 24
Peak memory	248672 kb
Host	smart-cbacb66a-9191-4f77-a24f-9a5e4ecea9d0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42032 94231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.4203294231
Directory	/workspace/19.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/19.alert_handler_lpg.3172789347
Short name	T596
Test name
Test status
Simulation time	50150627359 ps
CPU time	926.14 seconds
Started	Apr 30 02:22:14 PM PDT 24
Finished	Apr 30 02:37:41 PM PDT 24
Peak memory	272432 kb
Host	smart-32dfc426-5817-4851-b383-182eed88dc96
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3172789347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.3172789347
Directory	/workspace/19.alert_handler_lpg/latest

Test location	/workspace/coverage/default/19.alert_handler_lpg_stub_clk.826139871
Short name	T62
Test name
Test status
Simulation time	734577896957 ps
CPU time	3327.51 seconds
Started	Apr 30 02:22:12 PM PDT 24
Finished	Apr 30 03:17:40 PM PDT 24
Peak memory	287652 kb
Host	smart-dd6be80b-10af-4d6b-a4c9-82f992e22bd2
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=826139871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.826139871
Directory	/workspace/19.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/19.alert_handler_ping_timeout.2756718751
Short name	T329
Test name
Test status
Simulation time	10114418338 ps
CPU time	419.69 seconds
Started	Apr 30 02:21:59 PM PDT 24
Finished	Apr 30 02:28:59 PM PDT 24
Peak memory	247792 kb
Host	smart-4b4aee83-6ce3-476d-bfc9-ef2eebd9b4ba
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2756718751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.2756718751
Directory	/workspace/19.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/19.alert_handler_random_alerts.3343611858
Short name	T466
Test name
Test status
Simulation time	2540550876 ps
CPU time	21.1 seconds
Started	Apr 30 02:22:09 PM PDT 24
Finished	Apr 30 02:22:31 PM PDT 24
Peak memory	254620 kb
Host	smart-daec748a-b57f-4d50-a6a2-b02b0a5ed3f5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33436 11858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.3343611858
Directory	/workspace/19.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/19.alert_handler_random_classes.2282174662
Short name	T534
Test name
Test status
Simulation time	266389516 ps
CPU time	25.33 seconds
Started	Apr 30 02:22:17 PM PDT 24
Finished	Apr 30 02:22:43 PM PDT 24
Peak memory	255348 kb
Host	smart-204d1db3-c920-43ee-864d-fed466dd6cfe
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22821 74662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.2282174662
Directory	/workspace/19.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/19.alert_handler_sig_int_fail.3191529991
Short name	T25
Test name
Test status
Simulation time	184891254 ps
CPU time	22.31 seconds
Started	Apr 30 02:22:03 PM PDT 24
Finished	Apr 30 02:22:26 PM PDT 24
Peak memory	248696 kb
Host	smart-46b52680-5cf4-4132-ae1e-3b40dd6be2f2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31915 29991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.3191529991
Directory	/workspace/19.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/19.alert_handler_smoke.1080996626
Short name	T613
Test name
Test status
Simulation time	4238938472 ps
CPU time	60.69 seconds
Started	Apr 30 02:22:07 PM PDT 24
Finished	Apr 30 02:23:08 PM PDT 24
Peak memory	248788 kb
Host	smart-a8f57455-0eb3-447f-92a4-2511457b2e28
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10809 96626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.1080996626
Directory	/workspace/19.alert_handler_smoke/latest

Test location	/workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.2522449056
Short name	T17
Test name
Test status
Simulation time	517429955050 ps
CPU time	1842.16 seconds
Started	Apr 30 02:22:17 PM PDT 24
Finished	Apr 30 02:53:00 PM PDT 24
Peak memory	289220 kb
Host	smart-62e59410-a625-42e8-8cc9-c24c3c7e4e3c
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522449056 -assert nopostproc +UVM_TESTNAME=aler t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.2522449056
Directory	/workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/2.alert_handler_alert_accum_saturation.1309656639
Short name	T241
Test name
Test status
Simulation time	50543449 ps
CPU time	4.03 seconds
Started	Apr 30 02:21:31 PM PDT 24
Finished	Apr 30 02:21:35 PM PDT 24
Peak memory	248908 kb
Host	smart-716bbe3e-5b73-4ab5-a77d-917889418530
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1309656639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.1309656639
Directory	/workspace/2.alert_handler_alert_accum_saturation/latest

Test location	/workspace/coverage/default/2.alert_handler_entropy.3710423144
Short name	T478
Test name
Test status
Simulation time	127058407768 ps
CPU time	1272.77 seconds
Started	Apr 30 02:21:29 PM PDT 24
Finished	Apr 30 02:42:43 PM PDT 24
Peak memory	273252 kb
Host	smart-6e927391-e9e2-4328-9c0d-6c51526b0fde
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3710423144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.3710423144
Directory	/workspace/2.alert_handler_entropy/latest

Test location	/workspace/coverage/default/2.alert_handler_entropy_stress.117236017
Short name	T611
Test name
Test status
Simulation time	2454990959 ps
CPU time	42.65 seconds
Started	Apr 30 02:21:32 PM PDT 24
Finished	Apr 30 02:22:15 PM PDT 24
Peak memory	248712 kb
Host	smart-7f8b6027-7c59-43ce-a1d9-1ae2923a223d
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=117236017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.117236017
Directory	/workspace/2.alert_handler_entropy_stress/latest

Test location	/workspace/coverage/default/2.alert_handler_esc_alert_accum.510085975
Short name	T646
Test name
Test status
Simulation time	17388383366 ps
CPU time	199.18 seconds
Started	Apr 30 02:21:31 PM PDT 24
Finished	Apr 30 02:24:51 PM PDT 24
Peak memory	249908 kb
Host	smart-9db90eb1-7ad1-46ec-82bc-3bbbbcdcefa4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51008 5975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.510085975
Directory	/workspace/2.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/2.alert_handler_esc_intr_timeout.994488476
Short name	T567
Test name
Test status
Simulation time	958981729 ps
CPU time	52.8 seconds
Started	Apr 30 02:21:32 PM PDT 24
Finished	Apr 30 02:22:25 PM PDT 24
Peak memory	255456 kb
Host	smart-e6e7dc55-7ecc-41c6-b1d2-a028a31bb6c6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99448 8476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.994488476
Directory	/workspace/2.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/2.alert_handler_lpg_stub_clk.3754903112
Short name	T303
Test name
Test status
Simulation time	17479328982 ps
CPU time	1128.37 seconds
Started	Apr 30 02:21:30 PM PDT 24
Finished	Apr 30 02:40:19 PM PDT 24
Peak memory	273364 kb
Host	smart-dff43672-623f-4dae-9c2d-38c953bdae2a
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3754903112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.3754903112
Directory	/workspace/2.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/2.alert_handler_random_alerts.2025448423
Short name	T558
Test name
Test status
Simulation time	206100330 ps
CPU time	15.46 seconds
Started	Apr 30 02:21:29 PM PDT 24
Finished	Apr 30 02:21:45 PM PDT 24
Peak memory	254952 kb
Host	smart-b51ec623-1c6d-4775-bf95-f577ba38ef89
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20254 48423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.2025448423
Directory	/workspace/2.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/2.alert_handler_random_classes.3016774072
Short name	T127
Test name
Test status
Simulation time	419542335 ps
CPU time	32.49 seconds
Started	Apr 30 02:21:31 PM PDT 24
Finished	Apr 30 02:22:04 PM PDT 24
Peak memory	248580 kb
Host	smart-7f88b86c-8014-4576-94cf-01609d037049
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30167 74072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.3016774072
Directory	/workspace/2.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/2.alert_handler_sig_int_fail.3956534173
Short name	T651
Test name
Test status
Simulation time	2233771270 ps
CPU time	16.49 seconds
Started	Apr 30 02:21:30 PM PDT 24
Finished	Apr 30 02:21:47 PM PDT 24
Peak memory	248872 kb
Host	smart-c501c067-5af5-4871-bd4b-2594c78e3f45
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39565 34173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.3956534173
Directory	/workspace/2.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/2.alert_handler_smoke.961780644
Short name	T483
Test name
Test status
Simulation time	894774438 ps
CPU time	8.83 seconds
Started	Apr 30 02:21:29 PM PDT 24
Finished	Apr 30 02:21:39 PM PDT 24
Peak memory	254072 kb
Host	smart-a2bc2a9d-84c0-4364-a5b8-7c13ac21380f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96178 0644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.961780644
Directory	/workspace/2.alert_handler_smoke/latest

Test location	/workspace/coverage/default/2.alert_handler_stress_all.290596241
Short name	T444
Test name
Test status
Simulation time	22442534 ps
CPU time	3.41 seconds
Started	Apr 30 02:21:29 PM PDT 24
Finished	Apr 30 02:21:33 PM PDT 24
Peak memory	240460 kb
Host	smart-84942ed5-4954-451b-a722-06c46741e985
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290596241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_hand ler_stress_all.290596241
Directory	/workspace/2.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.17181974
Short name	T265
Test name
Test status
Simulation time	254435294185 ps
CPU time	7443.81 seconds
Started	Apr 30 02:21:32 PM PDT 24
Finished	Apr 30 04:25:37 PM PDT 24
Peak memory	322532 kb
Host	smart-03b74c2a-bc18-490d-bd9f-780e508ddf2e
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17181974 -assert nopostproc +UVM_TESTNAME=alert_ handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.17181974
Directory	/workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/20.alert_handler_entropy.1717185529
Short name	T90
Test name
Test status
Simulation time	127346614807 ps
CPU time	1998.86 seconds
Started	Apr 30 02:22:03 PM PDT 24
Finished	Apr 30 02:55:22 PM PDT 24
Peak memory	286936 kb
Host	smart-b3a2606f-4901-4155-a9c7-95485248904a
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1717185529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.1717185529
Directory	/workspace/20.alert_handler_entropy/latest

Test location	/workspace/coverage/default/20.alert_handler_esc_alert_accum.1730368992
Short name	T707
Test name
Test status
Simulation time	2891441868 ps
CPU time	162.57 seconds
Started	Apr 30 02:22:02 PM PDT 24
Finished	Apr 30 02:24:45 PM PDT 24
Peak memory	250244 kb
Host	smart-a156e35b-d2e6-439e-830a-29e588aa4999
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17303 68992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.1730368992
Directory	/workspace/20.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/20.alert_handler_esc_intr_timeout.637355713
Short name	T413
Test name
Test status
Simulation time	884892822 ps
CPU time	17.76 seconds
Started	Apr 30 02:22:01 PM PDT 24
Finished	Apr 30 02:22:19 PM PDT 24
Peak memory	248688 kb
Host	smart-df476cb9-4a4c-40c8-80fd-bd2fb99be597
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63735 5713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.637355713
Directory	/workspace/20.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/20.alert_handler_lpg.1484396021
Short name	T355
Test name
Test status
Simulation time	22937160782 ps
CPU time	1331.46 seconds
Started	Apr 30 02:21:58 PM PDT 24
Finished	Apr 30 02:44:10 PM PDT 24
Peak memory	272316 kb
Host	smart-67cd16ef-10a1-42c2-8a30-925079867a89
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1484396021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.1484396021
Directory	/workspace/20.alert_handler_lpg/latest

Test location	/workspace/coverage/default/20.alert_handler_lpg_stub_clk.3830151639
Short name	T227
Test name
Test status
Simulation time	94700642052 ps
CPU time	1274.83 seconds
Started	Apr 30 02:22:10 PM PDT 24
Finished	Apr 30 02:43:25 PM PDT 24
Peak memory	288816 kb
Host	smart-9e517e21-e9ec-4904-a984-d7c6ce40e54a
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3830151639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.3830151639
Directory	/workspace/20.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/20.alert_handler_ping_timeout.1691931583
Short name	T124
Test name
Test status
Simulation time	21136399680 ps
CPU time	417.08 seconds
Started	Apr 30 02:22:01 PM PDT 24
Finished	Apr 30 02:28:59 PM PDT 24
Peak memory	247780 kb
Host	smart-cc5266cf-9d66-4db4-bfc3-0f6dc20bafa1
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1691931583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.1691931583
Directory	/workspace/20.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/20.alert_handler_random_alerts.4240040097
Short name	T88
Test name
Test status
Simulation time	976449913 ps
CPU time	35.22 seconds
Started	Apr 30 02:22:00 PM PDT 24
Finished	Apr 30 02:22:36 PM PDT 24
Peak memory	248712 kb
Host	smart-e661b66c-7633-437f-b4c2-2d7270ad867e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42400 40097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.4240040097
Directory	/workspace/20.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/20.alert_handler_random_classes.2538186379
Short name	T31
Test name
Test status
Simulation time	3243344539 ps
CPU time	49.73 seconds
Started	Apr 30 02:22:08 PM PDT 24
Finished	Apr 30 02:22:58 PM PDT 24
Peak memory	248788 kb
Host	smart-74d1f34a-b526-4039-a457-4dd453647bf2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25381 86379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.2538186379
Directory	/workspace/20.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/20.alert_handler_sig_int_fail.1308975606
Short name	T656
Test name
Test status
Simulation time	521270035 ps
CPU time	20.77 seconds
Started	Apr 30 02:21:58 PM PDT 24
Finished	Apr 30 02:22:20 PM PDT 24
Peak memory	248708 kb
Host	smart-bc242320-b4cb-47d5-8ee6-f48e4b552546
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13089 75606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.1308975606
Directory	/workspace/20.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/20.alert_handler_smoke.629005118
Short name	T15
Test name
Test status
Simulation time	840931668 ps
CPU time	42.61 seconds
Started	Apr 30 02:21:58 PM PDT 24
Finished	Apr 30 02:22:42 PM PDT 24
Peak memory	248580 kb
Host	smart-159b0bee-68be-4355-a446-1588397a8884
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62900 5118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.629005118
Directory	/workspace/20.alert_handler_smoke/latest

Test location	/workspace/coverage/default/21.alert_handler_entropy.2194452650
Short name	T588
Test name
Test status
Simulation time	20633191931 ps
CPU time	1375.81 seconds
Started	Apr 30 02:22:03 PM PDT 24
Finished	Apr 30 02:45:00 PM PDT 24
Peak memory	273376 kb
Host	smart-243a65d2-4704-40fe-9cd5-d3de92c14aaf
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2194452650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.2194452650
Directory	/workspace/21.alert_handler_entropy/latest

Test location	/workspace/coverage/default/21.alert_handler_esc_alert_accum.2630885879
Short name	T636
Test name
Test status
Simulation time	78344214 ps
CPU time	5.16 seconds
Started	Apr 30 02:22:10 PM PDT 24
Finished	Apr 30 02:22:15 PM PDT 24
Peak memory	254164 kb
Host	smart-f82831d6-29b5-448d-91f3-8e4e02c3b277
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26308 85879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.2630885879
Directory	/workspace/21.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/21.alert_handler_esc_intr_timeout.1372208640
Short name	T630
Test name
Test status
Simulation time	899306206 ps
CPU time	28.81 seconds
Started	Apr 30 02:22:00 PM PDT 24
Finished	Apr 30 02:22:29 PM PDT 24
Peak memory	255908 kb
Host	smart-f8576a5d-b95b-493b-a588-cc646e9541de
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13722 08640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.1372208640
Directory	/workspace/21.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/21.alert_handler_lpg_stub_clk.1490605364
Short name	T645
Test name
Test status
Simulation time	195356189046 ps
CPU time	2956.97 seconds
Started	Apr 30 02:22:00 PM PDT 24
Finished	Apr 30 03:11:18 PM PDT 24
Peak memory	285656 kb
Host	smart-3d627a74-92b9-4ecc-8d88-a5ab70b1207f
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1490605364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.1490605364
Directory	/workspace/21.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/21.alert_handler_ping_timeout.1340821327
Short name	T337
Test name
Test status
Simulation time	26543141254 ps
CPU time	282.14 seconds
Started	Apr 30 02:22:01 PM PDT 24
Finished	Apr 30 02:26:43 PM PDT 24
Peak memory	247780 kb
Host	smart-63e55032-4223-459c-b9d5-f0d72ec8d4fa
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1340821327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.1340821327
Directory	/workspace/21.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/21.alert_handler_random_alerts.4049737576
Short name	T562
Test name
Test status
Simulation time	695240058 ps
CPU time	50.51 seconds
Started	Apr 30 02:22:14 PM PDT 24
Finished	Apr 30 02:23:05 PM PDT 24
Peak memory	248728 kb
Host	smart-29f956c6-e909-474c-b149-acc09416df02
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40497 37576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.4049737576
Directory	/workspace/21.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/21.alert_handler_random_classes.4219057607
Short name	T454
Test name
Test status
Simulation time	81345416 ps
CPU time	4.16 seconds
Started	Apr 30 02:22:07 PM PDT 24
Finished	Apr 30 02:22:12 PM PDT 24
Peak memory	240496 kb
Host	smart-357257ee-c27d-4557-9ad3-99ac60a8f86d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42190 57607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.4219057607
Directory	/workspace/21.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/21.alert_handler_sig_int_fail.851170776
Short name	T91
Test name
Test status
Simulation time	2047101689 ps
CPU time	46.19 seconds
Started	Apr 30 02:22:10 PM PDT 24
Finished	Apr 30 02:22:57 PM PDT 24
Peak memory	255452 kb
Host	smart-8d5936bf-e8b8-4ae8-9076-70436ff1c01f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85117 0776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.851170776
Directory	/workspace/21.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/21.alert_handler_smoke.286847825
Short name	T98
Test name
Test status
Simulation time	351202107 ps
CPU time	25.1 seconds
Started	Apr 30 02:22:08 PM PDT 24
Finished	Apr 30 02:22:34 PM PDT 24
Peak memory	255424 kb
Host	smart-f543d267-73b6-485d-8016-5c7ce2cc43fe
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28684 7825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.286847825
Directory	/workspace/21.alert_handler_smoke/latest

Test location	/workspace/coverage/default/21.alert_handler_stress_all.2922197650
Short name	T480
Test name
Test status
Simulation time	27697858919 ps
CPU time	1473.1 seconds
Started	Apr 30 02:22:01 PM PDT 24
Finished	Apr 30 02:46:35 PM PDT 24
Peak memory	272380 kb
Host	smart-edb19bad-b0e0-4688-ad4a-5e1f60004524
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922197650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha ndler_stress_all.2922197650
Directory	/workspace/21.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.2207545526
Short name	T652
Test name
Test status
Simulation time	218011621791 ps
CPU time	2124.22 seconds
Started	Apr 30 02:21:59 PM PDT 24
Finished	Apr 30 02:57:24 PM PDT 24
Peak memory	300100 kb
Host	smart-8d95d54f-0a0a-405a-a93c-90b5b2f93e74
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207545526 -assert nopostproc +UVM_TESTNAME=aler t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.2207545526
Directory	/workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/22.alert_handler_entropy.278106438
Short name	T608
Test name
Test status
Simulation time	12899752587 ps
CPU time	1180.15 seconds
Started	Apr 30 02:22:07 PM PDT 24
Finished	Apr 30 02:41:48 PM PDT 24
Peak memory	289632 kb
Host	smart-29b7243c-38a2-4e20-ba62-e0c995deb245
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=278106438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.278106438
Directory	/workspace/22.alert_handler_entropy/latest

Test location	/workspace/coverage/default/22.alert_handler_esc_alert_accum.3226106036
Short name	T445
Test name
Test status
Simulation time	7149004258 ps
CPU time	230.72 seconds
Started	Apr 30 02:22:09 PM PDT 24
Finished	Apr 30 02:26:00 PM PDT 24
Peak memory	256844 kb
Host	smart-b123cc9e-5045-4d51-a783-e924265fe2d5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32261 06036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.3226106036
Directory	/workspace/22.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/22.alert_handler_esc_intr_timeout.3692876819
Short name	T101
Test name
Test status
Simulation time	666150386 ps
CPU time	23.7 seconds
Started	Apr 30 02:22:09 PM PDT 24
Finished	Apr 30 02:22:33 PM PDT 24
Peak memory	254852 kb
Host	smart-d77d637c-2e88-4101-9b67-53e2aef35c67
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36928 76819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.3692876819
Directory	/workspace/22.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/22.alert_handler_lpg.3701983353
Short name	T687
Test name
Test status
Simulation time	95511666647 ps
CPU time	1553.67 seconds
Started	Apr 30 02:22:11 PM PDT 24
Finished	Apr 30 02:48:05 PM PDT 24
Peak memory	288724 kb
Host	smart-496fbc00-6099-4a64-b25b-37b9dce23b00
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3701983353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.3701983353
Directory	/workspace/22.alert_handler_lpg/latest

Test location	/workspace/coverage/default/22.alert_handler_lpg_stub_clk.1944840928
Short name	T223
Test name
Test status
Simulation time	61952692162 ps
CPU time	1597.48 seconds
Started	Apr 30 02:22:10 PM PDT 24
Finished	Apr 30 02:48:48 PM PDT 24
Peak memory	289292 kb
Host	smart-2e93b2de-b96e-4ed6-992d-4d88215c7dff
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1944840928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.1944840928
Directory	/workspace/22.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/22.alert_handler_ping_timeout.1771026281
Short name	T289
Test name
Test status
Simulation time	4698468607 ps
CPU time	177.11 seconds
Started	Apr 30 02:22:15 PM PDT 24
Finished	Apr 30 02:25:13 PM PDT 24
Peak memory	247788 kb
Host	smart-9a4fae3c-2605-4cb9-9027-1ad5c852dd4e
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1771026281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.1771026281
Directory	/workspace/22.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/22.alert_handler_random_alerts.2150548933
Short name	T410
Test name
Test status
Simulation time	1413841225 ps
CPU time	31.81 seconds
Started	Apr 30 02:22:01 PM PDT 24
Finished	Apr 30 02:22:33 PM PDT 24
Peak memory	248652 kb
Host	smart-1119b1cf-be84-4a08-a4e1-1658504243b6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21505 48933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.2150548933
Directory	/workspace/22.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/22.alert_handler_sig_int_fail.256507731
Short name	T53
Test name
Test status
Simulation time	1679704771 ps
CPU time	28.73 seconds
Started	Apr 30 02:22:15 PM PDT 24
Finished	Apr 30 02:22:45 PM PDT 24
Peak memory	248688 kb
Host	smart-51e8c96f-773b-4ce8-af13-b2bde7d6af20
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25650 7731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.256507731
Directory	/workspace/22.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/22.alert_handler_smoke.1256675598
Short name	T87
Test name
Test status
Simulation time	890088857 ps
CPU time	53.19 seconds
Started	Apr 30 02:22:01 PM PDT 24
Finished	Apr 30 02:22:55 PM PDT 24
Peak memory	255840 kb
Host	smart-baa8d775-9f16-4442-8b69-9b52b04f4d07
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12566 75598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.1256675598
Directory	/workspace/22.alert_handler_smoke/latest

Test location	/workspace/coverage/default/22.alert_handler_stress_all.154990266
Short name	T139
Test name
Test status
Simulation time	25285108243 ps
CPU time	1372.94 seconds
Started	Apr 30 02:22:09 PM PDT 24
Finished	Apr 30 02:45:03 PM PDT 24
Peak memory	289760 kb
Host	smart-1e8bf8cc-da69-415a-9fd4-a9b2ade96582
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154990266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_han dler_stress_all.154990266
Directory	/workspace/22.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/23.alert_handler_entropy.459449785
Short name	T224
Test name
Test status
Simulation time	71023232700 ps
CPU time	2245.75 seconds
Started	Apr 30 02:22:13 PM PDT 24
Finished	Apr 30 02:59:39 PM PDT 24
Peak memory	284420 kb
Host	smart-89598446-077e-4128-bccf-eeab8bb25594
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=459449785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.459449785
Directory	/workspace/23.alert_handler_entropy/latest

Test location	/workspace/coverage/default/23.alert_handler_esc_alert_accum.3054127210
Short name	T565
Test name
Test status
Simulation time	1268099660 ps
CPU time	92.82 seconds
Started	Apr 30 02:22:19 PM PDT 24
Finished	Apr 30 02:23:52 PM PDT 24
Peak memory	249708 kb
Host	smart-0ca97832-a38b-4d79-b984-f8da0dd9b5ec
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30541 27210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.3054127210
Directory	/workspace/23.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/23.alert_handler_esc_intr_timeout.623258553
Short name	T29
Test name
Test status
Simulation time	278236715 ps
CPU time	26.18 seconds
Started	Apr 30 02:22:14 PM PDT 24
Finished	Apr 30 02:22:41 PM PDT 24
Peak memory	248696 kb
Host	smart-2d55027b-a161-4c64-8f47-e26cb110edd5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62325 8553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.623258553
Directory	/workspace/23.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/23.alert_handler_lpg.3155182269
Short name	T705
Test name
Test status
Simulation time	11371999549 ps
CPU time	597.65 seconds
Started	Apr 30 02:22:14 PM PDT 24
Finished	Apr 30 02:32:12 PM PDT 24
Peak memory	265168 kb
Host	smart-9db978e8-96ca-4289-ab96-951a1d877251
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3155182269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.3155182269
Directory	/workspace/23.alert_handler_lpg/latest

Test location	/workspace/coverage/default/23.alert_handler_lpg_stub_clk.2833831093
Short name	T296
Test name
Test status
Simulation time	75410847508 ps
CPU time	2584.96 seconds
Started	Apr 30 02:22:22 PM PDT 24
Finished	Apr 30 03:05:28 PM PDT 24
Peak memory	289440 kb
Host	smart-1a71c0ac-436f-415c-8a22-4ae608cc5b82
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2833831093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.2833831093
Directory	/workspace/23.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/23.alert_handler_random_alerts.932993733
Short name	T81
Test name
Test status
Simulation time	133795965 ps
CPU time	11.3 seconds
Started	Apr 30 02:22:19 PM PDT 24
Finished	Apr 30 02:22:30 PM PDT 24
Peak memory	248680 kb
Host	smart-451cb9d1-6dce-4876-a2e8-17b452a6a781
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93299 3733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.932993733
Directory	/workspace/23.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/23.alert_handler_random_classes.3477069465
Short name	T537
Test name
Test status
Simulation time	1537759758 ps
CPU time	24.4 seconds
Started	Apr 30 02:22:12 PM PDT 24
Finished	Apr 30 02:22:37 PM PDT 24
Peak memory	249044 kb
Host	smart-5cc340cd-2ada-4470-8106-89f76f2a2d16
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34770 69465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.3477069465
Directory	/workspace/23.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/23.alert_handler_sig_int_fail.4139497957
Short name	T278
Test name
Test status
Simulation time	1945941054 ps
CPU time	63.9 seconds
Started	Apr 30 02:22:16 PM PDT 24
Finished	Apr 30 02:23:20 PM PDT 24
Peak memory	248636 kb
Host	smart-50432393-18f9-4c99-81d8-550f0bacd98b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41394 97957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.4139497957
Directory	/workspace/23.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/23.alert_handler_smoke.2247292030
Short name	T496
Test name
Test status
Simulation time	2814899255 ps
CPU time	47.08 seconds
Started	Apr 30 02:22:10 PM PDT 24
Finished	Apr 30 02:22:57 PM PDT 24
Peak memory	248724 kb
Host	smart-7c0800e2-ae6d-4ace-b4ed-5673ca05db4b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22472 92030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.2247292030
Directory	/workspace/23.alert_handler_smoke/latest

Test location	/workspace/coverage/default/23.alert_handler_stress_all.2384428096
Short name	T122
Test name
Test status
Simulation time	137339893145 ps
CPU time	3654.01 seconds
Started	Apr 30 02:22:18 PM PDT 24
Finished	Apr 30 03:23:13 PM PDT 24
Peak memory	297904 kb
Host	smart-b8afe697-c30f-4eca-990d-94182d837317
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384428096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha ndler_stress_all.2384428096
Directory	/workspace/23.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.3882740334
Short name	T266
Test name
Test status
Simulation time	307505190690 ps
CPU time	4586.95 seconds
Started	Apr 30 02:22:14 PM PDT 24
Finished	Apr 30 03:38:42 PM PDT 24
Peak memory	297944 kb
Host	smart-f5a1a8cf-1d73-497b-b96b-a6aa7848237b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882740334 -assert nopostproc +UVM_TESTNAME=aler t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.3882740334
Directory	/workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/24.alert_handler_entropy.257377075
Short name	T308
Test name
Test status
Simulation time	34724322937 ps
CPU time	2431.99 seconds
Started	Apr 30 02:22:17 PM PDT 24
Finished	Apr 30 03:02:50 PM PDT 24
Peak memory	281616 kb
Host	smart-b70cf384-82f1-49b5-87cb-d3c5e575328b
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=257377075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.257377075
Directory	/workspace/24.alert_handler_entropy/latest

Test location	/workspace/coverage/default/24.alert_handler_esc_alert_accum.3656326145
Short name	T398
Test name
Test status
Simulation time	3933960413 ps
CPU time	129.35 seconds
Started	Apr 30 02:22:20 PM PDT 24
Finished	Apr 30 02:24:29 PM PDT 24
Peak memory	249196 kb
Host	smart-2f2f0bce-405d-4169-b9fc-d8a1f49ad644
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36563 26145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.3656326145
Directory	/workspace/24.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/24.alert_handler_esc_intr_timeout.2828000573
Short name	T419
Test name
Test status
Simulation time	954277386 ps
CPU time	15.78 seconds
Started	Apr 30 02:22:15 PM PDT 24
Finished	Apr 30 02:22:31 PM PDT 24
Peak memory	254896 kb
Host	smart-9343f86b-7ede-4640-803d-5f54b951b26a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28280 00573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.2828000573
Directory	/workspace/24.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/24.alert_handler_lpg.3224084067
Short name	T670
Test name
Test status
Simulation time	8441128263 ps
CPU time	683.48 seconds
Started	Apr 30 02:22:20 PM PDT 24
Finished	Apr 30 02:33:44 PM PDT 24
Peak memory	269468 kb
Host	smart-a6d1ffd7-a228-412e-8be8-e36547a89ac2
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3224084067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.3224084067
Directory	/workspace/24.alert_handler_lpg/latest

Test location	/workspace/coverage/default/24.alert_handler_lpg_stub_clk.1363466398
Short name	T74
Test name
Test status
Simulation time	113713136791 ps
CPU time	1292.24 seconds
Started	Apr 30 02:22:22 PM PDT 24
Finished	Apr 30 02:43:55 PM PDT 24
Peak memory	281480 kb
Host	smart-ec16230a-f0cd-4e8a-9ebc-028b6ba801ba
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1363466398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.1363466398
Directory	/workspace/24.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/24.alert_handler_ping_timeout.4033074101
Short name	T75
Test name
Test status
Simulation time	39591626685 ps
CPU time	291.4 seconds
Started	Apr 30 02:22:28 PM PDT 24
Finished	Apr 30 02:27:19 PM PDT 24
Peak memory	247816 kb
Host	smart-82d0fd1c-dfc2-4dc9-a63b-594a373f8b3d
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4033074101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.4033074101
Directory	/workspace/24.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/24.alert_handler_random_alerts.891109189
Short name	T449
Test name
Test status
Simulation time	163017741 ps
CPU time	16.08 seconds
Started	Apr 30 02:22:16 PM PDT 24
Finished	Apr 30 02:22:33 PM PDT 24
Peak memory	248736 kb
Host	smart-8569358a-8354-4393-a933-b4a865087db3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89110 9189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.891109189
Directory	/workspace/24.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/24.alert_handler_random_classes.1895932956
Short name	T86
Test name
Test status
Simulation time	393849016 ps
CPU time	26.18 seconds
Started	Apr 30 02:22:17 PM PDT 24
Finished	Apr 30 02:22:43 PM PDT 24
Peak memory	248684 kb
Host	smart-ac28d241-b2cc-4445-bdbf-f932f0818805
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18959 32956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.1895932956
Directory	/workspace/24.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/24.alert_handler_sig_int_fail.672514910
Short name	T271
Test name
Test status
Simulation time	1280483235 ps
CPU time	21.82 seconds
Started	Apr 30 02:22:20 PM PDT 24
Finished	Apr 30 02:22:42 PM PDT 24
Peak memory	255804 kb
Host	smart-90808c1e-da1b-49f1-b433-889eeac3487c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67251 4910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.672514910
Directory	/workspace/24.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/24.alert_handler_smoke.663565284
Short name	T96
Test name
Test status
Simulation time	709932747 ps
CPU time	42.91 seconds
Started	Apr 30 02:22:15 PM PDT 24
Finished	Apr 30 02:22:59 PM PDT 24
Peak memory	248688 kb
Host	smart-11fc4e7a-0a98-49a7-bce9-1691ee1e539b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66356 5284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.663565284
Directory	/workspace/24.alert_handler_smoke/latest

Test location	/workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.2095696226
Short name	T201
Test name
Test status
Simulation time	95671150166 ps
CPU time	2494.16 seconds
Started	Apr 30 02:22:28 PM PDT 24
Finished	Apr 30 03:04:03 PM PDT 24
Peak memory	305568 kb
Host	smart-b303d2f9-505b-4a41-b340-877136f4ee9b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095696226 -assert nopostproc +UVM_TESTNAME=aler t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.2095696226
Directory	/workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/25.alert_handler_entropy.2139169860
Short name	T624
Test name
Test status
Simulation time	20585637961 ps
CPU time	1240.53 seconds
Started	Apr 30 02:22:25 PM PDT 24
Finished	Apr 30 02:43:06 PM PDT 24
Peak memory	273284 kb
Host	smart-3353b661-d4d9-4045-8f70-eb637a57c8b1
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2139169860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.2139169860
Directory	/workspace/25.alert_handler_entropy/latest

Test location	/workspace/coverage/default/25.alert_handler_esc_alert_accum.3774586369
Short name	T394
Test name
Test status
Simulation time	1353240323 ps
CPU time	55.43 seconds
Started	Apr 30 02:22:25 PM PDT 24
Finished	Apr 30 02:23:21 PM PDT 24
Peak memory	249040 kb
Host	smart-472a53a8-a510-40a6-b0b3-79fcc390bd81
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37745 86369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.3774586369
Directory	/workspace/25.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/25.alert_handler_esc_intr_timeout.417396495
Short name	T669
Test name
Test status
Simulation time	472521573 ps
CPU time	29.74 seconds
Started	Apr 30 02:22:24 PM PDT 24
Finished	Apr 30 02:22:54 PM PDT 24
Peak memory	248776 kb
Host	smart-057bdfa6-989e-44f2-b0c8-344781f2a96a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41739 6495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.417396495
Directory	/workspace/25.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/25.alert_handler_lpg.3831469425
Short name	T566
Test name
Test status
Simulation time	25354569900 ps
CPU time	600.87 seconds
Started	Apr 30 02:22:27 PM PDT 24
Finished	Apr 30 02:32:28 PM PDT 24
Peak memory	265148 kb
Host	smart-99165ad3-0978-4c37-b5c8-cb1e705920ec
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3831469425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.3831469425
Directory	/workspace/25.alert_handler_lpg/latest

Test location	/workspace/coverage/default/25.alert_handler_lpg_stub_clk.1346418033
Short name	T703
Test name
Test status
Simulation time	20362732557 ps
CPU time	1260.83 seconds
Started	Apr 30 02:22:26 PM PDT 24
Finished	Apr 30 02:43:28 PM PDT 24
Peak memory	272940 kb
Host	smart-3d8c7f00-f770-4150-9493-5b1b4ce5c6e6
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1346418033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.1346418033
Directory	/workspace/25.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/25.alert_handler_random_alerts.797634818
Short name	T408
Test name
Test status
Simulation time	2594294304 ps
CPU time	30.59 seconds
Started	Apr 30 02:22:24 PM PDT 24
Finished	Apr 30 02:22:55 PM PDT 24
Peak memory	255996 kb
Host	smart-17bde95c-1034-4b4c-93c9-f4534bde27f4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79763 4818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.797634818
Directory	/workspace/25.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/25.alert_handler_random_classes.2391043789
Short name	T136
Test name
Test status
Simulation time	415697142 ps
CPU time	43.97 seconds
Started	Apr 30 02:22:24 PM PDT 24
Finished	Apr 30 02:23:08 PM PDT 24
Peak memory	248712 kb
Host	smart-9df5c8c7-f725-49f8-8b31-bfe03f604d8e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23910 43789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.2391043789
Directory	/workspace/25.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/25.alert_handler_sig_int_fail.3987504241
Short name	T108
Test name
Test status
Simulation time	266673074 ps
CPU time	38.83 seconds
Started	Apr 30 02:22:28 PM PDT 24
Finished	Apr 30 02:23:08 PM PDT 24
Peak memory	249196 kb
Host	smart-5f6f9fba-6d28-4073-a864-8b6c0e9c658b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39875 04241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.3987504241
Directory	/workspace/25.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/25.alert_handler_smoke.2698386777
Short name	T561
Test name
Test status
Simulation time	45333828 ps
CPU time	6.39 seconds
Started	Apr 30 02:22:25 PM PDT 24
Finished	Apr 30 02:22:32 PM PDT 24
Peak memory	252828 kb
Host	smart-7444d79b-4562-4b02-b24e-7914778ed7ba
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26983 86777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.2698386777
Directory	/workspace/25.alert_handler_smoke/latest

Test location	/workspace/coverage/default/26.alert_handler_entropy.2241862758
Short name	T12
Test name
Test status
Simulation time	239278785232 ps
CPU time	2840.12 seconds
Started	Apr 30 02:22:31 PM PDT 24
Finished	Apr 30 03:09:51 PM PDT 24
Peak memory	289508 kb
Host	smart-ca6964ca-9956-41aa-a6f5-1b888e746487
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2241862758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.2241862758
Directory	/workspace/26.alert_handler_entropy/latest

Test location	/workspace/coverage/default/26.alert_handler_esc_alert_accum.4134354160
Short name	T548
Test name
Test status
Simulation time	8889382755 ps
CPU time	183.48 seconds
Started	Apr 30 02:22:29 PM PDT 24
Finished	Apr 30 02:25:33 PM PDT 24
Peak memory	250960 kb
Host	smart-5104e6db-209e-4aee-8afb-798a95ef8c59
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41343 54160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.4134354160
Directory	/workspace/26.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/26.alert_handler_esc_intr_timeout.1273370159
Short name	T554
Test name
Test status
Simulation time	713980208 ps
CPU time	43.4 seconds
Started	Apr 30 02:22:26 PM PDT 24
Finished	Apr 30 02:23:10 PM PDT 24
Peak memory	255876 kb
Host	smart-abe29837-f2bd-46bf-9959-645be21db0f8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12733 70159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.1273370159
Directory	/workspace/26.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/26.alert_handler_lpg.3587623562
Short name	T205
Test name
Test status
Simulation time	106993563610 ps
CPU time	3142.96 seconds
Started	Apr 30 02:22:30 PM PDT 24
Finished	Apr 30 03:14:54 PM PDT 24
Peak memory	289064 kb
Host	smart-a2229004-c7ae-4e93-99e7-b0b839eb9120
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3587623562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.3587623562
Directory	/workspace/26.alert_handler_lpg/latest

Test location	/workspace/coverage/default/26.alert_handler_lpg_stub_clk.4194893579
Short name	T391
Test name
Test status
Simulation time	43726838195 ps
CPU time	1359.29 seconds
Started	Apr 30 02:22:30 PM PDT 24
Finished	Apr 30 02:45:10 PM PDT 24
Peak memory	272960 kb
Host	smart-805fa8de-7229-4251-97b5-43f8acb7cdd6
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4194893579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.4194893579
Directory	/workspace/26.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/26.alert_handler_ping_timeout.862971980
Short name	T210
Test name
Test status
Simulation time	21248512625 ps
CPU time	440.68 seconds
Started	Apr 30 02:22:31 PM PDT 24
Finished	Apr 30 02:29:52 PM PDT 24
Peak memory	248204 kb
Host	smart-e0a15a79-7c15-47b5-9287-b4e839cd9cf8
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=862971980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.862971980
Directory	/workspace/26.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/26.alert_handler_random_alerts.1204033751
Short name	T674
Test name
Test status
Simulation time	195591148 ps
CPU time	15.84 seconds
Started	Apr 30 02:22:25 PM PDT 24
Finished	Apr 30 02:22:41 PM PDT 24
Peak memory	248700 kb
Host	smart-0a4a1d36-6393-4b23-a799-ce0a0fb68d43
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12040 33751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.1204033751
Directory	/workspace/26.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/26.alert_handler_random_classes.4039334845
Short name	T709
Test name
Test status
Simulation time	3671233247 ps
CPU time	43.85 seconds
Started	Apr 30 02:22:24 PM PDT 24
Finished	Apr 30 02:23:09 PM PDT 24
Peak memory	249116 kb
Host	smart-f366d955-b252-464c-a39a-f00d41138f85
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40393 34845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.4039334845
Directory	/workspace/26.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/26.alert_handler_sig_int_fail.3399825565
Short name	T497
Test name
Test status
Simulation time	1429831512 ps
CPU time	28.68 seconds
Started	Apr 30 02:22:30 PM PDT 24
Finished	Apr 30 02:22:59 PM PDT 24
Peak memory	248728 kb
Host	smart-eb9c1bb8-7b7e-4173-9d77-7921f860128c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33998 25565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.3399825565
Directory	/workspace/26.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/26.alert_handler_smoke.3795944032
Short name	T702
Test name
Test status
Simulation time	4203769313 ps
CPU time	47.29 seconds
Started	Apr 30 02:22:23 PM PDT 24
Finished	Apr 30 02:23:10 PM PDT 24
Peak memory	256076 kb
Host	smart-41ef8dff-dca0-48e8-bf12-c1bb0114fa31
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37959 44032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.3795944032
Directory	/workspace/26.alert_handler_smoke/latest

Test location	/workspace/coverage/default/26.alert_handler_stress_all.1476144141
Short name	T5
Test name
Test status
Simulation time	2705479535 ps
CPU time	135.66 seconds
Started	Apr 30 02:22:31 PM PDT 24
Finished	Apr 30 02:24:48 PM PDT 24
Peak memory	256900 kb
Host	smart-4edf689b-926d-4be2-89dc-8059275db764
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476144141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha ndler_stress_all.1476144141
Directory	/workspace/26.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.1709416427
Short name	T211
Test name
Test status
Simulation time	289589774908 ps
CPU time	6308.12 seconds
Started	Apr 30 02:22:30 PM PDT 24
Finished	Apr 30 04:07:39 PM PDT 24
Peak memory	362928 kb
Host	smart-3c8fc10d-fee0-4b15-a31f-843505cbb8f3
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709416427 -assert nopostproc +UVM_TESTNAME=aler t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.1709416427
Directory	/workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/27.alert_handler_entropy.2440145521
Short name	T33
Test name
Test status
Simulation time	20191528533 ps
CPU time	1612.09 seconds
Started	Apr 30 02:22:32 PM PDT 24
Finished	Apr 30 02:49:25 PM PDT 24
Peak memory	289356 kb
Host	smart-170f2ff5-7567-4c71-91f4-95d8fcdf5be2
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2440145521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.2440145521
Directory	/workspace/27.alert_handler_entropy/latest

Test location	/workspace/coverage/default/27.alert_handler_esc_alert_accum.3247199041
Short name	T641
Test name
Test status
Simulation time	10393943772 ps
CPU time	191.21 seconds
Started	Apr 30 02:22:32 PM PDT 24
Finished	Apr 30 02:25:44 PM PDT 24
Peak memory	250008 kb
Host	smart-354f4766-8faf-4f76-b229-502d201bc3f6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32471 99041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.3247199041
Directory	/workspace/27.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/27.alert_handler_esc_intr_timeout.2192255782
Short name	T697
Test name
Test status
Simulation time	247121307 ps
CPU time	6.47 seconds
Started	Apr 30 02:22:31 PM PDT 24
Finished	Apr 30 02:22:38 PM PDT 24
Peak memory	252964 kb
Host	smart-0ba8527d-7d44-4c43-b191-4837a8afe8d4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21922 55782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.2192255782
Directory	/workspace/27.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/27.alert_handler_lpg.3919941721
Short name	T32
Test name
Test status
Simulation time	34146947838 ps
CPU time	1762.84 seconds
Started	Apr 30 02:22:31 PM PDT 24
Finished	Apr 30 02:51:54 PM PDT 24
Peak memory	273316 kb
Host	smart-21109519-f851-4417-a5da-710b0d727cc5
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3919941721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.3919941721
Directory	/workspace/27.alert_handler_lpg/latest

Test location	/workspace/coverage/default/27.alert_handler_lpg_stub_clk.3127508012
Short name	T61
Test name
Test status
Simulation time	9526103978 ps
CPU time	1161.23 seconds
Started	Apr 30 02:22:29 PM PDT 24
Finished	Apr 30 02:41:51 PM PDT 24
Peak memory	281036 kb
Host	smart-b9e4d43a-728e-4833-bad7-64442372674d
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3127508012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.3127508012
Directory	/workspace/27.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/27.alert_handler_ping_timeout.2925630983
Short name	T253
Test name
Test status
Simulation time	2978192175 ps
CPU time	114.16 seconds
Started	Apr 30 02:22:30 PM PDT 24
Finished	Apr 30 02:24:25 PM PDT 24
Peak memory	248168 kb
Host	smart-2dbcfddf-b560-496f-8a42-0d1fd9ac1661
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2925630983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.2925630983
Directory	/workspace/27.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/27.alert_handler_random_alerts.4042324439
Short name	T516
Test name
Test status
Simulation time	992412091 ps
CPU time	24.96 seconds
Started	Apr 30 02:22:31 PM PDT 24
Finished	Apr 30 02:22:56 PM PDT 24
Peak memory	248668 kb
Host	smart-42ca52d4-3b17-426d-b735-e87ad9b1833d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40423 24439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.4042324439
Directory	/workspace/27.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/27.alert_handler_random_classes.1098206558
Short name	T504
Test name
Test status
Simulation time	2987932122 ps
CPU time	52.4 seconds
Started	Apr 30 02:22:32 PM PDT 24
Finished	Apr 30 02:23:25 PM PDT 24
Peak memory	255408 kb
Host	smart-9ec01d71-304f-41ac-86c6-fc5ff6095fd3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10982 06558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.1098206558
Directory	/workspace/27.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/27.alert_handler_sig_int_fail.104844137
Short name	T649
Test name
Test status
Simulation time	3369737845 ps
CPU time	39.26 seconds
Started	Apr 30 02:22:31 PM PDT 24
Finished	Apr 30 02:23:11 PM PDT 24
Peak memory	248992 kb
Host	smart-e65bf321-6926-4912-8026-17cc1601552b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10484 4137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.104844137
Directory	/workspace/27.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/27.alert_handler_smoke.1235468262
Short name	T204
Test name
Test status
Simulation time	83276557 ps
CPU time	13.11 seconds
Started	Apr 30 02:22:30 PM PDT 24
Finished	Apr 30 02:22:44 PM PDT 24
Peak memory	248708 kb
Host	smart-5fd4ac2b-228b-44e0-ab09-cf7fef1602c3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12354 68262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.1235468262
Directory	/workspace/27.alert_handler_smoke/latest

Test location	/workspace/coverage/default/27.alert_handler_stress_all.2418743920
Short name	T50
Test name
Test status
Simulation time	58258392640 ps
CPU time	1349.56 seconds
Started	Apr 30 02:22:42 PM PDT 24
Finished	Apr 30 02:45:12 PM PDT 24
Peak memory	288012 kb
Host	smart-2773bbc3-e7e0-48e1-ad1b-acaae535f71e
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418743920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha ndler_stress_all.2418743920
Directory	/workspace/27.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/28.alert_handler_entropy.1674338141
Short name	T531
Test name
Test status
Simulation time	33128307848 ps
CPU time	1135.37 seconds
Started	Apr 30 02:22:39 PM PDT 24
Finished	Apr 30 02:41:35 PM PDT 24
Peak memory	281520 kb
Host	smart-014c7b9d-0a93-42db-9971-83e838177c3d
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1674338141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.1674338141
Directory	/workspace/28.alert_handler_entropy/latest

Test location	/workspace/coverage/default/28.alert_handler_esc_alert_accum.1063461591
Short name	T292
Test name
Test status
Simulation time	9710813335 ps
CPU time	270.08 seconds
Started	Apr 30 02:22:40 PM PDT 24
Finished	Apr 30 02:27:10 PM PDT 24
Peak memory	249760 kb
Host	smart-67ccdce0-a922-4020-a0dd-cd8d314e97f1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10634 61591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.1063461591
Directory	/workspace/28.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/28.alert_handler_esc_intr_timeout.1300335246
Short name	T493
Test name
Test status
Simulation time	3193880089 ps
CPU time	49.21 seconds
Started	Apr 30 02:22:39 PM PDT 24
Finished	Apr 30 02:23:29 PM PDT 24
Peak memory	248752 kb
Host	smart-083fd54e-6c72-497a-9ddb-e703518dbd63
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13003 35246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.1300335246
Directory	/workspace/28.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/28.alert_handler_lpg.2737215358
Short name	T356
Test name
Test status
Simulation time	93553462473 ps
CPU time	1393.17 seconds
Started	Apr 30 02:22:39 PM PDT 24
Finished	Apr 30 02:45:53 PM PDT 24
Peak memory	272328 kb
Host	smart-1581e000-30d6-4e60-bde7-5c9c892026ab
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2737215358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.2737215358
Directory	/workspace/28.alert_handler_lpg/latest

Test location	/workspace/coverage/default/28.alert_handler_lpg_stub_clk.2899711348
Short name	T671
Test name
Test status
Simulation time	10411066694 ps
CPU time	1031.2 seconds
Started	Apr 30 02:22:39 PM PDT 24
Finished	Apr 30 02:39:51 PM PDT 24
Peak memory	272872 kb
Host	smart-eec6749b-5ba6-4237-b455-966bce4c27a0
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2899711348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.2899711348
Directory	/workspace/28.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/28.alert_handler_ping_timeout.1545750922
Short name	T349
Test name
Test status
Simulation time	63522847673 ps
CPU time	644.78 seconds
Started	Apr 30 02:22:40 PM PDT 24
Finished	Apr 30 02:33:25 PM PDT 24
Peak memory	247744 kb
Host	smart-026fd7ef-eb93-4199-b614-ec0a401c97f9
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1545750922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.1545750922
Directory	/workspace/28.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/28.alert_handler_random_alerts.106793864
Short name	T255
Test name
Test status
Simulation time	2938791438 ps
CPU time	59.22 seconds
Started	Apr 30 02:22:39 PM PDT 24
Finished	Apr 30 02:23:39 PM PDT 24
Peak memory	248796 kb
Host	smart-81324dc9-9332-4f2e-820f-d8bd429a2727
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10679 3864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.106793864
Directory	/workspace/28.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/28.alert_handler_random_classes.1229361904
Short name	T395
Test name
Test status
Simulation time	78237346 ps
CPU time	4.72 seconds
Started	Apr 30 02:22:40 PM PDT 24
Finished	Apr 30 02:22:45 PM PDT 24
Peak memory	240464 kb
Host	smart-6cfc34ef-b896-47df-afc6-04634a703c37
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12293 61904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.1229361904
Directory	/workspace/28.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/28.alert_handler_sig_int_fail.2695277684
Short name	T526
Test name
Test status
Simulation time	189046796 ps
CPU time	20.79 seconds
Started	Apr 30 02:22:40 PM PDT 24
Finished	Apr 30 02:23:02 PM PDT 24
Peak memory	248700 kb
Host	smart-84a23eeb-b27a-4b46-b8eb-8d22ad2fa8ab
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26952 77684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.2695277684
Directory	/workspace/28.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/28.alert_handler_smoke.98737990
Short name	T436
Test name
Test status
Simulation time	344021599 ps
CPU time	17.34 seconds
Started	Apr 30 02:22:40 PM PDT 24
Finished	Apr 30 02:22:58 PM PDT 24
Peak memory	248688 kb
Host	smart-9e793a8c-f67e-43af-af6b-bb19b8415ff3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98737 990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.98737990
Directory	/workspace/28.alert_handler_smoke/latest

Test location	/workspace/coverage/default/29.alert_handler_entropy.1065727086
Short name	T573
Test name
Test status
Simulation time	46910523916 ps
CPU time	1567.8 seconds
Started	Apr 30 02:22:39 PM PDT 24
Finished	Apr 30 02:48:47 PM PDT 24
Peak memory	289196 kb
Host	smart-9caf6367-4ec9-4063-8896-52e685fe0a00
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1065727086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.1065727086
Directory	/workspace/29.alert_handler_entropy/latest

Test location	/workspace/coverage/default/29.alert_handler_esc_alert_accum.1861883847
Short name	T549
Test name
Test status
Simulation time	3649893245 ps
CPU time	239.99 seconds
Started	Apr 30 02:22:42 PM PDT 24
Finished	Apr 30 02:26:42 PM PDT 24
Peak memory	256876 kb
Host	smart-d99bcd27-554e-4613-9e99-148586875289
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18618 83847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.1861883847
Directory	/workspace/29.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/29.alert_handler_esc_intr_timeout.3791683364
Short name	T619
Test name
Test status
Simulation time	341567977 ps
CPU time	9.67 seconds
Started	Apr 30 02:22:40 PM PDT 24
Finished	Apr 30 02:22:50 PM PDT 24
Peak memory	253040 kb
Host	smart-348331cb-7ed3-4bd1-86e1-eb6a1ffb196e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37916 83364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.3791683364
Directory	/workspace/29.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/29.alert_handler_lpg.3658840601
Short name	T132
Test name
Test status
Simulation time	82387194517 ps
CPU time	2322.65 seconds
Started	Apr 30 02:22:41 PM PDT 24
Finished	Apr 30 03:01:24 PM PDT 24
Peak memory	288080 kb
Host	smart-eaccd70b-7278-4f88-bc22-4372e00d606d
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3658840601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.3658840601
Directory	/workspace/29.alert_handler_lpg/latest

Test location	/workspace/coverage/default/29.alert_handler_lpg_stub_clk.2795248380
Short name	T67
Test name
Test status
Simulation time	12196389198 ps
CPU time	1046.42 seconds
Started	Apr 30 02:22:45 PM PDT 24
Finished	Apr 30 02:40:12 PM PDT 24
Peak memory	288912 kb
Host	smart-f66f6dd3-53e0-45bb-b632-f68cbc8ce4f5
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2795248380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.2795248380
Directory	/workspace/29.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/29.alert_handler_ping_timeout.3133533219
Short name	T341
Test name
Test status
Simulation time	19264919350 ps
CPU time	377.12 seconds
Started	Apr 30 02:22:45 PM PDT 24
Finished	Apr 30 02:29:03 PM PDT 24
Peak memory	248152 kb
Host	smart-39a1357d-6913-4f37-b20b-7c466dc2c1a5
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3133533219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.3133533219
Directory	/workspace/29.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/29.alert_handler_random_alerts.1085378338
Short name	T580
Test name
Test status
Simulation time	249750958 ps
CPU time	24.39 seconds
Started	Apr 30 02:22:45 PM PDT 24
Finished	Apr 30 02:23:10 PM PDT 24
Peak memory	256828 kb
Host	smart-217b5368-5d4e-46a6-bb96-dd72851b6b4c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10853 78338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.1085378338
Directory	/workspace/29.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/29.alert_handler_random_classes.2541489366
Short name	T471
Test name
Test status
Simulation time	908486859 ps
CPU time	24.53 seconds
Started	Apr 30 02:22:40 PM PDT 24
Finished	Apr 30 02:23:05 PM PDT 24
Peak memory	248660 kb
Host	smart-8e52d1d6-39de-460c-ad30-058f0010e436
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25414 89366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.2541489366
Directory	/workspace/29.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/29.alert_handler_sig_int_fail.2633942105
Short name	T270
Test name
Test status
Simulation time	701619623 ps
CPU time	24.02 seconds
Started	Apr 30 02:22:44 PM PDT 24
Finished	Apr 30 02:23:09 PM PDT 24
Peak memory	254908 kb
Host	smart-8af60bec-dac2-4915-ba30-164dc057a773
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26339 42105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.2633942105
Directory	/workspace/29.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/29.alert_handler_smoke.1360131395
Short name	T568
Test name
Test status
Simulation time	1498796111 ps
CPU time	47.24 seconds
Started	Apr 30 02:22:38 PM PDT 24
Finished	Apr 30 02:23:25 PM PDT 24
Peak memory	248692 kb
Host	smart-3203791a-253d-4200-96a1-b4cc12a63add
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13601 31395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.1360131395
Directory	/workspace/29.alert_handler_smoke/latest

Test location	/workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.1643815761
Short name	T673
Test name
Test status
Simulation time	77389701167 ps
CPU time	3675.96 seconds
Started	Apr 30 02:22:48 PM PDT 24
Finished	Apr 30 03:24:05 PM PDT 24
Peak memory	306064 kb
Host	smart-8eef3091-8d07-444c-a209-b86da3ee68ad
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643815761 -assert nopostproc +UVM_TESTNAME=aler t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.1643815761
Directory	/workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/3.alert_handler_alert_accum_saturation.3590328054
Short name	T242
Test name
Test status
Simulation time	33419464 ps
CPU time	3.66 seconds
Started	Apr 30 02:21:40 PM PDT 24
Finished	Apr 30 02:21:44 PM PDT 24
Peak memory	248920 kb
Host	smart-bcd00d0c-f666-4aca-b2b1-070cb3387514
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3590328054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.3590328054
Directory	/workspace/3.alert_handler_alert_accum_saturation/latest

Test location	/workspace/coverage/default/3.alert_handler_entropy.1243131175
Short name	T524
Test name
Test status
Simulation time	43176223986 ps
CPU time	923.81 seconds
Started	Apr 30 02:21:38 PM PDT 24
Finished	Apr 30 02:37:03 PM PDT 24
Peak memory	273372 kb
Host	smart-7fad7d89-4bdf-48d6-b67d-9558280ec4c5
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1243131175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.1243131175
Directory	/workspace/3.alert_handler_entropy/latest

Test location	/workspace/coverage/default/3.alert_handler_entropy_stress.3627444497
Short name	T417
Test name
Test status
Simulation time	2197343469 ps
CPU time	8.77 seconds
Started	Apr 30 02:21:39 PM PDT 24
Finished	Apr 30 02:21:48 PM PDT 24
Peak memory	248748 kb
Host	smart-9b2b3cad-8d1c-4948-b774-02c6485e047d
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3627444497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.3627444497
Directory	/workspace/3.alert_handler_entropy_stress/latest

Test location	/workspace/coverage/default/3.alert_handler_esc_alert_accum.1924108992
Short name	T468
Test name
Test status
Simulation time	18994861110 ps
CPU time	255.76 seconds
Started	Apr 30 02:21:38 PM PDT 24
Finished	Apr 30 02:25:55 PM PDT 24
Peak memory	256764 kb
Host	smart-f34052d2-dc75-4c22-811a-5f751da7e70e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19241 08992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.1924108992
Directory	/workspace/3.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/3.alert_handler_esc_intr_timeout.3183872194
Short name	T538
Test name
Test status
Simulation time	2119399744 ps
CPU time	55.14 seconds
Started	Apr 30 02:21:44 PM PDT 24
Finished	Apr 30 02:22:40 PM PDT 24
Peak memory	254940 kb
Host	smart-03f01148-511f-4d00-ac46-72b2735a9679
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31838 72194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.3183872194
Directory	/workspace/3.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/3.alert_handler_lpg_stub_clk.3433822620
Short name	T650
Test name
Test status
Simulation time	51303778404 ps
CPU time	1666.47 seconds
Started	Apr 30 02:21:36 PM PDT 24
Finished	Apr 30 02:49:23 PM PDT 24
Peak memory	283060 kb
Host	smart-26d3ce19-e5ce-4316-913d-621a7ef75354
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3433822620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.3433822620
Directory	/workspace/3.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/3.alert_handler_ping_timeout.1423016523
Short name	T323
Test name
Test status
Simulation time	9794661766 ps
CPU time	414.29 seconds
Started	Apr 30 02:21:42 PM PDT 24
Finished	Apr 30 02:28:37 PM PDT 24
Peak memory	255360 kb
Host	smart-a8985251-7c03-4c91-88a4-edb54163fbbd
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1423016523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.1423016523
Directory	/workspace/3.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/3.alert_handler_random_alerts.2573761133
Short name	T97
Test name
Test status
Simulation time	2903773267 ps
CPU time	48.09 seconds
Started	Apr 30 02:21:28 PM PDT 24
Finished	Apr 30 02:22:17 PM PDT 24
Peak memory	248788 kb
Host	smart-872e6f8f-1b58-4ca9-ae36-3e6f15f5f36e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25737 61133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.2573761133
Directory	/workspace/3.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/3.alert_handler_random_classes.345384540
Short name	T464
Test name
Test status
Simulation time	249744787 ps
CPU time	21.05 seconds
Started	Apr 30 02:21:43 PM PDT 24
Finished	Apr 30 02:22:05 PM PDT 24
Peak memory	248648 kb
Host	smart-f1c0d644-72c1-42d0-885d-3c6aa66c93c5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34538 4540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.345384540
Directory	/workspace/3.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/3.alert_handler_sig_int_fail.3295841632
Short name	T51
Test name
Test status
Simulation time	434221870 ps
CPU time	15.11 seconds
Started	Apr 30 02:21:49 PM PDT 24
Finished	Apr 30 02:22:05 PM PDT 24
Peak memory	254824 kb
Host	smart-05d0c9e4-0ce5-4425-9a18-3169cd0d3c06
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32958 41632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.3295841632
Directory	/workspace/3.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/3.alert_handler_smoke.2662935515
Short name	T388
Test name
Test status
Simulation time	1099787272 ps
CPU time	17.06 seconds
Started	Apr 30 02:21:32 PM PDT 24
Finished	Apr 30 02:21:49 PM PDT 24
Peak memory	248656 kb
Host	smart-7e5e49a4-5133-4d30-8c08-42b1b2a4fc80
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26629 35515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.2662935515
Directory	/workspace/3.alert_handler_smoke/latest

Test location	/workspace/coverage/default/3.alert_handler_stress_all.3628620648
Short name	T423
Test name
Test status
Simulation time	5345321352 ps
CPU time	134.74 seconds
Started	Apr 30 02:21:37 PM PDT 24
Finished	Apr 30 02:23:52 PM PDT 24
Peak memory	256964 kb
Host	smart-f881b5c9-6bd3-4372-890d-29ad222a390e
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628620648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han dler_stress_all.3628620648
Directory	/workspace/3.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.1615888655
Short name	T212
Test name
Test status
Simulation time	448393848473 ps
CPU time	5738.27 seconds
Started	Apr 30 02:21:42 PM PDT 24
Finished	Apr 30 03:57:21 PM PDT 24
Peak memory	317888 kb
Host	smart-73c2de02-44fe-4c65-81ae-f9145fb68d7b
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615888655 -assert nopostproc +UVM_TESTNAME=aler t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.1615888655
Directory	/workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/30.alert_handler_entropy.3551600204
Short name	T688
Test name
Test status
Simulation time	35593670533 ps
CPU time	1969.62 seconds
Started	Apr 30 02:22:48 PM PDT 24
Finished	Apr 30 02:55:39 PM PDT 24
Peak memory	273204 kb
Host	smart-a71af838-a1f0-422b-87e7-c47698eed4af
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3551600204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.3551600204
Directory	/workspace/30.alert_handler_entropy/latest

Test location	/workspace/coverage/default/30.alert_handler_esc_alert_accum.1418348056
Short name	T517
Test name
Test status
Simulation time	4981513675 ps
CPU time	103.9 seconds
Started	Apr 30 02:22:47 PM PDT 24
Finished	Apr 30 02:24:31 PM PDT 24
Peak memory	250152 kb
Host	smart-a68be163-9382-4ee9-8247-fed5acbd9ef4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14183 48056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.1418348056
Directory	/workspace/30.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/30.alert_handler_esc_intr_timeout.3737687360
Short name	T396
Test name
Test status
Simulation time	27777650 ps
CPU time	3.93 seconds
Started	Apr 30 02:22:48 PM PDT 24
Finished	Apr 30 02:22:53 PM PDT 24
Peak memory	239172 kb
Host	smart-0f589d30-34f3-42d8-9b94-45c62f7ff8eb
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37376 87360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.3737687360
Directory	/workspace/30.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/30.alert_handler_lpg.1302105173
Short name	T257
Test name
Test status
Simulation time	30785496364 ps
CPU time	689.07 seconds
Started	Apr 30 02:22:52 PM PDT 24
Finished	Apr 30 02:34:22 PM PDT 24
Peak memory	266204 kb
Host	smart-0d4bccff-7ea4-4850-bd05-895c37845c81
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1302105173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.1302105173
Directory	/workspace/30.alert_handler_lpg/latest

Test location	/workspace/coverage/default/30.alert_handler_lpg_stub_clk.2515670200
Short name	T63
Test name
Test status
Simulation time	128523595224 ps
CPU time	1913.24 seconds
Started	Apr 30 02:22:45 PM PDT 24
Finished	Apr 30 02:54:39 PM PDT 24
Peak memory	273380 kb
Host	smart-fe2ac63d-345a-41d5-90e1-186307285dd1
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2515670200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.2515670200
Directory	/workspace/30.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/30.alert_handler_random_alerts.4101386075
Short name	T667
Test name
Test status
Simulation time	760565769 ps
CPU time	9.97 seconds
Started	Apr 30 02:22:45 PM PDT 24
Finished	Apr 30 02:22:56 PM PDT 24
Peak memory	256796 kb
Host	smart-75191fd5-6df9-4ada-8d04-64cbf36af73c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41013 86075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.4101386075
Directory	/workspace/30.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/30.alert_handler_random_classes.3846948342
Short name	T131
Test name
Test status
Simulation time	535258946 ps
CPU time	15.14 seconds
Started	Apr 30 02:22:47 PM PDT 24
Finished	Apr 30 02:23:03 PM PDT 24
Peak memory	248680 kb
Host	smart-3aee18b5-5c5a-47e8-87e5-fed1ff765292
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38469 48342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.3846948342
Directory	/workspace/30.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/30.alert_handler_sig_int_fail.2600201602
Short name	T440
Test name
Test status
Simulation time	1449875303 ps
CPU time	10.82 seconds
Started	Apr 30 02:22:47 PM PDT 24
Finished	Apr 30 02:22:58 PM PDT 24
Peak memory	248672 kb
Host	smart-0f817d79-4718-42e5-a7ab-49e16a4d7e5e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26002 01602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.2600201602
Directory	/workspace/30.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/30.alert_handler_smoke.4243033402
Short name	T522
Test name
Test status
Simulation time	3223476965 ps
CPU time	44.41 seconds
Started	Apr 30 02:22:51 PM PDT 24
Finished	Apr 30 02:23:36 PM PDT 24
Peak memory	256000 kb
Host	smart-53aaf857-3cfd-4017-a7c1-e59c06c9173e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42430 33402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.4243033402
Directory	/workspace/30.alert_handler_smoke/latest

Test location	/workspace/coverage/default/30.alert_handler_stress_all.2041319274
Short name	T514
Test name
Test status
Simulation time	46534903098 ps
CPU time	1611.3 seconds
Started	Apr 30 02:22:46 PM PDT 24
Finished	Apr 30 02:49:38 PM PDT 24
Peak memory	273280 kb
Host	smart-18ccb22a-fa88-45a7-9e92-78f68b92fc4c
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041319274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha ndler_stress_all.2041319274
Directory	/workspace/30.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/31.alert_handler_entropy.4051668238
Short name	T621
Test name
Test status
Simulation time	33307376063 ps
CPU time	2120.3 seconds
Started	Apr 30 02:22:46 PM PDT 24
Finished	Apr 30 02:58:07 PM PDT 24
Peak memory	281536 kb
Host	smart-bd6de4b9-eb4c-44f6-bc17-87e4ac7d6537
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4051668238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.4051668238
Directory	/workspace/31.alert_handler_entropy/latest

Test location	/workspace/coverage/default/31.alert_handler_esc_alert_accum.926921896
Short name	T680
Test name
Test status
Simulation time	158741346 ps
CPU time	22.1 seconds
Started	Apr 30 02:22:55 PM PDT 24
Finished	Apr 30 02:23:17 PM PDT 24
Peak memory	255372 kb
Host	smart-fb504676-c882-497b-93b7-474d65b83cff
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92692 1896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.926921896
Directory	/workspace/31.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/31.alert_handler_esc_intr_timeout.2808697044
Short name	T280
Test name
Test status
Simulation time	213697632 ps
CPU time	21.51 seconds
Started	Apr 30 02:22:48 PM PDT 24
Finished	Apr 30 02:23:10 PM PDT 24
Peak memory	254156 kb
Host	smart-b2818590-b02b-4e66-acb1-89c99985141e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28086 97044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.2808697044
Directory	/workspace/31.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/31.alert_handler_lpg.3262737039
Short name	T299
Test name
Test status
Simulation time	11321550909 ps
CPU time	878.01 seconds
Started	Apr 30 02:22:44 PM PDT 24
Finished	Apr 30 02:37:23 PM PDT 24
Peak memory	273316 kb
Host	smart-b8373ded-8af2-43dd-a567-7645bcde7c23
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3262737039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.3262737039
Directory	/workspace/31.alert_handler_lpg/latest

Test location	/workspace/coverage/default/31.alert_handler_lpg_stub_clk.2114854553
Short name	T557
Test name
Test status
Simulation time	10532690025 ps
CPU time	1203.65 seconds
Started	Apr 30 02:22:47 PM PDT 24
Finished	Apr 30 02:42:51 PM PDT 24
Peak memory	281540 kb
Host	smart-751d4810-1a22-4124-9913-3514bf9c9130
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2114854553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.2114854553
Directory	/workspace/31.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/31.alert_handler_ping_timeout.4281285385
Short name	T340
Test name
Test status
Simulation time	116400196984 ps
CPU time	424.86 seconds
Started	Apr 30 02:22:47 PM PDT 24
Finished	Apr 30 02:29:53 PM PDT 24
Peak memory	255168 kb
Host	smart-1b8e4bb4-24f5-44e8-b57a-e797b70f178f
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4281285385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.4281285385
Directory	/workspace/31.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/31.alert_handler_random_alerts.378158562
Short name	T701
Test name
Test status
Simulation time	206817775 ps
CPU time	7.94 seconds
Started	Apr 30 02:22:47 PM PDT 24
Finished	Apr 30 02:22:56 PM PDT 24
Peak memory	252380 kb
Host	smart-5d8e8462-8a61-4510-9565-d56b212ad05b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37815 8562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.378158562
Directory	/workspace/31.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/31.alert_handler_random_classes.2981956834
Short name	T590
Test name
Test status
Simulation time	504324402 ps
CPU time	32.62 seconds
Started	Apr 30 02:22:45 PM PDT 24
Finished	Apr 30 02:23:18 PM PDT 24
Peak memory	248984 kb
Host	smart-b2391631-c657-4b64-a243-964b8079b528
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29819 56834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.2981956834
Directory	/workspace/31.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/31.alert_handler_sig_int_fail.468797221
Short name	T93
Test name
Test status
Simulation time	1041286132 ps
CPU time	32.7 seconds
Started	Apr 30 02:22:50 PM PDT 24
Finished	Apr 30 02:23:23 PM PDT 24
Peak memory	255296 kb
Host	smart-1c806907-6c7f-4487-a6a1-d816ce7ee993
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46879 7221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.468797221
Directory	/workspace/31.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/31.alert_handler_smoke.2139395654
Short name	T575
Test name
Test status
Simulation time	861140406 ps
CPU time	35.58 seconds
Started	Apr 30 02:22:45 PM PDT 24
Finished	Apr 30 02:23:22 PM PDT 24
Peak memory	255924 kb
Host	smart-5d1635c2-3ad5-4d3e-9e9a-cb91a3972fac
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21393 95654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.2139395654
Directory	/workspace/31.alert_handler_smoke/latest

Test location	/workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.736466938
Short name	T316
Test name
Test status
Simulation time	179838765203 ps
CPU time	2869.88 seconds
Started	Apr 30 02:22:45 PM PDT 24
Finished	Apr 30 03:10:36 PM PDT 24
Peak memory	306168 kb
Host	smart-677b9e27-aba1-4627-aa9a-8d4a13147b71
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736466938 -assert nopostproc +UVM_TESTNAME=alert _handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.736466938
Directory	/workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/32.alert_handler_entropy.368739119
Short name	T85
Test name
Test status
Simulation time	36400593463 ps
CPU time	2148.99 seconds
Started	Apr 30 02:22:51 PM PDT 24
Finished	Apr 30 02:58:41 PM PDT 24
Peak memory	273284 kb
Host	smart-70b493e2-b1cf-4af3-a324-0326017040f4
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=368739119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.368739119
Directory	/workspace/32.alert_handler_entropy/latest

Test location	/workspace/coverage/default/32.alert_handler_esc_alert_accum.1224790817
Short name	T663
Test name
Test status
Simulation time	4042824866 ps
CPU time	259.34 seconds
Started	Apr 30 02:22:57 PM PDT 24
Finished	Apr 30 02:27:17 PM PDT 24
Peak memory	256132 kb
Host	smart-209ecddc-d5fb-42dc-b184-0dbd52eba8c3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12247 90817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.1224790817
Directory	/workspace/32.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/32.alert_handler_esc_intr_timeout.1213768484
Short name	T615
Test name
Test status
Simulation time	4656350170 ps
CPU time	82.64 seconds
Started	Apr 30 02:22:52 PM PDT 24
Finished	Apr 30 02:24:15 PM PDT 24
Peak memory	256128 kb
Host	smart-f7972ec0-119e-4fea-bd43-d8e163c0a32b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12137 68484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.1213768484
Directory	/workspace/32.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/32.alert_handler_lpg.3469338616
Short name	T310
Test name
Test status
Simulation time	173699042136 ps
CPU time	2703.34 seconds
Started	Apr 30 02:22:53 PM PDT 24
Finished	Apr 30 03:07:57 PM PDT 24
Peak memory	288832 kb
Host	smart-fde4e39c-b13c-4d20-bc5c-b5f1e85b263b
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3469338616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.3469338616
Directory	/workspace/32.alert_handler_lpg/latest

Test location	/workspace/coverage/default/32.alert_handler_lpg_stub_clk.2951246272
Short name	T479
Test name
Test status
Simulation time	44870622024 ps
CPU time	1231.78 seconds
Started	Apr 30 02:22:52 PM PDT 24
Finished	Apr 30 02:43:24 PM PDT 24
Peak memory	281548 kb
Host	smart-af562e64-61a8-4210-b689-74f1f1ce13b2
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2951246272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.2951246272
Directory	/workspace/32.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/32.alert_handler_ping_timeout.634845553
Short name	T70
Test name
Test status
Simulation time	1928417985 ps
CPU time	77.06 seconds
Started	Apr 30 02:22:50 PM PDT 24
Finished	Apr 30 02:24:07 PM PDT 24
Peak memory	248100 kb
Host	smart-f6076add-2a60-40a6-a4b4-e56c4f5e95b8
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=634845553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.634845553
Directory	/workspace/32.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/32.alert_handler_random_alerts.3356287587
Short name	T605
Test name
Test status
Simulation time	1329519265 ps
CPU time	67.45 seconds
Started	Apr 30 02:22:53 PM PDT 24
Finished	Apr 30 02:24:01 PM PDT 24
Peak memory	256104 kb
Host	smart-2bca72d0-96d1-4644-a720-189c4ba0ebd9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33562 87587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.3356287587
Directory	/workspace/32.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/32.alert_handler_random_classes.2872243386
Short name	T421
Test name
Test status
Simulation time	4723840537 ps
CPU time	74.47 seconds
Started	Apr 30 02:22:49 PM PDT 24
Finished	Apr 30 02:24:04 PM PDT 24
Peak memory	256196 kb
Host	smart-5fa2c203-62b1-4974-825b-0b66a50bb3a4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28722 43386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.2872243386
Directory	/workspace/32.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/32.alert_handler_sig_int_fail.3498089180
Short name	T285
Test name
Test status
Simulation time	251472941 ps
CPU time	27.56 seconds
Started	Apr 30 02:22:52 PM PDT 24
Finished	Apr 30 02:23:21 PM PDT 24
Peak memory	248724 kb
Host	smart-6ad1edc3-cdc8-4692-856c-cb238a7b08ce
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34980 89180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.3498089180
Directory	/workspace/32.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/32.alert_handler_smoke.1548107285
Short name	T307
Test name
Test status
Simulation time	114179295 ps
CPU time	7.91 seconds
Started	Apr 30 02:22:46 PM PDT 24
Finished	Apr 30 02:22:55 PM PDT 24
Peak memory	252048 kb
Host	smart-2cde52fe-7f22-4be1-8d96-623b9d228143
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15481 07285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.1548107285
Directory	/workspace/32.alert_handler_smoke/latest

Test location	/workspace/coverage/default/32.alert_handler_stress_all.1845798727
Short name	T658
Test name
Test status
Simulation time	10857932351 ps
CPU time	1107.79 seconds
Started	Apr 30 02:22:53 PM PDT 24
Finished	Apr 30 02:41:21 PM PDT 24
Peak memory	282344 kb
Host	smart-caa0a183-c36a-4be8-8f26-49d084bcc0ff
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845798727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha ndler_stress_all.1845798727
Directory	/workspace/32.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/33.alert_handler_entropy.4242114753
Short name	T677
Test name
Test status
Simulation time	133292039852 ps
CPU time	1883.05 seconds
Started	Apr 30 02:22:52 PM PDT 24
Finished	Apr 30 02:54:16 PM PDT 24
Peak memory	272476 kb
Host	smart-68e6ccee-c355-4209-aaa6-98701be61117
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4242114753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.4242114753
Directory	/workspace/33.alert_handler_entropy/latest

Test location	/workspace/coverage/default/33.alert_handler_esc_alert_accum.4197200175
Short name	T606
Test name
Test status
Simulation time	307865026 ps
CPU time	4.25 seconds
Started	Apr 30 02:22:52 PM PDT 24
Finished	Apr 30 02:22:57 PM PDT 24
Peak memory	240508 kb
Host	smart-13f66a4f-5968-466b-8477-1ef83a5ffb71
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41972 00175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.4197200175
Directory	/workspace/33.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/33.alert_handler_esc_intr_timeout.1656297066
Short name	T506
Test name
Test status
Simulation time	1359720352 ps
CPU time	77.07 seconds
Started	Apr 30 02:22:53 PM PDT 24
Finished	Apr 30 02:24:10 PM PDT 24
Peak memory	255984 kb
Host	smart-178ea504-de9b-46a2-b702-18ffe7b2a7d1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16562 97066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.1656297066
Directory	/workspace/33.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/33.alert_handler_lpg.1332592712
Short name	T360
Test name
Test status
Simulation time	7936519012 ps
CPU time	823.74 seconds
Started	Apr 30 02:22:51 PM PDT 24
Finished	Apr 30 02:36:35 PM PDT 24
Peak memory	272568 kb
Host	smart-b959fd0b-1e9f-4278-899a-99a874041233
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1332592712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.1332592712
Directory	/workspace/33.alert_handler_lpg/latest

Test location	/workspace/coverage/default/33.alert_handler_lpg_stub_clk.3734937179
Short name	T572
Test name
Test status
Simulation time	133065153629 ps
CPU time	2040.62 seconds
Started	Apr 30 02:22:51 PM PDT 24
Finished	Apr 30 02:56:53 PM PDT 24
Peak memory	269288 kb
Host	smart-c0da3368-1908-4062-b701-ccc187a1fd24
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3734937179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.3734937179
Directory	/workspace/33.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/33.alert_handler_ping_timeout.3884352695
Short name	T331
Test name
Test status
Simulation time	13465683805 ps
CPU time	259.44 seconds
Started	Apr 30 02:22:53 PM PDT 24
Finished	Apr 30 02:27:13 PM PDT 24
Peak memory	246836 kb
Host	smart-6cb7a40e-08ca-4e38-9460-386043c28804
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3884352695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.3884352695
Directory	/workspace/33.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/33.alert_handler_random_alerts.3085765019
Short name	T435
Test name
Test status
Simulation time	670990906 ps
CPU time	23.55 seconds
Started	Apr 30 02:22:58 PM PDT 24
Finished	Apr 30 02:23:22 PM PDT 24
Peak memory	248720 kb
Host	smart-ec098d12-4b19-4b27-918a-b75510da149c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30857 65019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.3085765019
Directory	/workspace/33.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/33.alert_handler_random_classes.1443128380
Short name	T140
Test name
Test status
Simulation time	562424387 ps
CPU time	39.74 seconds
Started	Apr 30 02:22:52 PM PDT 24
Finished	Apr 30 02:23:33 PM PDT 24
Peak memory	248732 kb
Host	smart-d40b4fbf-61c6-4d11-84fe-ebc11503f0d0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14431 28380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.1443128380
Directory	/workspace/33.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/33.alert_handler_sig_int_fail.387798196
Short name	T487
Test name
Test status
Simulation time	619408546 ps
CPU time	20.62 seconds
Started	Apr 30 02:22:58 PM PDT 24
Finished	Apr 30 02:23:19 PM PDT 24
Peak memory	248724 kb
Host	smart-81845430-a454-44ea-9ce2-8b77877c644f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38779 8196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.387798196
Directory	/workspace/33.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/33.alert_handler_smoke.3941624628
Short name	T600
Test name
Test status
Simulation time	300779766 ps
CPU time	20.36 seconds
Started	Apr 30 02:22:58 PM PDT 24
Finished	Apr 30 02:23:18 PM PDT 24
Peak memory	248720 kb
Host	smart-2d63e35a-5232-41e7-88ad-6e286ab93c86
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39416 24628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.3941624628
Directory	/workspace/33.alert_handler_smoke/latest

Test location	/workspace/coverage/default/34.alert_handler_entropy.1308988995
Short name	T300
Test name
Test status
Simulation time	105799162223 ps
CPU time	1540.57 seconds
Started	Apr 30 02:22:59 PM PDT 24
Finished	Apr 30 02:48:40 PM PDT 24
Peak memory	273256 kb
Host	smart-b2a7c8b7-61e9-4511-bf90-b31df5d05306
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1308988995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.1308988995
Directory	/workspace/34.alert_handler_entropy/latest

Test location	/workspace/coverage/default/34.alert_handler_esc_alert_accum.4111994430
Short name	T692
Test name
Test status
Simulation time	4027999984 ps
CPU time	155.63 seconds
Started	Apr 30 02:22:57 PM PDT 24
Finished	Apr 30 02:25:33 PM PDT 24
Peak memory	256972 kb
Host	smart-40ce33f9-8196-4101-842e-8b94442699b6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41119 94430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.4111994430
Directory	/workspace/34.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/34.alert_handler_esc_intr_timeout.4124221600
Short name	T499
Test name
Test status
Simulation time	3178554376 ps
CPU time	56.49 seconds
Started	Apr 30 02:22:51 PM PDT 24
Finished	Apr 30 02:23:48 PM PDT 24
Peak memory	248732 kb
Host	smart-d45949e8-a6c6-4c9b-8416-edab5cdff99f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41242 21600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.4124221600
Directory	/workspace/34.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/34.alert_handler_lpg_stub_clk.3973014518
Short name	T484
Test name
Test status
Simulation time	74691323467 ps
CPU time	1114.57 seconds
Started	Apr 30 02:22:58 PM PDT 24
Finished	Apr 30 02:41:33 PM PDT 24
Peak memory	273088 kb
Host	smart-4ae3fec0-d960-4a68-b317-654d0520233e
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3973014518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.3973014518
Directory	/workspace/34.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/34.alert_handler_ping_timeout.3182287404
Short name	T69
Test name
Test status
Simulation time	11537548764 ps
CPU time	478.7 seconds
Started	Apr 30 02:23:00 PM PDT 24
Finished	Apr 30 02:30:59 PM PDT 24
Peak memory	247152 kb
Host	smart-fd760125-c9c0-408a-b849-a22f7b50c877
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3182287404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.3182287404
Directory	/workspace/34.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/34.alert_handler_random_alerts.1145949100
Short name	T311
Test name
Test status
Simulation time	38570102 ps
CPU time	3.9 seconds
Started	Apr 30 02:22:59 PM PDT 24
Finished	Apr 30 02:23:03 PM PDT 24
Peak memory	240528 kb
Host	smart-8f4e0318-d78c-40f6-a5f0-678fc0727aa6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11459 49100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.1145949100
Directory	/workspace/34.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/34.alert_handler_random_classes.912054387
Short name	T607
Test name
Test status
Simulation time	453206423 ps
CPU time	8.51 seconds
Started	Apr 30 02:22:54 PM PDT 24
Finished	Apr 30 02:23:02 PM PDT 24
Peak memory	248680 kb
Host	smart-a2216f68-069f-452c-bb3f-22a257e7b8d1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91205 4387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.912054387
Directory	/workspace/34.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/34.alert_handler_sig_int_fail.1014631960
Short name	T622
Test name
Test status
Simulation time	61213965 ps
CPU time	4.85 seconds
Started	Apr 30 02:23:00 PM PDT 24
Finished	Apr 30 02:23:05 PM PDT 24
Peak memory	240512 kb
Host	smart-69515c85-ffd7-466e-8e61-8e6f94a016df
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10146 31960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.1014631960
Directory	/workspace/34.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/34.alert_handler_smoke.1180635990
Short name	T597
Test name
Test status
Simulation time	638804537 ps
CPU time	11.05 seconds
Started	Apr 30 02:22:52 PM PDT 24
Finished	Apr 30 02:23:04 PM PDT 24
Peak memory	248692 kb
Host	smart-7027f116-f3e9-4faa-9636-fcf3e2cdad20
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11806 35990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.1180635990
Directory	/workspace/34.alert_handler_smoke/latest

Test location	/workspace/coverage/default/35.alert_handler_esc_alert_accum.115546645
Short name	T490
Test name
Test status
Simulation time	4625906832 ps
CPU time	62.26 seconds
Started	Apr 30 02:22:57 PM PDT 24
Finished	Apr 30 02:24:00 PM PDT 24
Peak memory	249180 kb
Host	smart-f1f48305-9cc3-458a-9178-cac85058ad8f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11554 6645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.115546645
Directory	/workspace/35.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/35.alert_handler_esc_intr_timeout.2067262548
Short name	T528
Test name
Test status
Simulation time	268037601 ps
CPU time	11.95 seconds
Started	Apr 30 02:22:57 PM PDT 24
Finished	Apr 30 02:23:09 PM PDT 24
Peak memory	254852 kb
Host	smart-c1179560-9820-4e63-8c1c-eede1d39b7b5
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20672 62548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.2067262548
Directory	/workspace/35.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/35.alert_handler_lpg.1250160565
Short name	T362
Test name
Test status
Simulation time	73214347526 ps
CPU time	1530.56 seconds
Started	Apr 30 02:22:58 PM PDT 24
Finished	Apr 30 02:48:30 PM PDT 24
Peak memory	288856 kb
Host	smart-4058499d-19cc-4ecb-bf56-7b01b5260d6e
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1250160565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.1250160565
Directory	/workspace/35.alert_handler_lpg/latest

Test location	/workspace/coverage/default/35.alert_handler_lpg_stub_clk.620808238
Short name	T459
Test name
Test status
Simulation time	229074641839 ps
CPU time	3319.56 seconds
Started	Apr 30 02:22:59 PM PDT 24
Finished	Apr 30 03:18:19 PM PDT 24
Peak memory	289372 kb
Host	smart-74068906-de3c-4bc1-ba12-ddd9ea893dd1
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=620808238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.620808238
Directory	/workspace/35.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/35.alert_handler_ping_timeout.2797059319
Short name	T577
Test name
Test status
Simulation time	7546668486 ps
CPU time	304.68 seconds
Started	Apr 30 02:23:01 PM PDT 24
Finished	Apr 30 02:28:06 PM PDT 24
Peak memory	248312 kb
Host	smart-1f361e22-d2e2-4178-bb55-47192ed35537
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2797059319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.2797059319
Directory	/workspace/35.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/35.alert_handler_random_alerts.1131912015
Short name	T456
Test name
Test status
Simulation time	3515515039 ps
CPU time	53.11 seconds
Started	Apr 30 02:22:59 PM PDT 24
Finished	Apr 30 02:23:52 PM PDT 24
Peak memory	256916 kb
Host	smart-e139ef76-a03a-49ad-ad8f-3ff101d862de
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11319 12015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.1131912015
Directory	/workspace/35.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/35.alert_handler_random_classes.1019616829
Short name	T304
Test name
Test status
Simulation time	387331123 ps
CPU time	28.32 seconds
Started	Apr 30 02:23:00 PM PDT 24
Finished	Apr 30 02:23:29 PM PDT 24
Peak memory	248704 kb
Host	smart-4256f207-6d82-4cc4-8b96-d6d4b15be0b6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10196 16829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.1019616829
Directory	/workspace/35.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/35.alert_handler_sig_int_fail.2075903813
Short name	T84
Test name
Test status
Simulation time	635071273 ps
CPU time	41.73 seconds
Started	Apr 30 02:22:57 PM PDT 24
Finished	Apr 30 02:23:39 PM PDT 24
Peak memory	248728 kb
Host	smart-7e9d1d1a-eede-4d78-8eb0-d6287bdd4b5c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20759 03813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.2075903813
Directory	/workspace/35.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/35.alert_handler_smoke.2388929082
Short name	T661
Test name
Test status
Simulation time	216819943 ps
CPU time	7.23 seconds
Started	Apr 30 02:22:58 PM PDT 24
Finished	Apr 30 02:23:06 PM PDT 24
Peak memory	253856 kb
Host	smart-9e3f626c-d11c-4c09-ae9d-5dc4a4e23251
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23889 29082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.2388929082
Directory	/workspace/35.alert_handler_smoke/latest

Test location	/workspace/coverage/default/35.alert_handler_stress_all.3120607119
Short name	T660
Test name
Test status
Simulation time	908239327 ps
CPU time	97.41 seconds
Started	Apr 30 02:22:59 PM PDT 24
Finished	Apr 30 02:24:37 PM PDT 24
Peak memory	257008 kb
Host	smart-da50094a-67b4-4424-89f8-7e866cd8cceb
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120607119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha ndler_stress_all.3120607119
Directory	/workspace/35.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/36.alert_handler_entropy.802794984
Short name	T137
Test name
Test status
Simulation time	32091754964 ps
CPU time	1321.37 seconds
Started	Apr 30 02:23:06 PM PDT 24
Finished	Apr 30 02:45:08 PM PDT 24
Peak memory	281500 kb
Host	smart-86e74570-a4d0-4e54-a344-ce005a09c7a6
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=802794984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.802794984
Directory	/workspace/36.alert_handler_entropy/latest

Test location	/workspace/coverage/default/36.alert_handler_esc_alert_accum.2999572334
Short name	T437
Test name
Test status
Simulation time	8079982259 ps
CPU time	241.91 seconds
Started	Apr 30 02:23:05 PM PDT 24
Finished	Apr 30 02:27:08 PM PDT 24
Peak memory	256784 kb
Host	smart-82776db3-5922-414b-ad7f-0662aed5c7bb
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29995 72334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.2999572334
Directory	/workspace/36.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/36.alert_handler_esc_intr_timeout.1109287245
Short name	T465
Test name
Test status
Simulation time	404574861 ps
CPU time	10.36 seconds
Started	Apr 30 02:23:05 PM PDT 24
Finished	Apr 30 02:23:16 PM PDT 24
Peak memory	254748 kb
Host	smart-1fd760a5-658e-4cff-a747-4ee2aee9afa9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11092 87245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.1109287245
Directory	/workspace/36.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/36.alert_handler_lpg.3799208702
Short name	T369
Test name
Test status
Simulation time	53986629687 ps
CPU time	1860.91 seconds
Started	Apr 30 02:23:07 PM PDT 24
Finished	Apr 30 02:54:08 PM PDT 24
Peak memory	272684 kb
Host	smart-f1c3e4b5-2ac3-4304-8d32-c085e2d5d080
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3799208702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.3799208702
Directory	/workspace/36.alert_handler_lpg/latest

Test location	/workspace/coverage/default/36.alert_handler_lpg_stub_clk.3996400582
Short name	T693
Test name
Test status
Simulation time	533030671779 ps
CPU time	2955.32 seconds
Started	Apr 30 02:23:06 PM PDT 24
Finished	Apr 30 03:12:22 PM PDT 24
Peak memory	281488 kb
Host	smart-5ca79e67-2057-49ab-bbbf-548e0fb3d99e
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3996400582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.3996400582
Directory	/workspace/36.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/36.alert_handler_ping_timeout.3489688807
Short name	T333
Test name
Test status
Simulation time	42105358573 ps
CPU time	101.18 seconds
Started	Apr 30 02:23:06 PM PDT 24
Finished	Apr 30 02:24:48 PM PDT 24
Peak memory	247880 kb
Host	smart-d4c1f678-56a2-4f5f-ad0a-d76c4fe5b4b7
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3489688807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.3489688807
Directory	/workspace/36.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/36.alert_handler_random_alerts.2655155186
Short name	T638
Test name
Test status
Simulation time	982557081 ps
CPU time	45.41 seconds
Started	Apr 30 02:22:59 PM PDT 24
Finished	Apr 30 02:23:45 PM PDT 24
Peak memory	255864 kb
Host	smart-6a0e4287-ad66-490f-8e17-db89e41da65f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26551 55186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.2655155186
Directory	/workspace/36.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/36.alert_handler_random_classes.18135705
Short name	T547
Test name
Test status
Simulation time	112263686 ps
CPU time	7.17 seconds
Started	Apr 30 02:23:00 PM PDT 24
Finished	Apr 30 02:23:07 PM PDT 24
Peak memory	248716 kb
Host	smart-b9cf5c94-2329-4898-b332-d50bd11dbdde
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18135 705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.18135705
Directory	/workspace/36.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/36.alert_handler_sig_int_fail.3767616984
Short name	T676
Test name
Test status
Simulation time	1792200431 ps
CPU time	30.95 seconds
Started	Apr 30 02:23:07 PM PDT 24
Finished	Apr 30 02:23:38 PM PDT 24
Peak memory	248712 kb
Host	smart-11a3e962-14aa-44f6-81e0-81d0434505ab
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37676 16984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.3767616984
Directory	/workspace/36.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/36.alert_handler_smoke.1898033079
Short name	T443
Test name
Test status
Simulation time	534201921 ps
CPU time	27.97 seconds
Started	Apr 30 02:22:57 PM PDT 24
Finished	Apr 30 02:23:26 PM PDT 24
Peak memory	248704 kb
Host	smart-88030fba-3b4c-4660-8f62-16944dd529e2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18980 33079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.1898033079
Directory	/workspace/36.alert_handler_smoke/latest

Test location	/workspace/coverage/default/37.alert_handler_entropy.2349147102
Short name	T72
Test name
Test status
Simulation time	11114943220 ps
CPU time	955.87 seconds
Started	Apr 30 02:23:13 PM PDT 24
Finished	Apr 30 02:39:09 PM PDT 24
Peak memory	289252 kb
Host	smart-8b3f21b9-7635-4c78-9a8a-121074e67701
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2349147102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.2349147102
Directory	/workspace/37.alert_handler_entropy/latest

Test location	/workspace/coverage/default/37.alert_handler_esc_alert_accum.2393655497
Short name	T470
Test name
Test status
Simulation time	1758960593 ps
CPU time	146.3 seconds
Started	Apr 30 02:23:05 PM PDT 24
Finished	Apr 30 02:25:32 PM PDT 24
Peak memory	256896 kb
Host	smart-55c52024-8489-4f90-a4e6-f7fe162830ee
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23936 55497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.2393655497
Directory	/workspace/37.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/37.alert_handler_esc_intr_timeout.1846138247
Short name	T678
Test name
Test status
Simulation time	590407681 ps
CPU time	28.74 seconds
Started	Apr 30 02:23:03 PM PDT 24
Finished	Apr 30 02:23:32 PM PDT 24
Peak memory	255848 kb
Host	smart-b662e929-bb2a-4fc3-b650-f38535c9e6b9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18461 38247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.1846138247
Directory	/workspace/37.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/37.alert_handler_lpg.3981892029
Short name	T354
Test name
Test status
Simulation time	129469805175 ps
CPU time	2277.7 seconds
Started	Apr 30 02:23:12 PM PDT 24
Finished	Apr 30 03:01:10 PM PDT 24
Peak memory	281428 kb
Host	smart-5c98f936-ba5c-483a-b91d-ad2e94dc7ed6
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3981892029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.3981892029
Directory	/workspace/37.alert_handler_lpg/latest

Test location	/workspace/coverage/default/37.alert_handler_lpg_stub_clk.1628475774
Short name	T430
Test name
Test status
Simulation time	31617410764 ps
CPU time	1521.42 seconds
Started	Apr 30 02:23:13 PM PDT 24
Finished	Apr 30 02:48:34 PM PDT 24
Peak memory	272844 kb
Host	smart-41cc9a95-32d3-406a-be33-c8fa1e18b23b
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1628475774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.1628475774
Directory	/workspace/37.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/37.alert_handler_ping_timeout.2316648291
Short name	T339
Test name
Test status
Simulation time	17035789576 ps
CPU time	394.83 seconds
Started	Apr 30 02:23:14 PM PDT 24
Finished	Apr 30 02:29:49 PM PDT 24
Peak memory	248084 kb
Host	smart-f76b326c-b34e-40e6-be09-d92a731c68ce
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2316648291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.2316648291
Directory	/workspace/37.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/37.alert_handler_random_alerts.3600667282
Short name	T116
Test name
Test status
Simulation time	1621360684 ps
CPU time	16.33 seconds
Started	Apr 30 02:23:05 PM PDT 24
Finished	Apr 30 02:23:22 PM PDT 24
Peak memory	248644 kb
Host	smart-c2544a7c-c188-4fef-9dee-70db18f7dce6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36006 67282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.3600667282
Directory	/workspace/37.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/37.alert_handler_random_classes.1324223787
Short name	T585
Test name
Test status
Simulation time	1153161204 ps
CPU time	31.26 seconds
Started	Apr 30 02:23:05 PM PDT 24
Finished	Apr 30 02:23:37 PM PDT 24
Peak memory	248672 kb
Host	smart-d337fce0-6a17-416e-b051-d95ce023106b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13242 23787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.1324223787
Directory	/workspace/37.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/37.alert_handler_sig_int_fail.1612016120
Short name	T409
Test name
Test status
Simulation time	905237326 ps
CPU time	51.87 seconds
Started	Apr 30 02:23:05 PM PDT 24
Finished	Apr 30 02:23:58 PM PDT 24
Peak memory	248728 kb
Host	smart-2ddbcc72-ce15-49ed-9b97-27ba6e149322
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16120 16120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.1612016120
Directory	/workspace/37.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/37.alert_handler_smoke.1785737643
Short name	T392
Test name
Test status
Simulation time	849643083 ps
CPU time	47.02 seconds
Started	Apr 30 02:23:05 PM PDT 24
Finished	Apr 30 02:23:53 PM PDT 24
Peak memory	248704 kb
Host	smart-1ac3da7f-49f7-44a2-a6ec-18fe08261526
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17857 37643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.1785737643
Directory	/workspace/37.alert_handler_smoke/latest

Test location	/workspace/coverage/default/37.alert_handler_stress_all.3651981793
Short name	T586
Test name
Test status
Simulation time	121280729247 ps
CPU time	1545.06 seconds
Started	Apr 30 02:23:11 PM PDT 24
Finished	Apr 30 02:48:56 PM PDT 24
Peak memory	289640 kb
Host	smart-426641a1-d2ac-4185-b890-dec00062e96d
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651981793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha ndler_stress_all.3651981793
Directory	/workspace/37.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.3469382067
Short name	T546
Test name
Test status
Simulation time	517315181671 ps
CPU time	5320.99 seconds
Started	Apr 30 02:23:13 PM PDT 24
Finished	Apr 30 03:51:55 PM PDT 24
Peak memory	355104 kb
Host	smart-e75168a1-0786-433c-b5ad-8a397d677223
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469382067 -assert nopostproc +UVM_TESTNAME=aler t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.3469382067
Directory	/workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/38.alert_handler_entropy.2051745165
Short name	T404
Test name
Test status
Simulation time	275258708569 ps
CPU time	1341.02 seconds
Started	Apr 30 02:23:13 PM PDT 24
Finished	Apr 30 02:45:34 PM PDT 24
Peak memory	273260 kb
Host	smart-5dcd3e42-6907-4f08-9d10-12393599066e
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2051745165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.2051745165
Directory	/workspace/38.alert_handler_entropy/latest

Test location	/workspace/coverage/default/38.alert_handler_esc_alert_accum.440912711
Short name	T655
Test name
Test status
Simulation time	7823690768 ps
CPU time	237.83 seconds
Started	Apr 30 02:23:13 PM PDT 24
Finished	Apr 30 02:27:11 PM PDT 24
Peak memory	256940 kb
Host	smart-dcaa6a45-0f0b-4856-b05a-8ab418e96c96
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44091 2711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.440912711
Directory	/workspace/38.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/38.alert_handler_esc_intr_timeout.2278550026
Short name	T628
Test name
Test status
Simulation time	3685887392 ps
CPU time	56.23 seconds
Started	Apr 30 02:23:15 PM PDT 24
Finished	Apr 30 02:24:12 PM PDT 24
Peak memory	256324 kb
Host	smart-ce644a72-19a3-4dc4-98a5-8738817a400d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22785 50026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.2278550026
Directory	/workspace/38.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/38.alert_handler_lpg.1095481875
Short name	T699
Test name
Test status
Simulation time	52448585472 ps
CPU time	1421.87 seconds
Started	Apr 30 02:23:12 PM PDT 24
Finished	Apr 30 02:46:55 PM PDT 24
Peak memory	272712 kb
Host	smart-21b1af83-474d-49f5-9b72-36cd77102a5c
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1095481875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.1095481875
Directory	/workspace/38.alert_handler_lpg/latest

Test location	/workspace/coverage/default/38.alert_handler_lpg_stub_clk.1756626952
Short name	T10
Test name
Test status
Simulation time	173420665277 ps
CPU time	2630.59 seconds
Started	Apr 30 02:23:22 PM PDT 24
Finished	Apr 30 03:07:13 PM PDT 24
Peak memory	281580 kb
Host	smart-601c4759-44c1-45a4-9813-d12d17864990
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1756626952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.1756626952
Directory	/workspace/38.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/38.alert_handler_ping_timeout.3140888365
Short name	T662
Test name
Test status
Simulation time	9468110419 ps
CPU time	89.85 seconds
Started	Apr 30 02:23:13 PM PDT 24
Finished	Apr 30 02:24:43 PM PDT 24
Peak memory	247064 kb
Host	smart-e7ae2cba-196a-4725-b32e-f9c80d332d5e
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3140888365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.3140888365
Directory	/workspace/38.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/38.alert_handler_random_alerts.663595614
Short name	T643
Test name
Test status
Simulation time	139582933 ps
CPU time	11.15 seconds
Started	Apr 30 02:23:11 PM PDT 24
Finished	Apr 30 02:23:23 PM PDT 24
Peak memory	253944 kb
Host	smart-71119c51-f7d7-44d9-89ea-2d0ab68bf6a8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66359 5614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.663595614
Directory	/workspace/38.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/38.alert_handler_random_classes.3227758120
Short name	T102
Test name
Test status
Simulation time	2221224540 ps
CPU time	42.98 seconds
Started	Apr 30 02:23:11 PM PDT 24
Finished	Apr 30 02:23:55 PM PDT 24
Peak memory	248704 kb
Host	smart-91a6b472-a032-44f7-8607-0617b47acf85
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32277 58120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.3227758120
Directory	/workspace/38.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/38.alert_handler_sig_int_fail.598736254
Short name	T415
Test name
Test status
Simulation time	280410406 ps
CPU time	16.43 seconds
Started	Apr 30 02:23:15 PM PDT 24
Finished	Apr 30 02:23:31 PM PDT 24
Peak memory	252796 kb
Host	smart-cdd64f20-6751-4eb3-9299-5100b367cbe4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59873 6254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.598736254
Directory	/workspace/38.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/38.alert_handler_smoke.4010905242
Short name	T599
Test name
Test status
Simulation time	130893634 ps
CPU time	9.68 seconds
Started	Apr 30 02:23:12 PM PDT 24
Finished	Apr 30 02:23:22 PM PDT 24
Peak memory	253900 kb
Host	smart-8dd17bfc-5052-4305-8f1b-45f092cf027f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40109 05242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.4010905242
Directory	/workspace/38.alert_handler_smoke/latest

Test location	/workspace/coverage/default/38.alert_handler_stress_all.1947049342
Short name	T698
Test name
Test status
Simulation time	18679421058 ps
CPU time	510.03 seconds
Started	Apr 30 02:23:11 PM PDT 24
Finished	Apr 30 02:31:42 PM PDT 24
Peak memory	265168 kb
Host	smart-a5b86f10-3b49-46f8-b9a0-e2943d12979a
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947049342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha ndler_stress_all.1947049342
Directory	/workspace/38.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.2161688757
Short name	T219
Test name
Test status
Simulation time	99278120364 ps
CPU time	5872.85 seconds
Started	Apr 30 02:23:13 PM PDT 24
Finished	Apr 30 04:01:07 PM PDT 24
Peak memory	321904 kb
Host	smart-370f3618-a61c-4150-bea3-ed8674adcc29
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161688757 -assert nopostproc +UVM_TESTNAME=aler t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.2161688757
Directory	/workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/39.alert_handler_entropy.1231868592
Short name	T297
Test name
Test status
Simulation time	66858785842 ps
CPU time	1465.39 seconds
Started	Apr 30 02:23:21 PM PDT 24
Finished	Apr 30 02:47:47 PM PDT 24
Peak memory	281532 kb
Host	smart-504c42fd-8215-4950-91b7-a9fa9758239a
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1231868592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.1231868592
Directory	/workspace/39.alert_handler_entropy/latest

Test location	/workspace/coverage/default/39.alert_handler_esc_alert_accum.3040240490
Short name	T482
Test name
Test status
Simulation time	3807737273 ps
CPU time	38.66 seconds
Started	Apr 30 02:23:21 PM PDT 24
Finished	Apr 30 02:24:00 PM PDT 24
Peak memory	256036 kb
Host	smart-612ba741-0b90-4550-9ca9-40520b4b74e1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30402 40490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.3040240490
Directory	/workspace/39.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/39.alert_handler_esc_intr_timeout.1967200673
Short name	T103
Test name
Test status
Simulation time	625186003 ps
CPU time	35.42 seconds
Started	Apr 30 02:23:21 PM PDT 24
Finished	Apr 30 02:23:56 PM PDT 24
Peak memory	248696 kb
Host	smart-f7a5fbe7-b345-4fae-b487-a8d085e65555
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19672 00673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.1967200673
Directory	/workspace/39.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/39.alert_handler_lpg.1901440451
Short name	T365
Test name
Test status
Simulation time	90598364183 ps
CPU time	2538.76 seconds
Started	Apr 30 02:23:20 PM PDT 24
Finished	Apr 30 03:05:40 PM PDT 24
Peak memory	289064 kb
Host	smart-ead3c487-f283-4c3b-93dc-51a690ad711e
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1901440451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.1901440451
Directory	/workspace/39.alert_handler_lpg/latest

Test location	/workspace/coverage/default/39.alert_handler_lpg_stub_clk.1502082477
Short name	T73
Test name
Test status
Simulation time	130614699988 ps
CPU time	1783.91 seconds
Started	Apr 30 02:23:22 PM PDT 24
Finished	Apr 30 02:53:06 PM PDT 24
Peak memory	272480 kb
Host	smart-debe372a-eff2-4cf1-920d-67f5d0573b69
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1502082477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.1502082477
Directory	/workspace/39.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/39.alert_handler_ping_timeout.1987421370
Short name	T335
Test name
Test status
Simulation time	116123462982 ps
CPU time	326.57 seconds
Started	Apr 30 02:23:24 PM PDT 24
Finished	Apr 30 02:28:50 PM PDT 24
Peak memory	247956 kb
Host	smart-45cbf425-fc88-4af1-93b8-94c92b3cde9b
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1987421370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.1987421370
Directory	/workspace/39.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/39.alert_handler_random_alerts.250038017
Short name	T439
Test name
Test status
Simulation time	572440499 ps
CPU time	32.92 seconds
Started	Apr 30 02:23:13 PM PDT 24
Finished	Apr 30 02:23:46 PM PDT 24
Peak memory	248712 kb
Host	smart-6530128f-4dd1-4176-99c7-e053c8157bcd
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25003 8017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.250038017
Directory	/workspace/39.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/39.alert_handler_random_classes.1293771462
Short name	T672
Test name
Test status
Simulation time	702634350 ps
CPU time	36.91 seconds
Started	Apr 30 02:23:11 PM PDT 24
Finished	Apr 30 02:23:49 PM PDT 24
Peak memory	255340 kb
Host	smart-0ed38e9f-52d5-4d43-a5d1-638a327d8e30
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12937 71462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.1293771462
Directory	/workspace/39.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/39.alert_handler_sig_int_fail.10430441
Short name	T284
Test name
Test status
Simulation time	4218917395 ps
CPU time	68.87 seconds
Started	Apr 30 02:23:21 PM PDT 24
Finished	Apr 30 02:24:31 PM PDT 24
Peak memory	256160 kb
Host	smart-87fc3ff9-3341-4dbd-bf90-455d874e1399
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10430 441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.10430441
Directory	/workspace/39.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/39.alert_handler_smoke.893079835
Short name	T543
Test name
Test status
Simulation time	1121010496 ps
CPU time	61 seconds
Started	Apr 30 02:23:14 PM PDT 24
Finished	Apr 30 02:24:16 PM PDT 24
Peak memory	248824 kb
Host	smart-63ea4c5b-2cac-4051-aa67-f42ace3fa0e6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89307 9835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.893079835
Directory	/workspace/39.alert_handler_smoke/latest

Test location	/workspace/coverage/default/39.alert_handler_stress_all.3031520440
Short name	T612
Test name
Test status
Simulation time	330057910 ps
CPU time	34.8 seconds
Started	Apr 30 02:23:23 PM PDT 24
Finished	Apr 30 02:23:58 PM PDT 24
Peak memory	248580 kb
Host	smart-0f4ae000-892e-4a25-9db6-7eeaf47278d7
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031520440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha ndler_stress_all.3031520440
Directory	/workspace/39.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.466661594
Short name	T620
Test name
Test status
Simulation time	120199423816 ps
CPU time	1852.82 seconds
Started	Apr 30 02:23:21 PM PDT 24
Finished	Apr 30 02:54:15 PM PDT 24
Peak memory	289716 kb
Host	smart-5e66ac99-c938-4cca-968b-8585fdade2d1
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466661594 -assert nopostproc +UVM_TESTNAME=alert _handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.466661594
Directory	/workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/4.alert_handler_alert_accum_saturation.744200475
Short name	T251
Test name
Test status
Simulation time	160061418 ps
CPU time	3.67 seconds
Started	Apr 30 02:21:37 PM PDT 24
Finished	Apr 30 02:21:41 PM PDT 24
Peak memory	248904 kb
Host	smart-95d5a7b1-af90-4f50-b936-d595001f832f
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=744200475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.744200475
Directory	/workspace/4.alert_handler_alert_accum_saturation/latest

Test location	/workspace/coverage/default/4.alert_handler_entropy.537522016
Short name	T56
Test name
Test status
Simulation time	12847844798 ps
CPU time	1343.61 seconds
Started	Apr 30 02:21:36 PM PDT 24
Finished	Apr 30 02:44:01 PM PDT 24
Peak memory	288376 kb
Host	smart-647578c6-9f5c-450b-b489-2185b26c8db3
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=537522016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.537522016
Directory	/workspace/4.alert_handler_entropy/latest

Test location	/workspace/coverage/default/4.alert_handler_entropy_stress.3534070998
Short name	T458
Test name
Test status
Simulation time	643028525 ps
CPU time	9.91 seconds
Started	Apr 30 02:21:43 PM PDT 24
Finished	Apr 30 02:21:53 PM PDT 24
Peak memory	248608 kb
Host	smart-46f52889-5ae5-4de5-bc9e-9f7ecce2a10e
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3534070998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.3534070998
Directory	/workspace/4.alert_handler_entropy_stress/latest

Test location	/workspace/coverage/default/4.alert_handler_esc_alert_accum.1628419018
Short name	T306
Test name
Test status
Simulation time	26094677216 ps
CPU time	169.38 seconds
Started	Apr 30 02:21:40 PM PDT 24
Finished	Apr 30 02:24:30 PM PDT 24
Peak memory	256084 kb
Host	smart-bfc5aaef-b355-470b-98b5-69d420bccd67
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16284 19018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.1628419018
Directory	/workspace/4.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/4.alert_handler_esc_intr_timeout.3662653404
Short name	T629
Test name
Test status
Simulation time	852470955 ps
CPU time	33.21 seconds
Started	Apr 30 02:21:36 PM PDT 24
Finished	Apr 30 02:22:10 PM PDT 24
Peak memory	255904 kb
Host	smart-8c46fb22-eb98-4c47-bd19-5b8ff3c41930
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36626 53404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.3662653404
Directory	/workspace/4.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/4.alert_handler_lpg_stub_clk.2454859495
Short name	T446
Test name
Test status
Simulation time	203037121455 ps
CPU time	2574.6 seconds
Started	Apr 30 02:21:47 PM PDT 24
Finished	Apr 30 03:04:43 PM PDT 24
Peak memory	281612 kb
Host	smart-99d74d1e-fcd7-4305-a7e3-2ee805896768
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2454859495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.2454859495
Directory	/workspace/4.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/4.alert_handler_random_alerts.2075072766
Short name	T583
Test name
Test status
Simulation time	289757004 ps
CPU time	28.85 seconds
Started	Apr 30 02:21:38 PM PDT 24
Finished	Apr 30 02:22:07 PM PDT 24
Peak memory	248640 kb
Host	smart-22c10fe8-61f8-42e0-8462-8e6458606c5c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20750 72766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.2075072766
Directory	/workspace/4.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/4.alert_handler_random_classes.2324718037
Short name	T318
Test name
Test status
Simulation time	961955731 ps
CPU time	58.52 seconds
Started	Apr 30 02:21:41 PM PDT 24
Finished	Apr 30 02:22:40 PM PDT 24
Peak memory	248700 kb
Host	smart-22e57144-843a-4ea9-bcb0-60790a662134
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23247 18037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.2324718037
Directory	/workspace/4.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/4.alert_handler_smoke.2996435971
Short name	T112
Test name
Test status
Simulation time	541207963 ps
CPU time	34.3 seconds
Started	Apr 30 02:21:47 PM PDT 24
Finished	Apr 30 02:22:22 PM PDT 24
Peak memory	248652 kb
Host	smart-aafa7a6a-a345-413b-9914-52a442f0673b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29964 35971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.2996435971
Directory	/workspace/4.alert_handler_smoke/latest

Test location	/workspace/coverage/default/4.alert_handler_stress_all.2229094545
Short name	T38
Test name
Test status
Simulation time	18481166767 ps
CPU time	1909.87 seconds
Started	Apr 30 02:21:39 PM PDT 24
Finished	Apr 30 02:53:29 PM PDT 24
Peak memory	304524 kb
Host	smart-a999ab11-7739-4360-a6d5-23e3d47ae851
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229094545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han dler_stress_all.2229094545
Directory	/workspace/4.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/40.alert_handler_entropy.4197110035
Short name	T508
Test name
Test status
Simulation time	43623689938 ps
CPU time	780.89 seconds
Started	Apr 30 02:23:25 PM PDT 24
Finished	Apr 30 02:36:26 PM PDT 24
Peak memory	273224 kb
Host	smart-7ffa6f2f-ae7e-4713-973b-3568a739d936
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4197110035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.4197110035
Directory	/workspace/40.alert_handler_entropy/latest

Test location	/workspace/coverage/default/40.alert_handler_esc_alert_accum.1021125655
Short name	T625
Test name
Test status
Simulation time	5884136015 ps
CPU time	187.49 seconds
Started	Apr 30 02:23:22 PM PDT 24
Finished	Apr 30 02:26:30 PM PDT 24
Peak memory	256888 kb
Host	smart-888a90ee-cea3-49e9-b573-cb2af21573f1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10211 25655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.1021125655
Directory	/workspace/40.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/40.alert_handler_esc_intr_timeout.1073952349
Short name	T635
Test name
Test status
Simulation time	1609217212 ps
CPU time	29.67 seconds
Started	Apr 30 02:23:22 PM PDT 24
Finished	Apr 30 02:23:52 PM PDT 24
Peak memory	255380 kb
Host	smart-bcb682cb-a3ba-40ce-814e-8151681f03e1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10739 52349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.1073952349
Directory	/workspace/40.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/40.alert_handler_lpg.2222568156
Short name	T220
Test name
Test status
Simulation time	38968380232 ps
CPU time	1937.16 seconds
Started	Apr 30 02:23:26 PM PDT 24
Finished	Apr 30 02:55:43 PM PDT 24
Peak memory	272584 kb
Host	smart-0924a200-08d6-4174-9724-59ecec507724
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2222568156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.2222568156
Directory	/workspace/40.alert_handler_lpg/latest

Test location	/workspace/coverage/default/40.alert_handler_ping_timeout.3535787548
Short name	T644
Test name
Test status
Simulation time	10968850304 ps
CPU time	402.38 seconds
Started	Apr 30 02:23:24 PM PDT 24
Finished	Apr 30 02:30:06 PM PDT 24
Peak memory	248216 kb
Host	smart-a24fb6e4-f081-405f-a8e0-17eb5d4ef0ee
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3535787548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.3535787548
Directory	/workspace/40.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/40.alert_handler_random_alerts.1757430125
Short name	T532
Test name
Test status
Simulation time	3432400139 ps
CPU time	76.88 seconds
Started	Apr 30 02:23:22 PM PDT 24
Finished	Apr 30 02:24:40 PM PDT 24
Peak memory	248744 kb
Host	smart-91ef13a8-848f-410d-b34f-70ca0c06b0d6
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17574 30125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.1757430125
Directory	/workspace/40.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/40.alert_handler_random_classes.4242702672
Short name	T291
Test name
Test status
Simulation time	1137794008 ps
CPU time	61.21 seconds
Started	Apr 30 02:23:22 PM PDT 24
Finished	Apr 30 02:24:24 PM PDT 24
Peak memory	249068 kb
Host	smart-26029350-f3ce-43b5-afc3-ec6c7e09033a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42427 02672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.4242702672
Directory	/workspace/40.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/40.alert_handler_sig_int_fail.1708722161
Short name	T277
Test name
Test status
Simulation time	1652988348 ps
CPU time	60.71 seconds
Started	Apr 30 02:23:22 PM PDT 24
Finished	Apr 30 02:24:23 PM PDT 24
Peak memory	255832 kb
Host	smart-4d8d6336-7e7e-4f3a-8194-8d5430e3eee4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17087 22161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.1708722161
Directory	/workspace/40.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/40.alert_handler_smoke.851350509
Short name	T19
Test name
Test status
Simulation time	4350801066 ps
CPU time	75.47 seconds
Started	Apr 30 02:23:22 PM PDT 24
Finished	Apr 30 02:24:38 PM PDT 24
Peak memory	256444 kb
Host	smart-ad4cd957-4eff-4a41-8ed2-46a587eea04c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85135 0509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.851350509
Directory	/workspace/40.alert_handler_smoke/latest

Test location	/workspace/coverage/default/40.alert_handler_stress_all.1058349913
Short name	T44
Test name
Test status
Simulation time	10497940547 ps
CPU time	891.08 seconds
Started	Apr 30 02:23:25 PM PDT 24
Finished	Apr 30 02:38:17 PM PDT 24
Peak memory	273220 kb
Host	smart-19dccc2c-e45b-4bf3-a855-0260958303ec
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058349913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha ndler_stress_all.1058349913
Directory	/workspace/40.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/41.alert_handler_entropy.1922101257
Short name	T533
Test name
Test status
Simulation time	110804732555 ps
CPU time	1736.56 seconds
Started	Apr 30 02:23:23 PM PDT 24
Finished	Apr 30 02:52:20 PM PDT 24
Peak memory	273440 kb
Host	smart-9e81d797-15e0-458a-9f89-e268211cce37
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1922101257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.1922101257
Directory	/workspace/41.alert_handler_entropy/latest

Test location	/workspace/coverage/default/41.alert_handler_esc_alert_accum.18806522
Short name	T28
Test name
Test status
Simulation time	1903361714 ps
CPU time	147.73 seconds
Started	Apr 30 02:23:30 PM PDT 24
Finished	Apr 30 02:25:58 PM PDT 24
Peak memory	256904 kb
Host	smart-eb21809a-5864-416a-865a-529f735fd19b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18806 522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.18806522
Directory	/workspace/41.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/41.alert_handler_esc_intr_timeout.1736234981
Short name	T34
Test name
Test status
Simulation time	1548075022 ps
CPU time	27.36 seconds
Started	Apr 30 02:23:24 PM PDT 24
Finished	Apr 30 02:23:51 PM PDT 24
Peak memory	255900 kb
Host	smart-bc2eca13-fa90-48f6-847d-a9989796a4c2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17362 34981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.1736234981
Directory	/workspace/41.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/41.alert_handler_lpg.3158848522
Short name	T49
Test name
Test status
Simulation time	39138818041 ps
CPU time	711.91 seconds
Started	Apr 30 02:23:32 PM PDT 24
Finished	Apr 30 02:35:24 PM PDT 24
Peak memory	265120 kb
Host	smart-7a49c48b-134b-4a75-9410-64401d8b1ba2
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3158848522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.3158848522
Directory	/workspace/41.alert_handler_lpg/latest

Test location	/workspace/coverage/default/41.alert_handler_lpg_stub_clk.2518128504
Short name	T507
Test name
Test status
Simulation time	39952127475 ps
CPU time	880.34 seconds
Started	Apr 30 02:23:39 PM PDT 24
Finished	Apr 30 02:38:20 PM PDT 24
Peak memory	273064 kb
Host	smart-2671617a-d467-46fa-8eb6-f1a832f559d4
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2518128504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.2518128504
Directory	/workspace/41.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/41.alert_handler_ping_timeout.3039153079
Short name	T564
Test name
Test status
Simulation time	61143463650 ps
CPU time	519.19 seconds
Started	Apr 30 02:23:35 PM PDT 24
Finished	Apr 30 02:32:15 PM PDT 24
Peak memory	248032 kb
Host	smart-96394cc5-ac48-4ecd-bb39-bbbafa612a02
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3039153079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.3039153079
Directory	/workspace/41.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/41.alert_handler_random_alerts.3023282984
Short name	T617
Test name
Test status
Simulation time	229721092 ps
CPU time	7.1 seconds
Started	Apr 30 02:23:25 PM PDT 24
Finished	Apr 30 02:23:33 PM PDT 24
Peak memory	248676 kb
Host	smart-a05cbda2-7ea6-401e-b279-f43784897145
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30232 82984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.3023282984
Directory	/workspace/41.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/41.alert_handler_random_classes.403499658
Short name	T9
Test name
Test status
Simulation time	3134827987 ps
CPU time	52.43 seconds
Started	Apr 30 02:23:24 PM PDT 24
Finished	Apr 30 02:24:17 PM PDT 24
Peak memory	248772 kb
Host	smart-e9841620-8617-48ae-a04d-ce9bad094bc9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40349 9658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.403499658
Directory	/workspace/41.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/41.alert_handler_sig_int_fail.3210921063
Short name	T305
Test name
Test status
Simulation time	320725885 ps
CPU time	21.29 seconds
Started	Apr 30 02:23:26 PM PDT 24
Finished	Apr 30 02:23:47 PM PDT 24
Peak memory	255600 kb
Host	smart-3924aad7-35ee-4bc8-aca9-b127a205d2f9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32109 21063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.3210921063
Directory	/workspace/41.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/41.alert_handler_smoke.3375663755
Short name	T387
Test name
Test status
Simulation time	1448844264 ps
CPU time	7.25 seconds
Started	Apr 30 02:23:25 PM PDT 24
Finished	Apr 30 02:23:33 PM PDT 24
Peak memory	248652 kb
Host	smart-d66a008b-93fc-4cc0-818c-7a10e82dda47
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33756 63755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.3375663755
Directory	/workspace/41.alert_handler_smoke/latest

Test location	/workspace/coverage/default/41.alert_handler_stress_all.1901007897
Short name	T260
Test name
Test status
Simulation time	63515073633 ps
CPU time	2484.72 seconds
Started	Apr 30 02:23:35 PM PDT 24
Finished	Apr 30 03:05:00 PM PDT 24
Peak memory	283660 kb
Host	smart-ad0ae5c5-bd54-4d4a-b896-f91fdf0f671f
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901007897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha ndler_stress_all.1901007897
Directory	/workspace/41.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/42.alert_handler_entropy.503764243
Short name	T690
Test name
Test status
Simulation time	152252799430 ps
CPU time	1701.02 seconds
Started	Apr 30 02:23:33 PM PDT 24
Finished	Apr 30 02:51:54 PM PDT 24
Peak memory	272912 kb
Host	smart-c3465347-44a5-4f9e-9a0e-b1d809a6c8d7
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=503764243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.503764243
Directory	/workspace/42.alert_handler_entropy/latest

Test location	/workspace/coverage/default/42.alert_handler_esc_alert_accum.3272534512
Short name	T666
Test name
Test status
Simulation time	4158890423 ps
CPU time	102.32 seconds
Started	Apr 30 02:23:34 PM PDT 24
Finished	Apr 30 02:25:16 PM PDT 24
Peak memory	256744 kb
Host	smart-c3ee6cf2-9871-4626-bf0b-958aac62f6cf
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32725 34512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.3272534512
Directory	/workspace/42.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/42.alert_handler_esc_intr_timeout.3061997563
Short name	T104
Test name
Test status
Simulation time	968960391 ps
CPU time	65.43 seconds
Started	Apr 30 02:23:39 PM PDT 24
Finished	Apr 30 02:24:45 PM PDT 24
Peak memory	255308 kb
Host	smart-110d4338-c6ee-43d2-b774-5bb86d1d6d28
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30619 97563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.3061997563
Directory	/workspace/42.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/42.alert_handler_lpg.1251380810
Short name	T221
Test name
Test status
Simulation time	14780607057 ps
CPU time	1256.65 seconds
Started	Apr 30 02:23:32 PM PDT 24
Finished	Apr 30 02:44:30 PM PDT 24
Peak memory	286736 kb
Host	smart-26dc435f-d366-4e04-8f65-69110d62505c
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1251380810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.1251380810
Directory	/workspace/42.alert_handler_lpg/latest

Test location	/workspace/coverage/default/42.alert_handler_ping_timeout.1986633391
Short name	T691
Test name
Test status
Simulation time	12712633120 ps
CPU time	259.67 seconds
Started	Apr 30 02:23:36 PM PDT 24
Finished	Apr 30 02:27:56 PM PDT 24
Peak memory	248068 kb
Host	smart-8e05410d-373e-4764-9bfa-4a0fca348c6e
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1986633391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.1986633391
Directory	/workspace/42.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/42.alert_handler_random_alerts.2366721287
Short name	T390
Test name
Test status
Simulation time	70500804 ps
CPU time	4.73 seconds
Started	Apr 30 02:23:33 PM PDT 24
Finished	Apr 30 02:23:38 PM PDT 24
Peak memory	240492 kb
Host	smart-ee668ae8-c35c-4c0f-b325-ad941d03d23a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23667 21287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.2366721287
Directory	/workspace/42.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/42.alert_handler_random_classes.234658812
Short name	T653
Test name
Test status
Simulation time	1276234285 ps
CPU time	30.46 seconds
Started	Apr 30 02:23:39 PM PDT 24
Finished	Apr 30 02:24:10 PM PDT 24
Peak memory	248720 kb
Host	smart-1aa940f6-f0c9-49a8-bd9b-14e0c7b54807
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23465 8812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.234658812
Directory	/workspace/42.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/42.alert_handler_sig_int_fail.784419157
Short name	T279
Test name
Test status
Simulation time	740948334 ps
CPU time	53.47 seconds
Started	Apr 30 02:23:32 PM PDT 24
Finished	Apr 30 02:24:26 PM PDT 24
Peak memory	256020 kb
Host	smart-0f1626d9-8782-442e-8754-706435b4e751
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78441 9157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.784419157
Directory	/workspace/42.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/42.alert_handler_smoke.2507126673
Short name	T634
Test name
Test status
Simulation time	4792949196 ps
CPU time	32.17 seconds
Started	Apr 30 02:23:34 PM PDT 24
Finished	Apr 30 02:24:06 PM PDT 24
Peak memory	248748 kb
Host	smart-b8c907ed-df54-4514-86ca-da576fad7ef3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25071 26673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.2507126673
Directory	/workspace/42.alert_handler_smoke/latest

Test location	/workspace/coverage/default/42.alert_handler_stress_all.1275632169
Short name	T286
Test name
Test status
Simulation time	1162178703 ps
CPU time	41.55 seconds
Started	Apr 30 02:23:32 PM PDT 24
Finished	Apr 30 02:24:14 PM PDT 24
Peak memory	256332 kb
Host	smart-554b2b84-d81b-4591-8d0a-ef826a07f0a3
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275632169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha ndler_stress_all.1275632169
Directory	/workspace/42.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.569857139
Short name	T545
Test name
Test status
Simulation time	13708350261 ps
CPU time	1508.73 seconds
Started	Apr 30 02:23:35 PM PDT 24
Finished	Apr 30 02:48:45 PM PDT 24
Peak memory	286588 kb
Host	smart-a0ac320f-f1be-4440-bf84-9be5d49b4682
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569857139 -assert nopostproc +UVM_TESTNAME=alert _handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.569857139
Directory	/workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/43.alert_handler_entropy.4016776969
Short name	T520
Test name
Test status
Simulation time	36099216026 ps
CPU time	2071.58 seconds
Started	Apr 30 02:23:41 PM PDT 24
Finished	Apr 30 02:58:13 PM PDT 24
Peak memory	289580 kb
Host	smart-4c430f37-d396-481a-9e32-71f7904010b6
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4016776969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.4016776969
Directory	/workspace/43.alert_handler_entropy/latest

Test location	/workspace/coverage/default/43.alert_handler_esc_alert_accum.3855898640
Short name	T411
Test name
Test status
Simulation time	487833918 ps
CPU time	43.86 seconds
Started	Apr 30 02:23:39 PM PDT 24
Finished	Apr 30 02:24:23 PM PDT 24
Peak memory	256708 kb
Host	smart-2107046e-705f-400e-ae8f-90b6b2191b48
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38558 98640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.3855898640
Directory	/workspace/43.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/43.alert_handler_esc_intr_timeout.653303060
Short name	T610
Test name
Test status
Simulation time	2861696328 ps
CPU time	23.4 seconds
Started	Apr 30 02:23:39 PM PDT 24
Finished	Apr 30 02:24:03 PM PDT 24
Peak memory	248712 kb
Host	smart-1bf90b32-c55d-46ee-b903-1c76fd511db1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65330 3060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.653303060
Directory	/workspace/43.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/43.alert_handler_lpg_stub_clk.1991225435
Short name	T119
Test name
Test status
Simulation time	51173761808 ps
CPU time	1099.7 seconds
Started	Apr 30 02:23:39 PM PDT 24
Finished	Apr 30 02:41:59 PM PDT 24
Peak memory	281628 kb
Host	smart-7dd98a38-8211-49d7-afb4-84dac289cd7f
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1991225435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.1991225435
Directory	/workspace/43.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/43.alert_handler_ping_timeout.3985497512
Short name	T595
Test name
Test status
Simulation time	3793699878 ps
CPU time	137.14 seconds
Started	Apr 30 02:23:39 PM PDT 24
Finished	Apr 30 02:25:57 PM PDT 24
Peak memory	248108 kb
Host	smart-053600d4-329d-4e87-a0cc-8ca1b8fb3494
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3985497512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.3985497512
Directory	/workspace/43.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/43.alert_handler_random_alerts.3041249761
Short name	T431
Test name
Test status
Simulation time	203381537 ps
CPU time	10.52 seconds
Started	Apr 30 02:23:43 PM PDT 24
Finished	Apr 30 02:23:54 PM PDT 24
Peak memory	248660 kb
Host	smart-2742e7f6-5960-4986-9240-0642e9fd1915
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30412 49761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.3041249761
Directory	/workspace/43.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/43.alert_handler_random_classes.3609703381
Short name	T469
Test name
Test status
Simulation time	1213474093 ps
CPU time	28.73 seconds
Started	Apr 30 02:23:39 PM PDT 24
Finished	Apr 30 02:24:08 PM PDT 24
Peak memory	248708 kb
Host	smart-df6e1072-bd37-466b-b5e9-4a606016ce50
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36097 03381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.3609703381
Directory	/workspace/43.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/43.alert_handler_sig_int_fail.2718020497
Short name	T276
Test name
Test status
Simulation time	1602005772 ps
CPU time	23.49 seconds
Started	Apr 30 02:23:41 PM PDT 24
Finished	Apr 30 02:24:05 PM PDT 24
Peak memory	248636 kb
Host	smart-d7fda00a-ace3-46a7-81a3-ec8d65e1b417
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27180 20497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.2718020497
Directory	/workspace/43.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/43.alert_handler_smoke.1190882617
Short name	T111
Test name
Test status
Simulation time	3154836749 ps
CPU time	54.54 seconds
Started	Apr 30 02:23:38 PM PDT 24
Finished	Apr 30 02:24:32 PM PDT 24
Peak memory	248720 kb
Host	smart-cc30f6e1-dd9b-412c-9a6b-35d2e6bcdcbe
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11908 82617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.1190882617
Directory	/workspace/43.alert_handler_smoke/latest

Test location	/workspace/coverage/default/43.alert_handler_stress_all.1486106503
Short name	T47
Test name
Test status
Simulation time	129791837606 ps
CPU time	1882.2 seconds
Started	Apr 30 02:23:41 PM PDT 24
Finished	Apr 30 02:55:03 PM PDT 24
Peak memory	289412 kb
Host	smart-83219da9-a9e7-4113-9d36-c3c4fac66175
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486106503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha ndler_stress_all.1486106503
Directory	/workspace/43.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.4232534335
Short name	T52
Test name
Test status
Simulation time	108513602400 ps
CPU time	7341.89 seconds
Started	Apr 30 02:23:38 PM PDT 24
Finished	Apr 30 04:26:02 PM PDT 24
Peak memory	339004 kb
Host	smart-7634ad23-bfe9-40f9-bb6c-6a77b982e407
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232534335 -assert nopostproc +UVM_TESTNAME=aler t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.4232534335
Directory	/workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/44.alert_handler_entropy.3315154475
Short name	T228
Test name
Test status
Simulation time	241434844116 ps
CPU time	1673.59 seconds
Started	Apr 30 02:23:47 PM PDT 24
Finished	Apr 30 02:51:42 PM PDT 24
Peak memory	273320 kb
Host	smart-485564b4-fe0c-4f09-8dac-001dfd341945
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3315154475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.3315154475
Directory	/workspace/44.alert_handler_entropy/latest

Test location	/workspace/coverage/default/44.alert_handler_esc_alert_accum.838288521
Short name	T563
Test name
Test status
Simulation time	2890921268 ps
CPU time	171.59 seconds
Started	Apr 30 02:23:40 PM PDT 24
Finished	Apr 30 02:26:32 PM PDT 24
Peak memory	256764 kb
Host	smart-ac3a8f97-488e-4c0e-993b-30587d3517e7
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83828 8521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.838288521
Directory	/workspace/44.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/44.alert_handler_esc_intr_timeout.3145998174
Short name	T623
Test name
Test status
Simulation time	1575177275 ps
CPU time	25.81 seconds
Started	Apr 30 02:23:41 PM PDT 24
Finished	Apr 30 02:24:07 PM PDT 24
Peak memory	255500 kb
Host	smart-d109bd45-f186-4d20-93ee-9bd4168f3152
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31459 98174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.3145998174
Directory	/workspace/44.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/44.alert_handler_lpg.4228397285
Short name	T363
Test name
Test status
Simulation time	339561768315 ps
CPU time	1228.63 seconds
Started	Apr 30 02:23:47 PM PDT 24
Finished	Apr 30 02:44:16 PM PDT 24
Peak memory	289016 kb
Host	smart-0546098e-30f8-4658-a6b9-b2516be0ec7a
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4228397285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.4228397285
Directory	/workspace/44.alert_handler_lpg/latest

Test location	/workspace/coverage/default/44.alert_handler_lpg_stub_clk.3819177891
Short name	T510
Test name
Test status
Simulation time	14181119462 ps
CPU time	1283.63 seconds
Started	Apr 30 02:23:46 PM PDT 24
Finished	Apr 30 02:45:10 PM PDT 24
Peak memory	289128 kb
Host	smart-ff201948-8cf4-4a1e-9636-4c4dc8bbda01
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3819177891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.3819177891
Directory	/workspace/44.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/44.alert_handler_ping_timeout.3269509982
Short name	T351
Test name
Test status
Simulation time	10329370393 ps
CPU time	213.88 seconds
Started	Apr 30 02:23:45 PM PDT 24
Finished	Apr 30 02:27:20 PM PDT 24
Peak memory	248300 kb
Host	smart-c1f5f283-803d-499a-a4b1-51f1592b1994
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3269509982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.3269509982
Directory	/workspace/44.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/44.alert_handler_random_alerts.2192245002
Short name	T455
Test name
Test status
Simulation time	409422595 ps
CPU time	24.11 seconds
Started	Apr 30 02:23:38 PM PDT 24
Finished	Apr 30 02:24:03 PM PDT 24
Peak memory	248684 kb
Host	smart-783e6e08-a517-4650-802a-2838c67c995d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21922 45002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.2192245002
Directory	/workspace/44.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/44.alert_handler_random_classes.2290019277
Short name	T314
Test name
Test status
Simulation time	53976710 ps
CPU time	5.49 seconds
Started	Apr 30 02:23:39 PM PDT 24
Finished	Apr 30 02:23:45 PM PDT 24
Peak memory	251532 kb
Host	smart-c2c884b2-da17-4d33-b811-11152b5cab9d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22900 19277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.2290019277
Directory	/workspace/44.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/44.alert_handler_sig_int_fail.642014874
Short name	T609
Test name
Test status
Simulation time	1122896571 ps
CPU time	38.1 seconds
Started	Apr 30 02:23:46 PM PDT 24
Finished	Apr 30 02:24:24 PM PDT 24
Peak memory	255180 kb
Host	smart-06e36667-409e-4124-af32-05d70764ab45
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64201 4874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.642014874
Directory	/workspace/44.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/44.alert_handler_smoke.3187839405
Short name	T3
Test name
Test status
Simulation time	145648555 ps
CPU time	17.32 seconds
Started	Apr 30 02:23:40 PM PDT 24
Finished	Apr 30 02:23:58 PM PDT 24
Peak memory	248728 kb
Host	smart-0498adaa-6247-4329-b4a2-23a549e4584e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31878 39405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.3187839405
Directory	/workspace/44.alert_handler_smoke/latest

Test location	/workspace/coverage/default/44.alert_handler_stress_all.4188800671
Short name	T475
Test name
Test status
Simulation time	234368543 ps
CPU time	4.59 seconds
Started	Apr 30 02:23:47 PM PDT 24
Finished	Apr 30 02:23:52 PM PDT 24
Peak memory	250092 kb
Host	smart-b4148bc6-f0a0-41c9-8179-938b417da1d1
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188800671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha ndler_stress_all.4188800671
Directory	/workspace/44.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.1532590595
Short name	T275
Test name
Test status
Simulation time	38737535555 ps
CPU time	4425.9 seconds
Started	Apr 30 02:23:47 PM PDT 24
Finished	Apr 30 03:37:34 PM PDT 24
Peak memory	337756 kb
Host	smart-97a024e4-5ad3-4eb1-8e0c-d8996865b4a1
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532590595 -assert nopostproc +UVM_TESTNAME=aler t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.1532590595
Directory	/workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/45.alert_handler_entropy.2790539875
Short name	T509
Test name
Test status
Simulation time	13729786624 ps
CPU time	1239.87 seconds
Started	Apr 30 02:23:44 PM PDT 24
Finished	Apr 30 02:44:25 PM PDT 24
Peak memory	289288 kb
Host	smart-a16af795-303f-4aee-826a-1cd4dad34d61
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2790539875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.2790539875
Directory	/workspace/45.alert_handler_entropy/latest

Test location	/workspace/coverage/default/45.alert_handler_esc_alert_accum.2335070068
Short name	T539
Test name
Test status
Simulation time	10343191890 ps
CPU time	258.27 seconds
Started	Apr 30 02:23:46 PM PDT 24
Finished	Apr 30 02:28:05 PM PDT 24
Peak memory	250844 kb
Host	smart-cdc93b3f-ede0-4cf7-bb65-b3825eeaaff4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23350 70068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.2335070068
Directory	/workspace/45.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/45.alert_handler_esc_intr_timeout.4014391400
Short name	T485
Test name
Test status
Simulation time	3769741004 ps
CPU time	49.22 seconds
Started	Apr 30 02:23:45 PM PDT 24
Finished	Apr 30 02:24:35 PM PDT 24
Peak memory	248784 kb
Host	smart-fd0aea76-d3ba-40d5-9ef1-4d4051260e4b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40143 91400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.4014391400
Directory	/workspace/45.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/45.alert_handler_lpg.2437419062
Short name	T603
Test name
Test status
Simulation time	28763210352 ps
CPU time	768.09 seconds
Started	Apr 30 02:23:48 PM PDT 24
Finished	Apr 30 02:36:37 PM PDT 24
Peak memory	268212 kb
Host	smart-20f3948d-da5a-4844-b28e-ebfbff5194e8
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2437419062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.2437419062
Directory	/workspace/45.alert_handler_lpg/latest

Test location	/workspace/coverage/default/45.alert_handler_ping_timeout.3804569367
Short name	T530
Test name
Test status
Simulation time	12337403696 ps
CPU time	496.85 seconds
Started	Apr 30 02:23:48 PM PDT 24
Finished	Apr 30 02:32:05 PM PDT 24
Peak memory	248076 kb
Host	smart-55729fc1-e023-4aa9-85e1-51f5ee86d897
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3804569367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.3804569367
Directory	/workspace/45.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/45.alert_handler_random_alerts.2896074099
Short name	T389
Test name
Test status
Simulation time	313777097 ps
CPU time	27.35 seconds
Started	Apr 30 02:23:48 PM PDT 24
Finished	Apr 30 02:24:15 PM PDT 24
Peak memory	248680 kb
Host	smart-6fa616e9-c889-43bf-a8b7-ceb826aa0e41
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28960 74099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.2896074099
Directory	/workspace/45.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/45.alert_handler_random_classes.2655846570
Short name	T576
Test name
Test status
Simulation time	401986491 ps
CPU time	26.46 seconds
Started	Apr 30 02:23:47 PM PDT 24
Finished	Apr 30 02:24:13 PM PDT 24
Peak memory	256020 kb
Host	smart-1911f4e0-33be-42d8-b8ec-f2a4a08e5db9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26558 46570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.2655846570
Directory	/workspace/45.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/45.alert_handler_sig_int_fail.2987070890
Short name	T105
Test name
Test status
Simulation time	377968752 ps
CPU time	31.34 seconds
Started	Apr 30 02:23:46 PM PDT 24
Finished	Apr 30 02:24:18 PM PDT 24
Peak memory	248644 kb
Host	smart-93c7a65f-5dd1-4092-94b9-a85ecfbea5a0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29870 70890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.2987070890
Directory	/workspace/45.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/45.alert_handler_smoke.2396210001
Short name	T542
Test name
Test status
Simulation time	984422456 ps
CPU time	71.37 seconds
Started	Apr 30 02:23:45 PM PDT 24
Finished	Apr 30 02:24:56 PM PDT 24
Peak memory	248672 kb
Host	smart-8dd4896b-854a-410f-ab06-2781a8154629
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23962 10001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.2396210001
Directory	/workspace/45.alert_handler_smoke/latest

Test location	/workspace/coverage/default/45.alert_handler_stress_all.3866395967
Short name	T281
Test name
Test status
Simulation time	243398480764 ps
CPU time	2567.72 seconds
Started	Apr 30 02:23:46 PM PDT 24
Finished	Apr 30 03:06:34 PM PDT 24
Peak memory	289216 kb
Host	smart-6cc28888-e39c-4f77-b2e1-dfef39c64ad2
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866395967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha ndler_stress_all.3866395967
Directory	/workspace/45.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.1767261042
Short name	T208
Test name
Test status
Simulation time	22413139471 ps
CPU time	1242.1 seconds
Started	Apr 30 02:23:51 PM PDT 24
Finished	Apr 30 02:44:33 PM PDT 24
Peak memory	281596 kb
Host	smart-e5f2d813-a8c5-4068-83e9-c0787ccbce02
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767261042 -assert nopostproc +UVM_TESTNAME=aler t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.1767261042
Directory	/workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/46.alert_handler_entropy.2310948463
Short name	T322
Test name
Test status
Simulation time	59715994882 ps
CPU time	1902.58 seconds
Started	Apr 30 02:24:01 PM PDT 24
Finished	Apr 30 02:55:44 PM PDT 24
Peak memory	285992 kb
Host	smart-56340515-3224-42fa-9973-b1b42a214d59
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2310948463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.2310948463
Directory	/workspace/46.alert_handler_entropy/latest

Test location	/workspace/coverage/default/46.alert_handler_esc_alert_accum.1867762275
Short name	T704
Test name
Test status
Simulation time	2545364921 ps
CPU time	150.82 seconds
Started	Apr 30 02:23:53 PM PDT 24
Finished	Apr 30 02:26:24 PM PDT 24
Peak memory	249820 kb
Host	smart-aa7fada9-b8a2-4a63-a6a6-f2933f57f5d4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18677 62275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.1867762275
Directory	/workspace/46.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/46.alert_handler_esc_intr_timeout.3838492401
Short name	T648
Test name
Test status
Simulation time	893298973 ps
CPU time	58.53 seconds
Started	Apr 30 02:23:51 PM PDT 24
Finished	Apr 30 02:24:49 PM PDT 24
Peak memory	249116 kb
Host	smart-6e9c4df2-f7b8-4536-805e-177650eabdbe
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38384 92401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.3838492401
Directory	/workspace/46.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/46.alert_handler_lpg_stub_clk.2424020249
Short name	T26
Test name
Test status
Simulation time	454480419901 ps
CPU time	2291.8 seconds
Started	Apr 30 02:24:01 PM PDT 24
Finished	Apr 30 03:02:13 PM PDT 24
Peak memory	282532 kb
Host	smart-6189d962-8a84-42ac-8bfb-4faaef707c8f
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2424020249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.2424020249
Directory	/workspace/46.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/46.alert_handler_ping_timeout.3195914064
Short name	T126
Test name
Test status
Simulation time	22193205121 ps
CPU time	238.57 seconds
Started	Apr 30 02:23:59 PM PDT 24
Finished	Apr 30 02:27:58 PM PDT 24
Peak memory	248280 kb
Host	smart-e8ba6c24-4936-4e66-8e5a-3e4fc02e996f
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3195914064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.3195914064
Directory	/workspace/46.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/46.alert_handler_random_alerts.2406905590
Short name	T579
Test name
Test status
Simulation time	142246279 ps
CPU time	9.5 seconds
Started	Apr 30 02:23:52 PM PDT 24
Finished	Apr 30 02:24:01 PM PDT 24
Peak memory	248964 kb
Host	smart-d42fbcbb-6b69-4005-aacf-ba96c2627f86
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24069 05590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.2406905590
Directory	/workspace/46.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/46.alert_handler_random_classes.3486241852
Short name	T604
Test name
Test status
Simulation time	409409731 ps
CPU time	25.71 seconds
Started	Apr 30 02:23:51 PM PDT 24
Finished	Apr 30 02:24:17 PM PDT 24
Peak memory	248688 kb
Host	smart-fef5b7be-8582-441c-857c-0b65556d916b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34862 41852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.3486241852
Directory	/workspace/46.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/46.alert_handler_sig_int_fail.2240352263
Short name	T501
Test name
Test status
Simulation time	351924716 ps
CPU time	37.93 seconds
Started	Apr 30 02:24:02 PM PDT 24
Finished	Apr 30 02:24:40 PM PDT 24
Peak memory	248668 kb
Host	smart-cdf9bcae-829b-439c-a142-c88b7b234744
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22403 52263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.2240352263
Directory	/workspace/46.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/46.alert_handler_smoke.1556941148
Short name	T581
Test name
Test status
Simulation time	3643792599 ps
CPU time	17.81 seconds
Started	Apr 30 02:23:51 PM PDT 24
Finished	Apr 30 02:24:09 PM PDT 24
Peak memory	256084 kb
Host	smart-88e8a443-41a3-4a41-a496-aafba6f39470
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15569 41148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.1556941148
Directory	/workspace/46.alert_handler_smoke/latest

Test location	/workspace/coverage/default/47.alert_handler_entropy.3324998855
Short name	T553
Test name
Test status
Simulation time	328716570297 ps
CPU time	1553.36 seconds
Started	Apr 30 02:24:01 PM PDT 24
Finished	Apr 30 02:49:55 PM PDT 24
Peak memory	289384 kb
Host	smart-51c66776-e80a-417a-a767-3a4df5354596
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3324998855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.3324998855
Directory	/workspace/47.alert_handler_entropy/latest

Test location	/workspace/coverage/default/47.alert_handler_esc_alert_accum.83487507
Short name	T574
Test name
Test status
Simulation time	1560570965 ps
CPU time	133.31 seconds
Started	Apr 30 02:24:01 PM PDT 24
Finished	Apr 30 02:26:15 PM PDT 24
Peak memory	250744 kb
Host	smart-8c0d9373-4c18-4e9a-b65b-6c879c9cfced
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83487 507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.83487507
Directory	/workspace/47.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/47.alert_handler_lpg.3893272529
Short name	T708
Test name
Test status
Simulation time	161592212880 ps
CPU time	2258.21 seconds
Started	Apr 30 02:24:03 PM PDT 24
Finished	Apr 30 03:01:42 PM PDT 24
Peak memory	284160 kb
Host	smart-d8fa77c6-af68-4be9-9a67-4a046bae014b
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3893272529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.3893272529
Directory	/workspace/47.alert_handler_lpg/latest

Test location	/workspace/coverage/default/47.alert_handler_lpg_stub_clk.3679387636
Short name	T135
Test name
Test status
Simulation time	11653809111 ps
CPU time	1429.15 seconds
Started	Apr 30 02:23:59 PM PDT 24
Finished	Apr 30 02:47:49 PM PDT 24
Peak memory	289000 kb
Host	smart-1d03eacb-bcd1-4cee-bbe8-c2a46b218ffd
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3679387636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.3679387636
Directory	/workspace/47.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/47.alert_handler_ping_timeout.4001219351
Short name	T342
Test name
Test status
Simulation time	5742006825 ps
CPU time	251.69 seconds
Started	Apr 30 02:24:00 PM PDT 24
Finished	Apr 30 02:28:12 PM PDT 24
Peak memory	247032 kb
Host	smart-16e22d83-f1d8-4cfe-baa0-25b0e1991618
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4001219351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.4001219351
Directory	/workspace/47.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/47.alert_handler_random_alerts.2815112650
Short name	T312
Test name
Test status
Simulation time	884764756 ps
CPU time	24.99 seconds
Started	Apr 30 02:24:03 PM PDT 24
Finished	Apr 30 02:24:28 PM PDT 24
Peak memory	248640 kb
Host	smart-9da2eaa9-7693-4110-b424-cec754c2a412
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28151 12650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.2815112650
Directory	/workspace/47.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/47.alert_handler_random_classes.3704337954
Short name	T668
Test name
Test status
Simulation time	714202225 ps
CPU time	23.84 seconds
Started	Apr 30 02:23:59 PM PDT 24
Finished	Apr 30 02:24:24 PM PDT 24
Peak memory	248716 kb
Host	smart-eb80913c-d1b8-4998-ac63-41b5aeac114b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37043 37954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.3704337954
Directory	/workspace/47.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/47.alert_handler_sig_int_fail.1822249314
Short name	T433
Test name
Test status
Simulation time	1193944190 ps
CPU time	20.01 seconds
Started	Apr 30 02:24:00 PM PDT 24
Finished	Apr 30 02:24:21 PM PDT 24
Peak memory	249136 kb
Host	smart-63afa651-461f-4487-8a02-909db841b30e
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18222 49314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.1822249314
Directory	/workspace/47.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/47.alert_handler_smoke.1057768800
Short name	T682
Test name
Test status
Simulation time	1000873830 ps
CPU time	35.1 seconds
Started	Apr 30 02:24:00 PM PDT 24
Finished	Apr 30 02:24:35 PM PDT 24
Peak memory	248640 kb
Host	smart-86bb1359-3679-4521-b501-eeacd4def933
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10577 68800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.1057768800
Directory	/workspace/47.alert_handler_smoke/latest

Test location	/workspace/coverage/default/47.alert_handler_stress_all.3727080743
Short name	T422
Test name
Test status
Simulation time	79214319152 ps
CPU time	1733.99 seconds
Started	Apr 30 02:23:59 PM PDT 24
Finished	Apr 30 02:52:54 PM PDT 24
Peak memory	289468 kb
Host	smart-d83f5c2f-4ff3-4c84-b4b0-5012afd1ea0f
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727080743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha ndler_stress_all.3727080743
Directory	/workspace/47.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.2871277461
Short name	T287
Test name
Test status
Simulation time	53286266455 ps
CPU time	3648.84 seconds
Started	Apr 30 02:24:06 PM PDT 24
Finished	Apr 30 03:24:56 PM PDT 24
Peak memory	306108 kb
Host	smart-e3246818-eb6e-4089-ac59-01f7f0d498a1
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871277461 -assert nopostproc +UVM_TESTNAME=aler t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.2871277461
Directory	/workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/48.alert_handler_entropy.1327525746
Short name	T453
Test name
Test status
Simulation time	91737442464 ps
CPU time	1242.54 seconds
Started	Apr 30 02:24:06 PM PDT 24
Finished	Apr 30 02:44:49 PM PDT 24
Peak memory	272160 kb
Host	smart-b508deab-a42e-4cba-b0ae-568bb8b14941
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1327525746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.1327525746
Directory	/workspace/48.alert_handler_entropy/latest

Test location	/workspace/coverage/default/48.alert_handler_esc_alert_accum.4289081414
Short name	T263
Test name
Test status
Simulation time	8615860177 ps
CPU time	126.77 seconds
Started	Apr 30 02:24:07 PM PDT 24
Finished	Apr 30 02:26:14 PM PDT 24
Peak memory	256948 kb
Host	smart-4db0ee09-64d9-4e1d-b2b9-06c02d8b33d8
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42890 81414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.4289081414
Directory	/workspace/48.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/48.alert_handler_esc_intr_timeout.1635428276
Short name	T685
Test name
Test status
Simulation time	1043952766 ps
CPU time	35.55 seconds
Started	Apr 30 02:24:07 PM PDT 24
Finished	Apr 30 02:24:43 PM PDT 24
Peak memory	255856 kb
Host	smart-7a5e6d1a-b431-4876-b95f-3c5c4b5a4c40
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16354 28276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.1635428276
Directory	/workspace/48.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/48.alert_handler_lpg.759205814
Short name	T332
Test name
Test status
Simulation time	21963745813 ps
CPU time	1403.56 seconds
Started	Apr 30 02:24:07 PM PDT 24
Finished	Apr 30 02:47:31 PM PDT 24
Peak memory	266176 kb
Host	smart-9415c005-bb19-4ef0-825a-fc2f99acc559
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=759205814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.759205814
Directory	/workspace/48.alert_handler_lpg/latest

Test location	/workspace/coverage/default/48.alert_handler_lpg_stub_clk.608130336
Short name	T416
Test name
Test status
Simulation time	68575466133 ps
CPU time	2221.06 seconds
Started	Apr 30 02:24:07 PM PDT 24
Finished	Apr 30 03:01:08 PM PDT 24
Peak memory	289696 kb
Host	smart-2db8daed-cd62-4e56-a5f0-59d43ba256c7
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=608130336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.608130336
Directory	/workspace/48.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/48.alert_handler_ping_timeout.1041880505
Short name	T325
Test name
Test status
Simulation time	15077163959 ps
CPU time	317.73 seconds
Started	Apr 30 02:24:06 PM PDT 24
Finished	Apr 30 02:29:25 PM PDT 24
Peak memory	248208 kb
Host	smart-6abdb9aa-d3bd-4e69-b10e-c8f5107ea81e
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1041880505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.1041880505
Directory	/workspace/48.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/48.alert_handler_random_alerts.1913828744
Short name	T594
Test name
Test status
Simulation time	10575261485 ps
CPU time	45.27 seconds
Started	Apr 30 02:24:07 PM PDT 24
Finished	Apr 30 02:24:53 PM PDT 24
Peak memory	256136 kb
Host	smart-18e6c540-8766-4932-8fa6-b925b4875619
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19138 28744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.1913828744
Directory	/workspace/48.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/48.alert_handler_random_classes.3478220347
Short name	T441
Test name
Test status
Simulation time	689011603 ps
CPU time	41.81 seconds
Started	Apr 30 02:24:05 PM PDT 24
Finished	Apr 30 02:24:47 PM PDT 24
Peak memory	248808 kb
Host	smart-1ce15708-0729-411d-898a-67d902c3edc0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34782 20347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.3478220347
Directory	/workspace/48.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/48.alert_handler_sig_int_fail.3694956589
Short name	T529
Test name
Test status
Simulation time	180416981 ps
CPU time	23.23 seconds
Started	Apr 30 02:24:05 PM PDT 24
Finished	Apr 30 02:24:29 PM PDT 24
Peak memory	255996 kb
Host	smart-26c7b86c-1c03-4ec6-8af4-257001179a00
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36949 56589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.3694956589
Directory	/workspace/48.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/48.alert_handler_smoke.3213598402
Short name	T689
Test name
Test status
Simulation time	1158695502 ps
CPU time	17.42 seconds
Started	Apr 30 02:24:06 PM PDT 24
Finished	Apr 30 02:24:24 PM PDT 24
Peak memory	254116 kb
Host	smart-ad47f017-3a8c-4127-b105-8c6b0895e129
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32135 98402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.3213598402
Directory	/workspace/48.alert_handler_smoke/latest

Test location	/workspace/coverage/default/48.alert_handler_stress_all.2186582272
Short name	T293
Test name
Test status
Simulation time	27275835229 ps
CPU time	1526.28 seconds
Started	Apr 30 02:24:11 PM PDT 24
Finished	Apr 30 02:49:38 PM PDT 24
Peak memory	289736 kb
Host	smart-d9ca8d04-5adf-4957-aa8e-f0bf2e096080
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186582272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha ndler_stress_all.2186582272
Directory	/workspace/48.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.3138998157
Short name	T41
Test name
Test status
Simulation time	416101294834 ps
CPU time	8270.94 seconds
Started	Apr 30 02:24:13 PM PDT 24
Finished	Apr 30 04:42:05 PM PDT 24
Peak memory	395244 kb
Host	smart-07d1681c-7f40-463a-b871-afce5188b936
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138998157 -assert nopostproc +UVM_TESTNAME=aler t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.3138998157
Directory	/workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/49.alert_handler_entropy.208541773
Short name	T511
Test name
Test status
Simulation time	127691696639 ps
CPU time	2057.47 seconds
Started	Apr 30 02:24:13 PM PDT 24
Finished	Apr 30 02:58:31 PM PDT 24
Peak memory	273364 kb
Host	smart-2079687f-6ece-4276-99fc-fc5983ab72b5
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=208541773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.208541773
Directory	/workspace/49.alert_handler_entropy/latest

Test location	/workspace/coverage/default/49.alert_handler_esc_alert_accum.2550464072
Short name	T425
Test name
Test status
Simulation time	357697060 ps
CPU time	19.16 seconds
Started	Apr 30 02:24:13 PM PDT 24
Finished	Apr 30 02:24:33 PM PDT 24
Peak memory	256588 kb
Host	smart-7ab56f70-b28d-44c5-b04d-a99a8be2988d
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25504 64072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.2550464072
Directory	/workspace/49.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/49.alert_handler_esc_intr_timeout.4028831735
Short name	T106
Test name
Test status
Simulation time	694769168 ps
CPU time	44.55 seconds
Started	Apr 30 02:24:12 PM PDT 24
Finished	Apr 30 02:24:57 PM PDT 24
Peak memory	248680 kb
Host	smart-302cd3d6-d6a6-4b59-a33b-4b116c1ffd3f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40288 31735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.4028831735
Directory	/workspace/49.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/49.alert_handler_lpg.1631472145
Short name	T115
Test name
Test status
Simulation time	18635506502 ps
CPU time	1100.27 seconds
Started	Apr 30 02:24:20 PM PDT 24
Finished	Apr 30 02:42:40 PM PDT 24
Peak memory	281612 kb
Host	smart-3387ca1c-3a76-4861-a32f-0e270a0e81ce
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1631472145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.1631472145
Directory	/workspace/49.alert_handler_lpg/latest

Test location	/workspace/coverage/default/49.alert_handler_lpg_stub_clk.2935258653
Short name	T64
Test name
Test status
Simulation time	185835727052 ps
CPU time	2612.5 seconds
Started	Apr 30 02:24:18 PM PDT 24
Finished	Apr 30 03:07:51 PM PDT 24
Peak memory	289284 kb
Host	smart-51e2fc18-ae79-41b4-9dce-403e71573d54
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2935258653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.2935258653
Directory	/workspace/49.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/49.alert_handler_ping_timeout.1365951326
Short name	T495
Test name
Test status
Simulation time	6113292698 ps
CPU time	156.97 seconds
Started	Apr 30 02:24:12 PM PDT 24
Finished	Apr 30 02:26:49 PM PDT 24
Peak memory	248084 kb
Host	smart-6799b639-8265-4edc-9341-383ac4e52057
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1365951326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.1365951326
Directory	/workspace/49.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/49.alert_handler_random_alerts.1840864604
Short name	T569
Test name
Test status
Simulation time	586099051 ps
CPU time	44.29 seconds
Started	Apr 30 02:24:12 PM PDT 24
Finished	Apr 30 02:24:57 PM PDT 24
Peak memory	248664 kb
Host	smart-316f593b-c46d-42dd-ab8e-d14edb813808
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18408 64604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.1840864604
Directory	/workspace/49.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/49.alert_handler_random_classes.438920646
Short name	T386
Test name
Test status
Simulation time	3917276854 ps
CPU time	51 seconds
Started	Apr 30 02:24:14 PM PDT 24
Finished	Apr 30 02:25:06 PM PDT 24
Peak memory	249036 kb
Host	smart-8aaa5738-6f12-4d1a-a458-eb0368241db4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43892 0646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.438920646
Directory	/workspace/49.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/49.alert_handler_sig_int_fail.1381852627
Short name	T209
Test name
Test status
Simulation time	518603779 ps
CPU time	7.43 seconds
Started	Apr 30 02:24:13 PM PDT 24
Finished	Apr 30 02:24:21 PM PDT 24
Peak memory	240476 kb
Host	smart-bd9ac302-9817-4271-b4dc-d5429d39fd46
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13818 52627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.1381852627
Directory	/workspace/49.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/49.alert_handler_smoke.1165053324
Short name	T463
Test name
Test status
Simulation time	1746749853 ps
CPU time	31.44 seconds
Started	Apr 30 02:24:11 PM PDT 24
Finished	Apr 30 02:24:43 PM PDT 24
Peak memory	256340 kb
Host	smart-84a5082b-5200-4231-9329-8cc9457269e0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11650 53324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.1165053324
Directory	/workspace/49.alert_handler_smoke/latest

Test location	/workspace/coverage/default/5.alert_handler_alert_accum_saturation.2382636328
Short name	T240
Test name
Test status
Simulation time	87844308 ps
CPU time	3.58 seconds
Started	Apr 30 02:21:40 PM PDT 24
Finished	Apr 30 02:21:44 PM PDT 24
Peak memory	248888 kb
Host	smart-b5ed334d-61a9-48fe-ab10-3fda527d7a9c
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2382636328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.2382636328
Directory	/workspace/5.alert_handler_alert_accum_saturation/latest

Test location	/workspace/coverage/default/5.alert_handler_entropy.3069332241
Short name	T664
Test name
Test status
Simulation time	107217523600 ps
CPU time	1384.74 seconds
Started	Apr 30 02:21:40 PM PDT 24
Finished	Apr 30 02:44:45 PM PDT 24
Peak memory	273308 kb
Host	smart-02ee65cc-7e28-4619-91c4-dff45e74fcbf
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3069332241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.3069332241
Directory	/workspace/5.alert_handler_entropy/latest

Test location	/workspace/coverage/default/5.alert_handler_entropy_stress.90305400
Short name	T451
Test name
Test status
Simulation time	1493553269 ps
CPU time	32.04 seconds
Started	Apr 30 02:21:39 PM PDT 24
Finished	Apr 30 02:22:12 PM PDT 24
Peak memory	248720 kb
Host	smart-0026593a-c71e-4f7b-b5ea-0548e97d0007
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=90305400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.90305400
Directory	/workspace/5.alert_handler_entropy_stress/latest

Test location	/workspace/coverage/default/5.alert_handler_esc_alert_accum.3973985804
Short name	T301
Test name
Test status
Simulation time	4971595150 ps
CPU time	103.93 seconds
Started	Apr 30 02:21:36 PM PDT 24
Finished	Apr 30 02:23:21 PM PDT 24
Peak memory	256960 kb
Host	smart-09d34e85-edf2-44e2-aa1d-8f64b70fa757
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39739 85804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.3973985804
Directory	/workspace/5.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/5.alert_handler_esc_intr_timeout.2173144233
Short name	T536
Test name
Test status
Simulation time	291724732 ps
CPU time	18.51 seconds
Started	Apr 30 02:21:43 PM PDT 24
Finished	Apr 30 02:22:02 PM PDT 24
Peak memory	248756 kb
Host	smart-ebd79666-0c53-464d-8227-2773ca6b65f1
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21731 44233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.2173144233
Directory	/workspace/5.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/5.alert_handler_lpg.2156870643
Short name	T541
Test name
Test status
Simulation time	8725322809 ps
CPU time	753.45 seconds
Started	Apr 30 02:21:52 PM PDT 24
Finished	Apr 30 02:34:26 PM PDT 24
Peak memory	267276 kb
Host	smart-2ea20340-6a56-48ed-8ae5-74ac278d9aa8
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2156870643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.2156870643
Directory	/workspace/5.alert_handler_lpg/latest

Test location	/workspace/coverage/default/5.alert_handler_lpg_stub_clk.3638591636
Short name	T128
Test name
Test status
Simulation time	15307109263 ps
CPU time	1360.28 seconds
Started	Apr 30 02:21:37 PM PDT 24
Finished	Apr 30 02:44:18 PM PDT 24
Peak memory	281580 kb
Host	smart-0c4bb7b6-366c-4f84-99e4-84ece57495bc
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3638591636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.3638591636
Directory	/workspace/5.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/5.alert_handler_ping_timeout.3173133938
Short name	T71
Test name
Test status
Simulation time	9916348746 ps
CPU time	418.82 seconds
Started	Apr 30 02:21:38 PM PDT 24
Finished	Apr 30 02:28:38 PM PDT 24
Peak memory	248172 kb
Host	smart-46f93758-c836-40d5-94f1-cc2ba9ac53f3
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3173133938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.3173133938
Directory	/workspace/5.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/5.alert_handler_random_alerts.2887885646
Short name	T527
Test name
Test status
Simulation time	3081389822 ps
CPU time	50.24 seconds
Started	Apr 30 02:21:35 PM PDT 24
Finished	Apr 30 02:22:26 PM PDT 24
Peak memory	256876 kb
Host	smart-43c23d2f-abce-4216-acb9-16c986fbdceb
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28878 85646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.2887885646
Directory	/workspace/5.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/5.alert_handler_random_classes.4161612624
Short name	T659
Test name
Test status
Simulation time	1898229696 ps
CPU time	53.85 seconds
Started	Apr 30 02:21:40 PM PDT 24
Finished	Apr 30 02:22:34 PM PDT 24
Peak memory	255896 kb
Host	smart-ba466cc7-34d7-4e00-9ef7-fbc4f9a05410
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41616 12624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.4161612624
Directory	/workspace/5.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/5.alert_handler_sig_int_fail.94664097
Short name	T706
Test name
Test status
Simulation time	1456888240 ps
CPU time	31.63 seconds
Started	Apr 30 02:21:40 PM PDT 24
Finished	Apr 30 02:22:12 PM PDT 24
Peak memory	247260 kb
Host	smart-274178f7-0964-43be-ae18-41a4ed1bfc40
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94664 097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.94664097
Directory	/workspace/5.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/5.alert_handler_smoke.2201226888
Short name	T412
Test name
Test status
Simulation time	1634930595 ps
CPU time	35.1 seconds
Started	Apr 30 02:21:36 PM PDT 24
Finished	Apr 30 02:22:12 PM PDT 24
Peak memory	248708 kb
Host	smart-33cf0b22-04da-4714-b966-f600b7caf986
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22012 26888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.2201226888
Directory	/workspace/5.alert_handler_smoke/latest

Test location	/workspace/coverage/default/5.alert_handler_stress_all.2312273945
Short name	T639
Test name
Test status
Simulation time	751406408 ps
CPU time	12.02 seconds
Started	Apr 30 02:21:39 PM PDT 24
Finished	Apr 30 02:21:52 PM PDT 24
Peak memory	253904 kb
Host	smart-a9b393a1-69a5-41e8-8c21-4dd990add948
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312273945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han dler_stress_all.2312273945
Directory	/workspace/5.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.3902612784
Short name	T134
Test name
Test status
Simulation time	11017118749 ps
CPU time	1173.42 seconds
Started	Apr 30 02:21:39 PM PDT 24
Finished	Apr 30 02:41:13 PM PDT 24
Peak memory	281064 kb
Host	smart-20aa5e98-baf7-4cb2-b4f3-89bd54c37990
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902612784 -assert nopostproc +UVM_TESTNAME=aler t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.3902612784
Directory	/workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/6.alert_handler_alert_accum_saturation.305935230
Short name	T234
Test name
Test status
Simulation time	77045928 ps
CPU time	2.86 seconds
Started	Apr 30 02:21:42 PM PDT 24
Finished	Apr 30 02:21:45 PM PDT 24
Peak memory	248860 kb
Host	smart-aaa68f37-984d-433f-aacb-903c723bcabe
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=305935230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.305935230
Directory	/workspace/6.alert_handler_alert_accum_saturation/latest

Test location	/workspace/coverage/default/6.alert_handler_entropy.1110780285
Short name	T474
Test name
Test status
Simulation time	155850115093 ps
CPU time	1791.05 seconds
Started	Apr 30 02:21:40 PM PDT 24
Finished	Apr 30 02:51:32 PM PDT 24
Peak memory	273336 kb
Host	smart-c34c5b64-e411-490e-8ae9-fcc81785ff04
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1110780285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.1110780285
Directory	/workspace/6.alert_handler_entropy/latest

Test location	/workspace/coverage/default/6.alert_handler_entropy_stress.2716620545
Short name	T519
Test name
Test status
Simulation time	375213442 ps
CPU time	18.95 seconds
Started	Apr 30 02:21:41 PM PDT 24
Finished	Apr 30 02:22:01 PM PDT 24
Peak memory	248704 kb
Host	smart-2b370104-aafd-4586-9c7f-0c02bb47f974
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2716620545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.2716620545
Directory	/workspace/6.alert_handler_entropy_stress/latest

Test location	/workspace/coverage/default/6.alert_handler_esc_alert_accum.2664512524
Short name	T39
Test name
Test status
Simulation time	6372894614 ps
CPU time	328.35 seconds
Started	Apr 30 02:21:42 PM PDT 24
Finished	Apr 30 02:27:10 PM PDT 24
Peak memory	251376 kb
Host	smart-cfb7fb48-d60f-4a38-a08a-be205f89695c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26645 12524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.2664512524
Directory	/workspace/6.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/6.alert_handler_esc_intr_timeout.2314058411
Short name	T544
Test name
Test status
Simulation time	1210756728 ps
CPU time	65.87 seconds
Started	Apr 30 02:21:39 PM PDT 24
Finished	Apr 30 02:22:45 PM PDT 24
Peak memory	255900 kb
Host	smart-b3b739fd-bc7d-4fe6-8e8e-0c248cfb4675
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23140 58411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.2314058411
Directory	/workspace/6.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/6.alert_handler_lpg.3807239850
Short name	T370
Test name
Test status
Simulation time	236413688551 ps
CPU time	2866.31 seconds
Started	Apr 30 02:21:39 PM PDT 24
Finished	Apr 30 03:09:27 PM PDT 24
Peak memory	289084 kb
Host	smart-ad5d3d04-2415-4f5d-be65-f2ebfb67a451
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3807239850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.3807239850
Directory	/workspace/6.alert_handler_lpg/latest

Test location	/workspace/coverage/default/6.alert_handler_lpg_stub_clk.1268362065
Short name	T432
Test name
Test status
Simulation time	183724119322 ps
CPU time	1232.43 seconds
Started	Apr 30 02:21:41 PM PDT 24
Finished	Apr 30 02:42:14 PM PDT 24
Peak memory	272592 kb
Host	smart-27710c4e-4622-4024-b168-55c4c24c117f
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1268362065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.1268362065
Directory	/workspace/6.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/6.alert_handler_random_alerts.3719122584
Short name	T473
Test name
Test status
Simulation time	3598250583 ps
CPU time	48.35 seconds
Started	Apr 30 02:21:42 PM PDT 24
Finished	Apr 30 02:22:30 PM PDT 24
Peak memory	248800 kb
Host	smart-c6a45026-7351-4881-9014-158e36587841
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37191 22584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.3719122584
Directory	/workspace/6.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/6.alert_handler_random_classes.2401825942
Short name	T95
Test name
Test status
Simulation time	2263850170 ps
CPU time	32.89 seconds
Started	Apr 30 02:21:40 PM PDT 24
Finished	Apr 30 02:22:14 PM PDT 24
Peak memory	255324 kb
Host	smart-d87690b3-0e6c-4f82-8247-59076787cda3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24018 25942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.2401825942
Directory	/workspace/6.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/6.alert_handler_sig_int_fail.1649381621
Short name	T20
Test name
Test status
Simulation time	107413536 ps
CPU time	12.12 seconds
Started	Apr 30 02:21:39 PM PDT 24
Finished	Apr 30 02:21:52 PM PDT 24
Peak memory	255528 kb
Host	smart-268cdfa8-7461-46c9-81a3-849df87ebce0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16493 81621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.1649381621
Directory	/workspace/6.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/6.alert_handler_smoke.4018121416
Short name	T428
Test name
Test status
Simulation time	1967505723 ps
CPU time	30.25 seconds
Started	Apr 30 02:21:40 PM PDT 24
Finished	Apr 30 02:22:11 PM PDT 24
Peak memory	248656 kb
Host	smart-0b9d251c-dce1-4335-a93b-50c64e995099
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40181 21416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.4018121416
Directory	/workspace/6.alert_handler_smoke/latest

Test location	/workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.342834318
Short name	T282
Test name
Test status
Simulation time	126643347695 ps
CPU time	2477.86 seconds
Started	Apr 30 02:21:42 PM PDT 24
Finished	Apr 30 03:03:01 PM PDT 24
Peak memory	301236 kb
Host	smart-99e092a8-0342-4e91-8b89-9c66267defc4
User	root
Command	/workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342834318 -assert nopostproc +UVM_TESTNAME=alert _handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.342834318
Directory	/workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/7.alert_handler_alert_accum_saturation.3646241147
Short name	T233
Test name
Test status
Simulation time	21478207 ps
CPU time	2.66 seconds
Started	Apr 30 02:21:44 PM PDT 24
Finished	Apr 30 02:21:47 PM PDT 24
Peak memory	248916 kb
Host	smart-d0b277f1-315a-4042-b551-0630f34205fb
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3646241147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.3646241147
Directory	/workspace/7.alert_handler_alert_accum_saturation/latest

Test location	/workspace/coverage/default/7.alert_handler_entropy.3893418505
Short name	T582
Test name
Test status
Simulation time	43966543969 ps
CPU time	2603.27 seconds
Started	Apr 30 02:21:41 PM PDT 24
Finished	Apr 30 03:05:05 PM PDT 24
Peak memory	287448 kb
Host	smart-bea77bb3-669c-4074-91a2-bbb465522c02
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3893418505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.3893418505
Directory	/workspace/7.alert_handler_entropy/latest

Test location	/workspace/coverage/default/7.alert_handler_entropy_stress.1744936471
Short name	T426
Test name
Test status
Simulation time	2181813693 ps
CPU time	51.19 seconds
Started	Apr 30 02:21:38 PM PDT 24
Finished	Apr 30 02:22:30 PM PDT 24
Peak memory	248780 kb
Host	smart-2388ce96-1179-4f8f-afd1-2c0334112299
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1744936471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.1744936471
Directory	/workspace/7.alert_handler_entropy_stress/latest

Test location	/workspace/coverage/default/7.alert_handler_esc_alert_accum.208693193
Short name	T498
Test name
Test status
Simulation time	1059702916 ps
CPU time	88.57 seconds
Started	Apr 30 02:21:48 PM PDT 24
Finished	Apr 30 02:23:17 PM PDT 24
Peak memory	256840 kb
Host	smart-a2767827-b3c8-4efa-ac49-0a148b957959
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20869 3193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.208693193
Directory	/workspace/7.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/7.alert_handler_esc_intr_timeout.484686546
Short name	T129
Test name
Test status
Simulation time	1228444968 ps
CPU time	38.78 seconds
Started	Apr 30 02:21:40 PM PDT 24
Finished	Apr 30 02:22:20 PM PDT 24
Peak memory	256136 kb
Host	smart-a550a383-3dfd-47e5-8b4b-6f6f59266593
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48468 6546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.484686546
Directory	/workspace/7.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/7.alert_handler_lpg.1487610625
Short name	T366
Test name
Test status
Simulation time	18834715744 ps
CPU time	1184.82 seconds
Started	Apr 30 02:21:39 PM PDT 24
Finished	Apr 30 02:41:25 PM PDT 24
Peak memory	273232 kb
Host	smart-2c4ca68c-b9fd-4c64-aa1c-5dab99a24757
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1487610625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.1487610625
Directory	/workspace/7.alert_handler_lpg/latest

Test location	/workspace/coverage/default/7.alert_handler_lpg_stub_clk.2625741474
Short name	T675
Test name
Test status
Simulation time	80582788974 ps
CPU time	1519.79 seconds
Started	Apr 30 02:21:40 PM PDT 24
Finished	Apr 30 02:47:01 PM PDT 24
Peak memory	268352 kb
Host	smart-e6f7a365-a3ba-4b3d-af22-9ec1c8fd747c
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2625741474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.2625741474
Directory	/workspace/7.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/7.alert_handler_ping_timeout.3098482967
Short name	T338
Test name
Test status
Simulation time	121415501198 ps
CPU time	420.24 seconds
Started	Apr 30 02:21:49 PM PDT 24
Finished	Apr 30 02:28:50 PM PDT 24
Peak memory	247940 kb
Host	smart-5b9029a1-1140-420d-ad2d-1a4bdc0bf88f
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3098482967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.3098482967
Directory	/workspace/7.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/7.alert_handler_random_alerts.3346171019
Short name	T450
Test name
Test status
Simulation time	399341816 ps
CPU time	33.54 seconds
Started	Apr 30 02:21:43 PM PDT 24
Finished	Apr 30 02:22:17 PM PDT 24
Peak memory	248672 kb
Host	smart-dcde4bf7-2e7d-4d32-8d33-84a6cf0ef261
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33461 71019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.3346171019
Directory	/workspace/7.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/7.alert_handler_random_classes.663194130
Short name	T571
Test name
Test status
Simulation time	63316740 ps
CPU time	9.21 seconds
Started	Apr 30 02:21:48 PM PDT 24
Finished	Apr 30 02:21:58 PM PDT 24
Peak memory	248672 kb
Host	smart-f0b49787-5edf-4e1c-9324-a9e763a6c3b3
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66319 4130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.663194130
Directory	/workspace/7.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/7.alert_handler_sig_int_fail.3374251920
Short name	T206
Test name
Test status
Simulation time	478176378 ps
CPU time	4.79 seconds
Started	Apr 30 02:21:48 PM PDT 24
Finished	Apr 30 02:21:54 PM PDT 24
Peak memory	238992 kb
Host	smart-cc052170-83b5-4825-bc86-6f7b16bed11c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33742 51920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.3374251920
Directory	/workspace/7.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/7.alert_handler_smoke.2685661957
Short name	T424
Test name
Test status
Simulation time	536058267 ps
CPU time	32.78 seconds
Started	Apr 30 02:21:39 PM PDT 24
Finished	Apr 30 02:22:13 PM PDT 24
Peak memory	248676 kb
Host	smart-ecc01706-f670-40cf-8321-3eee15588ec9
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26856 61957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.2685661957
Directory	/workspace/7.alert_handler_smoke/latest

Test location	/workspace/coverage/default/7.alert_handler_stress_all.728088591
Short name	T295
Test name
Test status
Simulation time	16268180510 ps
CPU time	459.71 seconds
Started	Apr 30 02:21:44 PM PDT 24
Finished	Apr 30 02:29:25 PM PDT 24
Peak memory	256968 kb
Host	smart-5adc7a14-90e4-4ccc-aeba-aae9fb94d110
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728088591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_hand ler_stress_all.728088591
Directory	/workspace/7.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/8.alert_handler_alert_accum_saturation.4141275810
Short name	T239
Test name
Test status
Simulation time	30483665 ps
CPU time	2.91 seconds
Started	Apr 30 02:21:48 PM PDT 24
Finished	Apr 30 02:21:52 PM PDT 24
Peak memory	248868 kb
Host	smart-6000acbf-e63d-4240-b95d-0030a8bacc88
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=4141275810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.4141275810
Directory	/workspace/8.alert_handler_alert_accum_saturation/latest

Test location	/workspace/coverage/default/8.alert_handler_entropy.4258176435
Short name	T559
Test name
Test status
Simulation time	27228750248 ps
CPU time	826.83 seconds
Started	Apr 30 02:21:47 PM PDT 24
Finished	Apr 30 02:35:34 PM PDT 24
Peak memory	266144 kb
Host	smart-edad3a12-6344-4836-ab16-f1eac657e4ad
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4258176435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.4258176435
Directory	/workspace/8.alert_handler_entropy/latest

Test location	/workspace/coverage/default/8.alert_handler_entropy_stress.48198732
Short name	T405
Test name
Test status
Simulation time	169287189 ps
CPU time	9.9 seconds
Started	Apr 30 02:21:54 PM PDT 24
Finished	Apr 30 02:22:05 PM PDT 24
Peak memory	240424 kb
Host	smart-4c68b17b-91f5-4580-b40d-67849313d70e
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=48198732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.48198732
Directory	/workspace/8.alert_handler_entropy_stress/latest

Test location	/workspace/coverage/default/8.alert_handler_esc_alert_accum.1375378105
Short name	T393
Test name
Test status
Simulation time	60966497856 ps
CPU time	274.25 seconds
Started	Apr 30 02:21:39 PM PDT 24
Finished	Apr 30 02:26:14 PM PDT 24
Peak memory	256820 kb
Host	smart-42c95648-c384-4673-98d2-ac3ac2c2a6e2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13753 78105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.1375378105
Directory	/workspace/8.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/8.alert_handler_esc_intr_timeout.1559898246
Short name	T457
Test name
Test status
Simulation time	812657100 ps
CPU time	19.75 seconds
Started	Apr 30 02:21:43 PM PDT 24
Finished	Apr 30 02:22:03 PM PDT 24
Peak memory	255776 kb
Host	smart-8eb95318-e3e4-4a98-80c2-380a3144d71f
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15598 98246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.1559898246
Directory	/workspace/8.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/8.alert_handler_lpg.4172216809
Short name	T614
Test name
Test status
Simulation time	28674021777 ps
CPU time	1716.78 seconds
Started	Apr 30 02:21:46 PM PDT 24
Finished	Apr 30 02:50:24 PM PDT 24
Peak memory	282124 kb
Host	smart-b52e7374-8fe9-44c4-87ab-89730a402c87
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4172216809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.4172216809
Directory	/workspace/8.alert_handler_lpg/latest

Test location	/workspace/coverage/default/8.alert_handler_lpg_stub_clk.401718509
Short name	T627
Test name
Test status
Simulation time	20464578590 ps
CPU time	1051.9 seconds
Started	Apr 30 02:21:48 PM PDT 24
Finished	Apr 30 02:39:20 PM PDT 24
Peak memory	272256 kb
Host	smart-a48f3b2b-7ab0-45db-a0a4-d4b2ba066ea5
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=401718509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.401718509
Directory	/workspace/8.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/8.alert_handler_ping_timeout.4027853134
Short name	T344
Test name
Test status
Simulation time	15032514198 ps
CPU time	312.28 seconds
Started	Apr 30 02:21:52 PM PDT 24
Finished	Apr 30 02:27:05 PM PDT 24
Peak memory	248236 kb
Host	smart-f1792e36-f360-4970-bf09-40fc72565791
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4027853134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.4027853134
Directory	/workspace/8.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/8.alert_handler_random_alerts.108007288
Short name	T486
Test name
Test status
Simulation time	1235267811 ps
CPU time	23.29 seconds
Started	Apr 30 02:21:43 PM PDT 24
Finished	Apr 30 02:22:06 PM PDT 24
Peak memory	255912 kb
Host	smart-f8c1584c-ed57-48ca-8be9-0f98706be966
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10800 7288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.108007288
Directory	/workspace/8.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/8.alert_handler_random_classes.2615341845
Short name	T120
Test name
Test status
Simulation time	1470502352 ps
CPU time	36.07 seconds
Started	Apr 30 02:21:43 PM PDT 24
Finished	Apr 30 02:22:19 PM PDT 24
Peak memory	249136 kb
Host	smart-6ecf017e-cc36-460f-8852-24f83809a9f0
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26153 41845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.2615341845
Directory	/workspace/8.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/8.alert_handler_sig_int_fail.3460863364
Short name	T268
Test name
Test status
Simulation time	976721151 ps
CPU time	57 seconds
Started	Apr 30 02:21:44 PM PDT 24
Finished	Apr 30 02:22:41 PM PDT 24
Peak memory	255480 kb
Host	smart-9c58c0e5-d2c6-46c0-a609-c0e7f7d869fa
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34608 63364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.3460863364
Directory	/workspace/8.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/8.alert_handler_smoke.2298778013
Short name	T512
Test name
Test status
Simulation time	11223977839 ps
CPU time	62.83 seconds
Started	Apr 30 02:21:42 PM PDT 24
Finished	Apr 30 02:22:45 PM PDT 24
Peak memory	256124 kb
Host	smart-667dfcae-3410-4443-8f7f-4f05fbd2701b
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22987 78013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.2298778013
Directory	/workspace/8.alert_handler_smoke/latest

Test location	/workspace/coverage/default/8.alert_handler_stress_all.477595978
Short name	T696
Test name
Test status
Simulation time	49321007785 ps
CPU time	1305.88 seconds
Started	Apr 30 02:21:50 PM PDT 24
Finished	Apr 30 02:43:36 PM PDT 24
Peak memory	289132 kb
Host	smart-40d7fe46-02f0-4bdd-bcfa-5047eef83490
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477595978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_hand ler_stress_all.477595978
Directory	/workspace/8.alert_handler_stress_all/latest

Test location	/workspace/coverage/default/9.alert_handler_alert_accum_saturation.947546138
Short name	T249
Test name
Test status
Simulation time	90107563 ps
CPU time	3.72 seconds
Started	Apr 30 02:21:52 PM PDT 24
Finished	Apr 30 02:21:56 PM PDT 24
Peak memory	248868 kb
Host	smart-08725920-ebee-437a-a304-d64f37b894f9
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=947546138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.947546138
Directory	/workspace/9.alert_handler_alert_accum_saturation/latest

Test location	/workspace/coverage/default/9.alert_handler_entropy.486328319
Short name	T461
Test name
Test status
Simulation time	33647102977 ps
CPU time	1046.81 seconds
Started	Apr 30 02:21:50 PM PDT 24
Finished	Apr 30 02:39:17 PM PDT 24
Peak memory	285480 kb
Host	smart-06d1e407-bb05-4188-b6a2-46ea99bbdcc1
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=486328319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.486328319
Directory	/workspace/9.alert_handler_entropy/latest

Test location	/workspace/coverage/default/9.alert_handler_entropy_stress.182691454
Short name	T400
Test name
Test status
Simulation time	315414655 ps
CPU time	10.45 seconds
Started	Apr 30 02:21:48 PM PDT 24
Finished	Apr 30 02:22:00 PM PDT 24
Peak memory	248664 kb
Host	smart-3c1a2a87-266d-4c8d-8a15-f5410aaf696d
User	root
Command	/workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=182691454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.182691454
Directory	/workspace/9.alert_handler_entropy_stress/latest

Test location	/workspace/coverage/default/9.alert_handler_esc_alert_accum.939479822
Short name	T418
Test name
Test status
Simulation time	8450993599 ps
CPU time	153.32 seconds
Started	Apr 30 02:21:48 PM PDT 24
Finished	Apr 30 02:24:21 PM PDT 24
Peak memory	256648 kb
Host	smart-f0172a1f-55f0-4177-bcd0-f4ccda06039c
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93947 9822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.939479822
Directory	/workspace/9.alert_handler_esc_alert_accum/latest

Test location	/workspace/coverage/default/9.alert_handler_esc_intr_timeout.1587694998
Short name	T78
Test name
Test status
Simulation time	2932074488 ps
CPU time	41.21 seconds
Started	Apr 30 02:21:49 PM PDT 24
Finished	Apr 30 02:22:31 PM PDT 24
Peak memory	248836 kb
Host	smart-3d23134b-ace0-42ee-b5b8-1c65d0cb1305
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15876 94998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.1587694998
Directory	/workspace/9.alert_handler_esc_intr_timeout/latest

Test location	/workspace/coverage/default/9.alert_handler_lpg.2795732216
Short name	T113
Test name
Test status
Simulation time	27491835834 ps
CPU time	1435.58 seconds
Started	Apr 30 02:21:49 PM PDT 24
Finished	Apr 30 02:45:45 PM PDT 24
Peak memory	273068 kb
Host	smart-0ca95745-e8d5-4a2e-88cc-42ea8e8b3925
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2795732216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.2795732216
Directory	/workspace/9.alert_handler_lpg/latest

Test location	/workspace/coverage/default/9.alert_handler_lpg_stub_clk.50714512
Short name	T521
Test name
Test status
Simulation time	17543892107 ps
CPU time	1461.12 seconds
Started	Apr 30 02:21:50 PM PDT 24
Finished	Apr 30 02:46:11 PM PDT 24
Peak memory	281576 kb
Host	smart-528277c9-ea2d-429b-9a55-78d04876f82f
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=50714512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.50714512
Directory	/workspace/9.alert_handler_lpg_stub_clk/latest

Test location	/workspace/coverage/default/9.alert_handler_ping_timeout.2632607264
Short name	T326
Test name
Test status
Simulation time	34221337496 ps
CPU time	356.53 seconds
Started	Apr 30 02:21:48 PM PDT 24
Finished	Apr 30 02:27:46 PM PDT 24
Peak memory	246952 kb
Host	smart-4b3e49ec-e7e2-4d0b-ab98-cbb548b1aa7b
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2632607264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.2632607264
Directory	/workspace/9.alert_handler_ping_timeout/latest

Test location	/workspace/coverage/default/9.alert_handler_random_alerts.1758054574
Short name	T684
Test name
Test status
Simulation time	283134341 ps
CPU time	15.75 seconds
Started	Apr 30 02:21:46 PM PDT 24
Finished	Apr 30 02:22:02 PM PDT 24
Peak memory	256868 kb
Host	smart-0e53b262-c83f-4081-8fb7-0026b2c12ed4
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17580 54574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.1758054574
Directory	/workspace/9.alert_handler_random_alerts/latest

Test location	/workspace/coverage/default/9.alert_handler_random_classes.1968940846
Short name	T133
Test name
Test status
Simulation time	286785775 ps
CPU time	10.99 seconds
Started	Apr 30 02:21:47 PM PDT 24
Finished	Apr 30 02:21:59 PM PDT 24
Peak memory	249188 kb
Host	smart-f179d062-39e0-4d79-abad-cb28b6ec76b2
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19689 40846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.1968940846
Directory	/workspace/9.alert_handler_random_classes/latest

Test location	/workspace/coverage/default/9.alert_handler_sig_int_fail.4009180883
Short name	T598
Test name
Test status
Simulation time	382112441 ps
CPU time	13.34 seconds
Started	Apr 30 02:21:48 PM PDT 24
Finished	Apr 30 02:22:02 PM PDT 24
Peak memory	248580 kb
Host	smart-f1284bf0-ee4f-4773-8ea8-4af1a4fdae0a
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40091 80883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.4009180883
Directory	/workspace/9.alert_handler_sig_int_fail/latest

Test location	/workspace/coverage/default/9.alert_handler_smoke.3726293747
Short name	T591
Test name
Test status
Simulation time	699158824 ps
CPU time	37.43 seconds
Started	Apr 30 02:21:46 PM PDT 24
Finished	Apr 30 02:22:24 PM PDT 24
Peak memory	248768 kb
Host	smart-05201fc0-1954-47d5-a3f9-0ecfa7a23533
User	root
Command	/workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37262 93747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.3726293747
Directory	/workspace/9.alert_handler_smoke/latest

Test location	/workspace/coverage/default/9.alert_handler_stress_all.1424906687
Short name	T618
Test name
Test status
Simulation time	44050556417 ps
CPU time	1218.35 seconds
Started	Apr 30 02:21:48 PM PDT 24
Finished	Apr 30 02:42:07 PM PDT 24
Peak memory	289152 kb
Host	smart-e84f9f62-f78e-4cba-b56a-fba226ae6cb3
User	root
Command	/workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424906687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han dler_stress_all.1424906687
Directory	/workspace/9.alert_handler_stress_all/latest