Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 66284739 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 32232931 1 T1 2513 T2 1276 T3 2043



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 15140659 1 T1 1406 T2 522 T3 2370
values[0x0] 40589831 1 T1 3050 T2 1753 T3 1477
values[0x1] 42787180 1 T1 3040 T2 1699 T3 1478



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 56515476 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 42002194 1 T1 3158 T2 1617 T3 2512



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 315169 1 T3 18 T10 24 T8 1556
valid_sources[0x01] 310841 1 T1 57 T3 17 T10 41
valid_sources[0x02] 315322 1 T3 26 T10 14 T8 1634
valid_sources[0x03] 313970 1 T3 21 T10 26 T8 1314
valid_sources[0x04] 298599 1 T3 9 T10 18 T8 1467
valid_sources[0x05] 524556 1 T3 24 T10 18 T8 1519
valid_sources[0x06] 301559 1 T3 22 T10 48 T8 2083
valid_sources[0x07] 320774 1 T1 114 T3 17 T10 14
valid_sources[0x08] 299189 1 T3 16 T10 46 T8 1808
valid_sources[0x09] 307587 1 T3 23 T10 19 T8 1816
valid_sources[0x0a] 317061 1 T3 24 T10 40 T8 2006
valid_sources[0x0b] 310097 1 T3 20 T10 17 T8 1672
valid_sources[0x0c] 304726 1 T3 16 T10 6 T8 1649
valid_sources[0x0d] 314849 1 T1 23 T3 26 T10 30
valid_sources[0x0e] 683322 1 T3 14 T10 42 T8 1519
valid_sources[0x0f] 316172 1 T3 24 T10 37 T8 1597
valid_sources[0x10] 318024 1 T1 169 T3 16 T10 29
valid_sources[0x11] 303535 1 T1 68 T3 21 T10 20
valid_sources[0x12] 298716 1 T1 100 T3 24 T10 40
valid_sources[0x13] 306829 1 T3 22 T10 47 T8 1474
valid_sources[0x14] 335998 1 T1 106 T3 24 T10 22
valid_sources[0x15] 314801 1 T1 354 T3 17 T10 30
valid_sources[0x16] 316389 1 T1 71 T3 16 T10 24
valid_sources[0x17] 320325 1 T1 133 T3 21 T10 18
valid_sources[0x18] 316435 1 T1 58 T3 20 T10 20
valid_sources[0x19] 601316 1 T1 12 T3 22 T10 29
valid_sources[0x1a] 309825 1 T3 16 T10 35 T8 1653
valid_sources[0x1b] 315859 1 T1 42 T3 14 T10 21
valid_sources[0x1c] 298914 1 T3 29 T10 48 T8 1558
valid_sources[0x1d] 305878 1 T3 23 T10 35 T8 1840
valid_sources[0x1e] 309188 1 T3 21 T10 48 T8 1750
valid_sources[0x1f] 309066 1 T1 35 T3 11 T10 15
valid_sources[0x20] 311171 1 T1 88 T3 25 T10 16
valid_sources[0x21] 316849 1 T1 15 T3 20 T10 43
valid_sources[0x22] 848110 1 T3 22 T10 33 T8 1952
valid_sources[0x23] 315410 1 T1 3 T3 15 T10 42
valid_sources[0x24] 301227 1 T1 41 T3 17 T10 15
valid_sources[0x25] 316905 1 T3 30 T10 11 T8 1608
valid_sources[0x26] 317700 1 T3 15 T10 38 T8 1411
valid_sources[0x27] 336318 1 T3 15 T10 20 T8 1493
valid_sources[0x28] 790183 1 T1 33 T3 21 T10 32
valid_sources[0x29] 310135 1 T1 117 T3 22 T10 36
valid_sources[0x2a] 302140 1 T3 23 T10 53 T8 1536
valid_sources[0x2b] 532968 1 T1 24 T3 15 T10 21
valid_sources[0x2c] 307097 1 T3 18 T10 66 T8 1280
valid_sources[0x2d] 309740 1 T3 24 T10 39 T8 1744
valid_sources[0x2e] 304712 1 T3 21 T10 34 T8 1832
valid_sources[0x2f] 318951 1 T1 174 T3 16 T10 46
valid_sources[0x30] 299564 1 T1 118 T3 22 T10 48
valid_sources[0x31] 623134 1 T3 11 T10 52 T8 1539
valid_sources[0x32] 299280 1 T1 26 T3 23 T10 36
valid_sources[0x33] 307437 1 T3 20 T10 28 T8 1464
valid_sources[0x34] 305232 1 T3 18 T10 34 T8 1691
valid_sources[0x35] 319536 1 T1 98 T3 23 T10 25
valid_sources[0x36] 308348 1 T3 25 T10 23 T8 1623
valid_sources[0x37] 310885 1 T1 6 T3 23 T10 28
valid_sources[0x38] 306880 1 T1 18 T3 18 T10 11
valid_sources[0x39] 305842 1 T1 62 T3 21 T10 21
valid_sources[0x3a] 302184 1 T3 22 T10 46 T8 1627
valid_sources[0x3b] 303767 1 T3 14 T10 32 T8 1741
valid_sources[0x3c] 551508 1 T1 178 T3 24 T10 20
valid_sources[0x3d] 300879 1 T1 75 T3 24 T10 14
valid_sources[0x3e] 660086 1 T3 12 T10 51 T8 1642
valid_sources[0x3f] 617207 1 T1 61 T3 20 T10 17
valid_sources[0x40] 632138 1 T1 275 T3 18 T10 15
valid_sources[0x41] 304945 1 T1 19 T3 23 T10 43
valid_sources[0x42] 315981 1 T3 20 T10 51 T8 1711
valid_sources[0x43] 664869 1 T3 30 T10 33 T8 1493
valid_sources[0x44] 305112 1 T3 25 T10 42 T8 1790
valid_sources[0x45] 308758 1 T3 26 T10 22 T8 1488
valid_sources[0x46] 310657 1 T3 29 T10 6 T8 1981
valid_sources[0x47] 311201 1 T1 64 T3 17 T10 25
valid_sources[0x48] 350833 1 T3 26 T10 10 T8 1748
valid_sources[0x49] 307999 1 T1 34 T3 17 T10 33
valid_sources[0x4a] 374102 1 T1 180 T3 25 T10 8
valid_sources[0x4b] 315554 1 T3 16 T10 28 T8 1786
valid_sources[0x4c] 603454 1 T3 20 T10 43 T8 1467
valid_sources[0x4d] 310410 1 T1 94 T3 32 T10 25
valid_sources[0x4e] 327829 1 T1 66 T3 22 T10 43
valid_sources[0x4f] 305001 1 T1 23 T3 10 T10 12
valid_sources[0x50] 309638 1 T3 16 T10 67 T8 1662
valid_sources[0x51] 303727 1 T3 23 T10 56 T8 1378
valid_sources[0x52] 771516 1 T3 26 T10 33 T8 1423
valid_sources[0x53] 302580 1 T3 23 T10 24 T8 1594
valid_sources[0x54] 341979 1 T3 24 T10 16 T8 1728
valid_sources[0x55] 300662 1 T3 23 T10 50 T8 1759
valid_sources[0x56] 949916 1 T1 29 T3 21 T10 41
valid_sources[0x57] 607410 1 T3 16 T10 74 T8 1558
valid_sources[0x58] 307964 1 T3 33 T10 53 T8 1475
valid_sources[0x59] 305040 1 T3 17 T10 30 T8 1860
valid_sources[0x5a] 310385 1 T3 28 T10 61 T8 1664
valid_sources[0x5b] 307735 1 T3 17 T10 35 T8 1589
valid_sources[0x5c] 319853 1 T1 17 T3 32 T10 53
valid_sources[0x5d] 312001 1 T3 23 T10 30 T8 1717
valid_sources[0x5e] 510552 1 T3 20 T10 33 T8 1429
valid_sources[0x5f] 307841 1 T3 15 T10 59 T8 1919
valid_sources[0x60] 718710 1 T1 213 T3 30 T10 29
valid_sources[0x61] 312998 1 T3 20 T10 30 T8 1884
valid_sources[0x62] 318811 1 T3 18 T10 62 T8 1789
valid_sources[0x63] 306710 1 T1 2 T3 22 T10 46
valid_sources[0x64] 311931 1 T1 15 T3 20 T10 50
valid_sources[0x65] 313458 1 T3 28 T10 45 T8 1299
valid_sources[0x66] 302170 1 T1 18 T3 18 T10 26
valid_sources[0x67] 693605 1 T3 34 T10 19 T8 1620
valid_sources[0x68] 306543 1 T1 52 T3 24 T10 18
valid_sources[0x69] 300256 1 T3 25 T10 40 T8 1587
valid_sources[0x6a] 319078 1 T1 21 T3 20 T10 47
valid_sources[0x6b] 317283 1 T1 60 T3 22 T10 40
valid_sources[0x6c] 304310 1 T1 5 T3 18 T10 57
valid_sources[0x6d] 309545 1 T3 20 T10 18 T8 1567
valid_sources[0x6e] 310777 1 T1 44 T3 13 T10 33
valid_sources[0x6f] 304604 1 T3 21 T10 30 T8 1506
valid_sources[0x70] 308469 1 T1 69 T3 18 T10 11
valid_sources[0x71] 587966 1 T1 12 T3 27 T10 10
valid_sources[0x72] 307720 1 T1 87 T3 19 T10 55
valid_sources[0x73] 306741 1 T1 38 T3 14 T10 37
valid_sources[0x74] 318521 1 T3 22 T10 43 T8 1492
valid_sources[0x75] 314506 1 T1 143 T3 17 T10 11
valid_sources[0x76] 303912 1 T3 26 T10 39 T8 1724
valid_sources[0x77] 305387 1 T3 9 T10 30 T8 1596
valid_sources[0x78] 786646 1 T3 12 T10 50 T8 1824
valid_sources[0x79] 305260 1 T3 27 T10 27 T8 1554
valid_sources[0x7a] 311137 1 T3 24 T10 44 T8 1768
valid_sources[0x7b] 311033 1 T3 20 T10 32 T8 1454
valid_sources[0x7c] 720747 1 T3 16 T10 46 T8 1704
valid_sources[0x7d] 307656 1 T1 31 T3 30 T10 32
valid_sources[0x7e] 316435 1 T3 21 T10 17 T8 1935
valid_sources[0x7f] 299134 1 T1 22 T3 14 T10 46
valid_sources[0x80] 316265 1 T3 26 T10 25 T8 1380



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 7521441 1 T1 713 T2 254 T3 1183
values[0x0] all_enables biggest_size 15576310 1 T1 1156 T2 650 T3 550
values[0x1] all_enables biggest_size 9135180 1 T1 644 T2 372 T3 310

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%