Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.62	100.00	100.00	86.49			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
81.38	100.00		97.26			46.88	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	86.49			86.49

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.62	100.00	100.00	86.49			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
81.38	100.00		97.26			46.88	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	86.49			86.49

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.30	100.00	100.00	89.19			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
81.38	100.00		97.26			46.88	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	89.19			89.19

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.95	100.00	100.00	83.78			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
81.38	100.00		97.26			46.88	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	83.78			83.78

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T215,T216,T217
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T7,T8

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	12937	0	0
DisabledNoTrigBkwd_A	2147483647	901622	0	0
DisabledNoTrigFwd_A	2147483647	1572899059	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	12937	0	0
T53	357692	0	0	0
T70	128053	0	0	0
T90	232231	0	0	0
T119	227391	0	0	0
T215	0	640	0	0
T216	0	681	0	0
T217	3961	579	0	0
T218	1570	741	0	0
T219	0	417	0	0
T220	0	398	0	0
T221	0	1166	0	0
T222	0	772	0	0
T223	0	764	0	0
T224	0	733	0	0
T225	0	1048	0	0
T226	3821	773	0	0
T227	0	163	0	0
T228	0	260	0	0
T229	0	301	0	0
T230	0	465	0	0
T231	0	1126	0	0
T232	0	538	0	0
T233	0	539	0	0
T234	0	833	0	0
T235	21908	0	0	0
T236	11486	0	0	0
T237	237920	0	0	0
T238	14659	0	0	0
T239	19830	0	0	0
T240	14254	0	0	0
T241	113252	0	0	0
T242	370618	0	0	0
T243	107927	0	0	0
T244	84427	0	0	0
T245	832901	0	0	0
T246	60004	0	0	0
T247	27524	0	0	0
T248	715446	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	901622	0	0
T3	40308	16	0	0
T4	437388	3002	0	0
T5	0	358	0	0
T6	0	41	0	0
T7	2069720	1246	0	0
T8	1790580	3179	0	0
T9	1855416	357	0	0
T10	307452	0	0	0
T16	181144	101	0	0
T17	229156	62	0	0
T18	0	249	0	0
T19	1301312	4127	0	0
T24	74480	0	0	0
T34	0	1	0	0
T35	0	221	0	0
T40	0	65	0	0
T44	16935	0	0	0
T45	0	231	0	0
T48	0	8	0	0
T52	0	2542	0	0
T58	0	2217	0	0
T72	0	634	0	0
T76	0	24	0	0
T77	0	144	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1572899059	0	0
T1	268992	137046	0	0
T2	174696	132725	0	0
T3	53744	22309	0	0
T4	437388	1457267	0	0
T7	2069720	567640	0	0
T8	1790580	961254	0	0
T9	1855416	1404417	0	0
T10	307452	216600	0	0
T16	181144	136245	0	0
T19	1301312	697544	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T10
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T217,T219,T220
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T8,T16

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	713624352	5634	0	0
DisabledNoTrigBkwd_A	713624352	264652	0	0
DisabledNoTrigFwd_A	713624352	335417214	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	5634	0	0
T53	357692	0	0	0
T70	128053	0	0	0
T217	3961	579	0	0
T219	0	417	0	0
T220	0	398	0	0
T222	0	772	0	0
T224	0	733	0	0
T225	0	1048	0	0
T228	0	260	0	0
T229	0	301	0	0
T231	0	1126	0	0
T235	21908	0	0	0
T236	11486	0	0	0
T237	237920	0	0	0
T238	14659	0	0	0
T239	19830	0	0	0
T240	14254	0	0	0
T241	113252	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	264652	0	0
T4	109347	1098	0	0
T7	517430	1	0	0
T8	447645	1330	0	0
T9	463854	357	0	0
T10	76863	0	0	0
T16	45286	101	0	0
T17	57289	62	0	0
T18	0	75	0	0
T19	325328	3	0	0
T24	18620	0	0	0
T44	16935	0	0	0
T48	0	8	0	0
T76	0	24	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	335417214	0	0
T1	67248	1980	0	0
T2	43674	1961	0	0
T3	13436	5089	0	0
T4	109347	141238	0	0
T7	517430	515067	0	0
T8	447645	18214	0	0
T9	463854	16999	0	0
T10	76863	73249	0	0
T16	45286	582	0	0
T19	325328	324088	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T10
1	1	Covered	T1,T3,T7

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T226,T227
1	1	Covered	T1,T3,T7

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T7,T8

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	713624352	936	0	0
DisabledNoTrigBkwd_A	713624352	221741	0	0
DisabledNoTrigFwd_A	713624352	413977104	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	936	0	0
T90	232231	0	0	0
T119	227391	0	0	0
T226	3821	773	0	0
T227	0	163	0	0
T242	370618	0	0	0
T243	107927	0	0	0
T244	84427	0	0	0
T245	832901	0	0	0
T246	60004	0	0	0
T247	27524	0	0	0
T248	715446	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	221741	0	0
T3	13436	2	0	0
T4	109347	988	0	0
T7	517430	449	0	0
T8	447645	1830	0	0
T9	463854	0	0	0
T10	76863	0	0	0
T16	45286	0	0	0
T17	57289	0	0	0
T18	0	174	0	0
T19	325328	1945	0	0
T24	18620	0	0	0
T34	0	1	0	0
T35	0	221	0	0
T40	0	65	0	0
T52	0	2542	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	413977104	0	0
T1	67248	56371	0	0
T2	43674	43588	0	0
T3	13436	8850	0	0
T4	109347	622799	0	0
T7	517430	9335	0	0
T8	447645	55157	0	0
T9	463854	463325	0	0
T10	76863	72798	0	0
T16	45286	45221	0	0
T19	325328	29403	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T3,T7

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T218,T221,T232
1	1	Covered	T1,T3,T7

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T7,T8

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	713624352	2984	0	0
DisabledNoTrigBkwd_A	713624352	189616	0	0
DisabledNoTrigFwd_A	713624352	449638568	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	2984	0	0
T106	29158	0	0	0
T107	209406	0	0	0
T123	90439	0	0	0
T194	147932	0	0	0
T195	34699	0	0	0
T196	488427	0	0	0
T197	37432	0	0	0
T198	114266	0	0	0
T218	1570	741	0	0
T221	0	1166	0	0
T232	0	538	0	0
T233	0	539	0	0
T249	884691	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	189616	0	0
T3	13436	6	0	0
T4	109347	839	0	0
T5	0	116	0	0
T6	0	41	0	0
T7	517430	796	0	0
T8	447645	7	0	0
T9	463854	0	0	0
T10	76863	0	0	0
T16	45286	0	0	0
T17	57289	0	0	0
T19	325328	18	0	0
T24	18620	0	0	0
T45	0	231	0	0
T58	0	6	0	0
T77	0	46	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	449638568	0	0
T1	67248	11530	0	0
T2	43674	43588	0	0
T3	13436	5496	0	0
T4	109347	588808	0	0
T7	517430	27368	0	0
T8	447645	444748	0	0
T9	463854	462727	0	0
T10	76863	5595	0	0
T16	45286	45221	0	0
T19	325328	322477	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T10
1	0	Covered	T1,T3,T7
1	1	Covered	T3,T10,T8

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T215,T216,T223
1	1	Covered	T3,T10,T8

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T8,T19

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	713624352	3383	0	0
DisabledNoTrigBkwd_A	713624352	225613	0	0
DisabledNoTrigFwd_A	713624352	373866173	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	3383	0	0
T21	81746	0	0	0
T26	472378	0	0	0
T63	988002	0	0	0
T65	738591	0	0	0
T78	26490	0	0	0
T100	40271	0	0	0
T132	14195	0	0	0
T215	3176	640	0	0
T216	0	681	0	0
T223	0	764	0	0
T230	0	465	0	0
T234	0	833	0	0
T250	10093	0	0	0
T251	8959	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	225613	0	0
T3	13436	8	0	0
T4	109347	77	0	0
T5	0	242	0	0
T7	517430	0	0	0
T8	447645	12	0	0
T9	463854	0	0	0
T10	76863	0	0	0
T16	45286	0	0	0
T17	57289	0	0	0
T19	325328	2161	0	0
T24	18620	0	0	0
T55	0	6	0	0
T58	0	2211	0	0
T72	0	634	0	0
T77	0	98	0	0
T93	0	10	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	373866173	0	0
T1	67248	67165	0	0
T2	43674	43588	0	0
T3	13436	2874	0	0
T4	109347	104422	0	0
T7	517430	15870	0	0
T8	447645	443135	0	0
T9	463854	461366	0	0
T10	76863	64958	0	0
T16	45286	45221	0	0
T19	325328	21576	0	0