Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
81.69	96.04	76.60		65.00	88.46	82.35

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	87.50	96.04	77.78		92.86	88.46	82.35
tb.dut.gen_classes[2].u_esc_timer	87.50	96.04	77.78		92.86	88.46	82.35
tb.dut.gen_classes[3].u_esc_timer	87.50	96.04	77.78		92.86	88.46	82.35
tb.dut.gen_classes[1].u_esc_timer	87.94	96.04	80.00		92.86	88.46	82.35

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	96.04	77.78		92.86	88.46	82.35

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.22	96.36	77.78	35.71	92.86	89.29	83.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
81.38	100.00		97.26			46.88	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	35.71			35.71
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	96.04	77.78		92.86	88.46	82.35

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.22	96.36	77.78	35.71	92.86	89.29	83.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
81.38	100.00		97.26			46.88	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	35.71			35.71
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	96.04	77.78		92.86	88.46	82.35

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.22	96.36	77.78	35.71	92.86	89.29	83.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
81.38	100.00		97.26			46.88	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	35.71			35.71
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.94	96.04	80.00		92.86	88.46	82.35

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.59	96.36	80.00	35.71	92.86	89.29	83.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
81.38	100.00		97.26			46.88	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	35.71			35.71
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	97	96.04
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	85	95.51
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	0	1
269	0	1
283	1	1
284	0	1
285	0	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	36	76.60
Logical	47	36	76.60
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T3,T7,T8

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T7,T8
1	1	0	Covered	T1,T3,T10
1	1	1	Covered	T1,T2,T3

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T10,T4
1	0	Covered	T19,T5,T6

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T19,T5,T6

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T75
1	1	Covered	T1,T10,T4

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T3,T8,T4

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T3,T7,T10

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T7,T10
1	Covered	T1,T7,T8

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T3,T9,T19

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T3,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T3,T7,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T3,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T3,T7

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	7	87.50	(Not included in score)
Transitions	20	13	65.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Not Covered
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T7
Phase1St	198	Covered	T1,T3,T7
Phase2St	215	Covered	T1,T3,T7
Phase3St	233	Covered	T1,T3,T7
TerminalSt	249	Covered	T1,T3,T7
TimeoutSt	159	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Not Covered
IdleSt->Phase0St	152	Covered	T3,T7,T8
IdleSt->TimeoutSt	159	Covered	T1,T2,T3
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T4,T5,T45
Phase0St->Phase1St	198	Covered	T1,T3,T7
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T4,T17,T76
Phase1St->Phase2St	215	Covered	T1,T3,T7
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T19,T5,T56
Phase2St->Phase3St	233	Covered	T1,T3,T7
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T16,T4,T76
Phase3St->TerminalSt	249	Covered	T1,T3,T7
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T1,T3,T10
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T1,T2,T3
TimeoutSt->Phase0St	172	Covered	T1,T10,T19

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	23	88.46
CASE	144	22	20	90.91
IF	283	2	1	50.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T7,T8
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T10,T19
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T4,T5,T45
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T7
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T7
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T4,T17,T76
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T7
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T7
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T19,T5,T56
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T7
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T16,T4,T76
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T3,T10
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T7
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	14	82.35
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	14	82.35

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	0	0	0
CheckAccumTrig0_A	2147483647	2468	0	0
CheckAccumTrig1_A	2147483647	122	0	0
CheckClr_A	2147483647	1140	0	0
CheckEn_A	2147483647	1253501832	0	0
CheckPhase0_A	2147483647	2809	0	0
CheckPhase1_A	2147483647	2753	0	0
CheckPhase2_A	2147483647	2702	0	0
CheckPhase3_A	2147483647	2651	0	0
CheckTimeout0_A	2147483647	6464	0	0
CheckTimeoutSt1_A	2147483647	669874	0	0
CheckTimeoutSt2_A	2147483647	6062	0	0
CheckTimeoutStTrig_A	2147483647	272	0	0
ErrorStAllEscAsserted_A	2147483647	0	0	0
ErrorStIsTerminal_A	2147483647	0	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2468	0	0
T3	40308	4	0	0
T4	437388	26	0	0
T5	0	5	0	0
T6	0	1	0	0
T7	2069720	3	0	0
T8	1790580	10	0	0
T9	1855416	1	0	0
T10	307452	0	0	0
T16	181144	2	0	0
T17	229156	2	0	0
T18	0	2	0	0
T19	1301312	5	0	0
T24	74480	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T40	0	1	0	0
T44	16935	0	0	0
T45	0	1	0	0
T48	0	1	0	0
T52	0	1	0	0
T58	0	6	0	0
T72	0	1	0	0
T76	0	5	0	0
T77	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	122	0	0
T4	109347	0	0	0
T5	415159	1	0	0
T6	472608	1	0	0
T15	194464	0	0	0
T17	57289	0	0	0
T19	325328	1	0	0
T20	42778	0	0	0
T21	0	1	0	0
T23	899851	0	0	0
T25	41226	0	0	0
T27	0	1	0	0
T45	164427	0	0	0
T46	576287	0	0	0
T47	0	1	0	0
T54	0	1	0	0
T55	331026	0	0	0
T56	170137	0	0	0
T61	0	1	0	0
T64	413422	0	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0
T87	0	1	0	0
T88	0	3	0	0
T89	0	1	0	0
T90	0	1	0	0
T91	18279	0	0	0
T92	22454	0	0	0
T93	22365	0	0	0
T94	48610	0	0	0
T95	81626	0	0	0
T96	108806	0	0	0
T97	89169	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1140	0	0
T1	134496	2	0	0
T2	87348	0	0	0
T3	40308	2	0	0
T4	437388	12	0	0
T5	0	8	0	0
T6	0	2	0	0
T7	1552290	0	0	0
T8	1790580	4	0	0
T9	1855416	0	0	0
T10	230589	1	0	0
T15	0	3	0	0
T16	181144	1	0	0
T17	114578	1	0	0
T19	1301312	2	0	0
T24	37240	0	0	0
T26	0	2	0	0
T34	62547	0	0	0
T44	16935	0	0	0
T45	0	2	0	0
T55	0	5	0	0
T58	0	2	0	0
T63	0	1	0	0
T65	0	1	0	0
T68	0	2	0	0
T76	124898	4	0	0
T93	0	1	0	0
T98	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1253501832	0	0
T1	268992	130932	0	0
T2	174696	132722	0	0
T3	53744	13301	0	0
T4	437388	1998646	0	0
T7	2069720	80104	0	0
T8	1790580	73609	0	0
T9	1855416	1404417	0	0
T10	307452	158872	0	0
T16	181144	136242	0	0
T19	1301312	37142	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2809	0	0
T1	134496	3	0	0
T2	87348	0	0	0
T3	40308	5	0	0
T4	437388	29	0	0
T5	0	6	0	0
T7	2069720	3	0	0
T8	1790580	10	0	0
T9	1855416	1	0	0
T10	307452	2	0	0
T16	181144	2	0	0
T17	114578	2	0	0
T18	0	2	0	0
T19	1301312	6	0	0
T24	37240	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T44	16935	1	0	0
T48	0	1	0	0
T58	0	6	0	0
T72	0	1	0	0
T76	0	5	0	0
T77	0	2	0	0
T91	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2753	0	0
T1	134496	3	0	0
T2	87348	0	0	0
T3	40308	5	0	0
T4	437388	28	0	0
T5	0	5	0	0
T7	2069720	3	0	0
T8	1790580	10	0	0
T9	1855416	1	0	0
T10	307452	2	0	0
T16	181144	2	0	0
T17	114578	1	0	0
T18	0	2	0	0
T19	1301312	6	0	0
T24	37240	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T44	16935	1	0	0
T48	0	1	0	0
T58	0	5	0	0
T72	0	1	0	0
T76	0	4	0	0
T77	0	2	0	0
T91	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2702	0	0
T1	134496	3	0	0
T2	87348	0	0	0
T3	40308	5	0	0
T4	437388	28	0	0
T5	0	4	0	0
T7	2069720	3	0	0
T8	1790580	10	0	0
T9	1855416	1	0	0
T10	307452	2	0	0
T16	181144	2	0	0
T17	114578	1	0	0
T18	0	2	0	0
T19	1301312	5	0	0
T24	37240	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T44	16935	1	0	0
T48	0	1	0	0
T58	0	5	0	0
T72	0	1	0	0
T76	0	4	0	0
T77	0	2	0	0
T91	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2651	0	0
T1	134496	3	0	0
T2	87348	0	0	0
T3	40308	5	0	0
T4	437388	27	0	0
T5	0	4	0	0
T7	2069720	3	0	0
T8	1790580	9	0	0
T9	1855416	1	0	0
T10	307452	2	0	0
T16	181144	1	0	0
T17	114578	1	0	0
T18	0	2	0	0
T19	1301312	5	0	0
T24	37240	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T44	16935	1	0	0
T48	0	1	0	0
T58	0	5	0	0
T72	0	1	0	0
T76	0	3	0	0
T77	0	2	0	0
T91	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6464	0	0
T1	201744	15	0	0
T2	131022	5	0	0
T3	53744	4	0	0
T4	437388	21	0	0
T5	0	8	0	0
T6	0	2	0	0
T7	2069720	0	0	0
T8	1790580	1	0	0
T9	1855416	0	0	0
T10	307452	8	0	0
T15	0	2	0	0
T16	181144	0	0	0
T17	57289	0	0	0
T19	1301312	2	0	0
T20	0	6	0	0
T24	18620	4	0	0
T44	0	6	0	0
T56	0	1	0	0
T76	0	2	0	0
T91	0	2	0	0
T92	0	3	0	0
T95	0	2	0	0
T98	0	1	0	0
T99	0	1	0	0
T100	0	6	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	669874	0	0
T1	201744	2320	0	0
T2	131022	691	0	0
T3	53744	1391	0	0
T4	437388	1158	0	0
T5	0	1270	0	0
T6	0	55	0	0
T7	2069720	0	0	0
T8	1790580	150	0	0
T9	1855416	0	0	0
T10	307452	1011	0	0
T15	0	27	0	0
T16	181144	0	0	0
T17	57289	0	0	0
T19	1301312	24	0	0
T20	0	321	0	0
T24	18620	472	0	0
T44	0	486	0	0
T56	0	89	0	0
T76	0	243	0	0
T91	0	211	0	0
T92	0	486	0	0
T95	0	43	0	0
T98	0	18	0	0
T99	0	375	0	0
T100	0	789	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6062	0	0
T1	201744	12	0	0
T2	131022	5	0	0
T3	53744	2	0	0
T4	437388	5	0	0
T5	0	5	0	0
T6	0	1	0	0
T7	2069720	0	0	0
T8	1790580	1	0	0
T9	1855416	0	0	0
T10	307452	5	0	0
T15	0	1	0	0
T16	181144	0	0	0
T17	57289	0	0	0
T19	1301312	1	0	0
T20	0	7	0	0
T24	18620	4	0	0
T26	0	1	0	0
T44	0	5	0	0
T56	0	1	0	0
T65	0	5	0	0
T76	0	2	0	0
T92	0	3	0	0
T99	0	1	0	0
T100	0	2	0	0
T101	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	272	0	0
T1	134496	3	0	0
T2	87348	0	0	0
T3	40308	0	0	0
T4	437388	3	0	0
T5	0	1	0	0
T7	1552290	0	0	0
T8	1342935	0	0	0
T9	1391562	0	0	0
T10	230589	1	0	0
T15	0	1	0	0
T16	135858	0	0	0
T17	114578	0	0	0
T18	119265	0	0	0
T19	975984	0	0	0
T20	0	1	0	0
T22	0	5	0	0
T24	37240	0	0	0
T34	62547	0	0	0
T35	472146	0	0	0
T44	16935	1	0	0
T47	0	1	0	0
T48	987441	0	0	0
T54	0	4	0	0
T68	0	1	0	0
T72	271814	0	0	0
T76	124898	0	0	0
T81	0	3	0	0
T82	0	1	0	0
T91	0	1	0	0
T100	0	1	0	0
T102	0	2	0	0
T103	0	2	0	0
T104	0	1	0	0
T105	0	2	0	0
T106	0	1	0	0
T107	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	268992	268660	0	0
T2	174696	174352	0	0
T3	53744	53428	0	0
T4	437388	437380	0	0
T7	2069720	2069684	0	0
T8	1790580	1790544	0	0
T9	1855416	1855392	0	0
T10	307452	307152	0	0
T16	181144	180884	0	0
T19	1301312	1301272	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	268992	268660	0	0
T2	174696	174352	0	0
T3	53744	53428	0	0
T4	437388	437380	0	0
T7	2069720	2069684	0	0
T8	1790580	1790544	0	0
T9	1855416	1855392	0	0
T10	307452	307152	0	0
T16	181144	180884	0	0
T19	1301312	1301272	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	97	96.04
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	85	95.51
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	0	1
269	0	1
283	1	1
284	0	1
285	0	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	35	77.78
Logical	45	35	77.78
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T7,T8,T16

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T7,T4,T17
1	1	0	Covered	T10,T19,T4
1	1	1	Covered	T1,T2,T3

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T15,T102
1	0	Covered	T6,T78,T61

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T6,T78,T61

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T15,T102

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T7,T8,T16
1	Covered	T4,T5,T6

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T7,T8,T16
1	Covered	T8,T16,T4

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T8,T16,T9
1	Covered	T7,T8,T16

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T7,T8,T16
1	Covered	T9,T19,T4

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T7,T8,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T7,T8,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T7,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T7,T8,T4

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	7	87.50	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Not Covered
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T7,T8,T16
Phase1St	198	Covered	T7,T8,T16
Phase2St	215	Covered	T7,T8,T16
Phase3St	233	Covered	T7,T8,T16
TerminalSt	249	Covered	T7,T8,T16
TimeoutSt	159	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Not Covered
IdleSt->Phase0St	152	Covered	T7,T8,T16
IdleSt->TimeoutSt	159	Covered	T1,T2,T3
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T45,T74,T81
Phase0St->Phase1St	198	Covered	T7,T8,T16
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T17,T76,T63
Phase1St->Phase2St	215	Covered	T7,T8,T16
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T56,T15,T65
Phase2St->Phase3St	233	Covered	T7,T8,T16
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T16,T4,T76
Phase3St->TerminalSt	249	Covered	T7,T8,T16
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T8,T4,T76
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T2,T3
TimeoutSt->Phase0St	172	Covered	T4,T6,T15

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	23	88.46
CASE	144	22	20	90.91
IF	283	2	1	50.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T16
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T15
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T45,T74,T81
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T7,T8,T16
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T7,T8,T16
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T17,T76,T63
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T7,T8,T16
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T7,T8,T16
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T56,T15,T65
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T7,T8,T16
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T7,T8,T16
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T16,T4,T76
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T7,T8,T16
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T7,T8,T16
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T8,T4,T76
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T7,T8,T16
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	14	82.35
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	14	82.35

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	713624352	0	0	0
CheckAccumTrig0_A	713624352	966	0	0
CheckAccumTrig1_A	713624352	44	0	0
CheckClr_A	713624352	485	0	0
CheckEn_A	713624352	252499434	0	0
CheckPhase0_A	713624352	1061	0	0
CheckPhase1_A	713624352	1035	0	0
CheckPhase2_A	713624352	1009	0	0
CheckPhase3_A	713624352	990	0	0
CheckTimeout0_A	713624352	2030	0	0
CheckTimeoutSt1_A	713624352	210271	0	0
CheckTimeoutSt2_A	713624352	1909	0	0
CheckTimeoutStTrig_A	713624352	74	0	0
ErrorStAllEscAsserted_A	713624352	0	0	0
ErrorStIsTerminal_A	713624352	0	0	0
EscStateOut_A	713624352	713551541	0	0
u_state_regs_A	713624352	713551541	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	966	0	0
T4	109347	10	0	0
T7	517430	1	0	0
T8	447645	5	0	0
T9	463854	1	0	0
T10	76863	0	0	0
T16	45286	2	0	0
T17	57289	2	0	0
T18	0	1	0	0
T19	325328	1	0	0
T24	18620	0	0	0
T44	16935	0	0	0
T48	0	1	0	0
T76	0	5	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	44	0	0
T6	236304	1	0	0
T15	194464	0	0	0
T20	42778	0	0	0
T23	899851	0	0	0
T27	0	1	0	0
T46	576287	0	0	0
T56	170137	0	0	0
T61	0	1	0	0
T64	413422	0	0	0
T78	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0
T95	40813	0	0	0
T96	108806	0	0	0
T97	89169	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	485	0	0
T4	109347	6	0	0
T5	0	2	0	0
T6	0	2	0	0
T8	447645	4	0	0
T9	463854	0	0	0
T16	45286	1	0	0
T17	57289	1	0	0
T19	325328	0	0	0
T24	18620	0	0	0
T34	62547	0	0	0
T44	16935	0	0	0
T45	0	1	0	0
T55	0	5	0	0
T76	124898	4	0	0
T93	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	252499434	0	0
T1	67248	1980	0	0
T2	43674	1961	0	0
T3	13436	5089	0	0
T4	109347	138713	0	0
T7	517430	27531	0	0
T8	447645	18214	0	0
T9	463854	16999	0	0
T10	76863	73248	0	0
T16	45286	582	0	0
T19	325328	14745	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	1061	0	0
T4	109347	13	0	0
T7	517430	1	0	0
T8	447645	5	0	0
T9	463854	1	0	0
T10	76863	0	0	0
T16	45286	2	0	0
T17	57289	2	0	0
T18	0	1	0	0
T19	325328	1	0	0
T24	18620	0	0	0
T44	16935	0	0	0
T48	0	1	0	0
T76	0	5	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	1035	0	0
T4	109347	13	0	0
T7	517430	1	0	0
T8	447645	5	0	0
T9	463854	1	0	0
T10	76863	0	0	0
T16	45286	2	0	0
T17	57289	1	0	0
T18	0	1	0	0
T19	325328	1	0	0
T24	18620	0	0	0
T44	16935	0	0	0
T48	0	1	0	0
T76	0	4	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	1009	0	0
T4	109347	13	0	0
T7	517430	1	0	0
T8	447645	5	0	0
T9	463854	1	0	0
T10	76863	0	0	0
T16	45286	2	0	0
T17	57289	1	0	0
T18	0	1	0	0
T19	325328	1	0	0
T24	18620	0	0	0
T44	16935	0	0	0
T48	0	1	0	0
T76	0	4	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	990	0	0
T4	109347	12	0	0
T7	517430	1	0	0
T8	447645	5	0	0
T9	463854	1	0	0
T10	76863	0	0	0
T16	45286	1	0	0
T17	57289	1	0	0
T18	0	1	0	0
T19	325328	1	0	0
T24	18620	0	0	0
T44	16935	0	0	0
T48	0	1	0	0
T76	0	3	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	2030	0	0
T1	67248	9	0	0
T2	43674	5	0	0
T3	13436	2	0	0
T4	109347	7	0	0
T6	0	1	0	0
T7	517430	0	0	0
T8	447645	0	0	0
T9	463854	0	0	0
T10	76863	0	0	0
T16	45286	0	0	0
T19	325328	1	0	0
T24	0	4	0	0
T44	0	3	0	0
T76	0	2	0	0
T92	0	3	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	210271	0	0
T1	67248	1338	0	0
T2	43674	691	0	0
T3	13436	927	0	0
T4	109347	455	0	0
T6	0	1	0	0
T7	517430	0	0	0
T8	447645	0	0	0
T9	463854	0	0	0
T10	76863	0	0	0
T16	45286	0	0	0
T19	325328	23	0	0
T24	0	472	0	0
T44	0	290	0	0
T76	0	243	0	0
T92	0	486	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	1909	0	0
T1	67248	9	0	0
T2	43674	5	0	0
T3	13436	2	0	0
T4	109347	4	0	0
T7	517430	0	0	0
T8	447645	0	0	0
T9	463854	0	0	0
T10	76863	0	0	0
T16	45286	0	0	0
T19	325328	1	0	0
T20	0	2	0	0
T24	0	4	0	0
T44	0	3	0	0
T76	0	2	0	0
T92	0	3	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	74	0	0
T4	109347	3	0	0
T15	0	1	0	0
T17	57289	0	0	0
T18	119265	0	0	0
T22	0	3	0	0
T24	18620	0	0	0
T34	62547	0	0	0
T35	472146	0	0	0
T44	16935	0	0	0
T48	987441	0	0	0
T54	0	1	0	0
T72	271814	0	0	0
T76	124898	0	0	0
T81	0	2	0	0
T102	0	1	0	0
T103	0	1	0	0
T105	0	2	0	0
T106	0	1	0	0
T107	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	713551541	0	0
T1	67248	67165	0	0
T2	43674	43588	0	0
T3	13436	13357	0	0
T4	109347	109345	0	0
T7	517430	517421	0	0
T8	447645	447636	0	0
T9	463854	463848	0	0
T10	76863	76788	0	0
T16	45286	45221	0	0
T19	325328	325318	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	713551541	0	0
T1	67248	67165	0	0
T2	43674	43588	0	0
T3	13436	13357	0	0
T4	109347	109345	0	0
T7	517430	517421	0	0
T8	447645	447636	0	0
T9	463854	463848	0	0
T10	76863	76788	0	0
T16	45286	45221	0	0
T19	325328	325318	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	97	96.04
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	85	95.51
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	0	1
269	0	1
283	1	1
284	0	1
285	0	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	35	77.78
Logical	45	35	77.78
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T7

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T7
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T7,T8

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T10
1	0	1	Covered	T7,T8,T4
1	1	0	Covered	T1,T3,T4
1	1	1	Covered	T1,T10,T19

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T10,T19
0	1	Covered	T1,T44,T5
1	0	Covered	T19,T4,T108

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T10,T19
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T19,T4,T108

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T19
1	0	Not Covered
1	1	Covered	T1,T44,T5

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T3,T44,T77

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T19
1	Covered	T3,T7,T8

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T7,T8
1	Covered	T1,T19,T58

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T19,T4,T98

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T3,T4,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T3,T19,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T3,T8,T19

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T3,T7

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	7	87.50	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Not Covered
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T7
Phase1St	198	Covered	T1,T3,T7
Phase2St	215	Covered	T1,T3,T7
Phase3St	233	Covered	T1,T3,T7
TerminalSt	249	Covered	T1,T3,T7
TimeoutSt	159	Covered	T1,T10,T19

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Not Covered
IdleSt->Phase0St	152	Covered	T3,T7,T8
IdleSt->TimeoutSt	159	Covered	T1,T10,T19
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T109,T110,T111
Phase0St->Phase1St	198	Covered	T1,T3,T7
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T58,T5,T112
Phase1St->Phase2St	215	Covered	T1,T3,T7
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T19,T5,T54
Phase2St->Phase3St	233	Covered	T1,T3,T7
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T98,T113,T112
Phase3St->TerminalSt	249	Covered	T1,T3,T7
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T3,T19
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T10,T5
TimeoutSt->Phase0St	172	Covered	T1,T19,T4

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	23	88.46
CASE	144	22	20	90.91
IF	283	2	1	50.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T7,T8
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T10,T19
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T4
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T10,T19
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T10,T5
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T109,T110,T111
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T7
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T7
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T58,T112,T114
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T7
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T7
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T19,T54,T53
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T7
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T98,T113,T112
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T3,T19
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T7
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	14	82.35
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	14	82.35

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	713624352	0	0	0
CheckAccumTrig0_A	713624352	494	0	0
CheckAccumTrig1_A	713624352	19	0	0
CheckClr_A	713624352	202	0	0
CheckEn_A	713624352	356807368	0	0
CheckPhase0_A	713624352	574	0	0
CheckPhase1_A	713624352	565	0	0
CheckPhase2_A	713624352	554	0	0
CheckPhase3_A	713624352	547	0	0
CheckTimeout0_A	713624352	1969	0	0
CheckTimeoutSt1_A	713624352	180174	0	0
CheckTimeoutSt2_A	713624352	1879	0	0
CheckTimeoutStTrig_A	713624352	68	0	0
ErrorStAllEscAsserted_A	713624352	0	0	0
ErrorStIsTerminal_A	713624352	0	0	0
EscStateOut_A	713624352	713551541	0	0
u_state_regs_A	713624352	713551541	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	494	0	0
T3	13436	2	0	0
T4	109347	3	0	0
T5	0	3	0	0
T6	0	1	0	0
T7	517430	1	0	0
T8	447645	1	0	0
T9	463854	0	0	0
T10	76863	0	0	0
T16	45286	0	0	0
T17	57289	0	0	0
T19	325328	2	0	0
T24	18620	0	0	0
T45	0	1	0	0
T58	0	2	0	0
T77	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	19	0	0
T4	109347	1	0	0
T17	57289	0	0	0
T18	119265	0	0	0
T19	325328	1	0	0
T24	18620	0	0	0
T34	62547	0	0	0
T44	16935	0	0	0
T48	987441	0	0	0
T72	271814	0	0	0
T76	124898	0	0	0
T88	0	2	0	0
T108	0	1	0	0
T115	0	1	0	0
T116	0	1	0	0
T117	0	1	0	0
T118	0	1	0	0
T119	0	1	0	0
T120	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	202	0	0
T1	67248	1	0	0
T2	43674	0	0	0
T3	13436	2	0	0
T4	109347	0	0	0
T7	517430	0	0	0
T8	447645	0	0	0
T9	463854	0	0	0
T10	76863	0	0	0
T15	0	1	0	0
T16	45286	0	0	0
T19	325328	2	0	0
T22	0	6	0	0
T54	0	5	0	0
T58	0	2	0	0
T68	0	1	0	0
T98	0	2	0	0
T121	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	356807368	0	0
T1	67248	11530	0	0
T2	43674	43587	0	0
T3	13436	4752	0	0
T4	109347	588622	0	0
T7	517430	27368	0	0
T8	447645	8143	0	0
T9	463854	462727	0	0
T10	76863	5595	0	0
T16	45286	45220	0	0
T19	325328	2139	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	574	0	0
T1	67248	2	0	0
T2	43674	0	0	0
T3	13436	2	0	0
T4	109347	4	0	0
T5	0	4	0	0
T7	517430	1	0	0
T8	447645	1	0	0
T9	463854	0	0	0
T10	76863	0	0	0
T16	45286	0	0	0
T19	325328	3	0	0
T44	0	1	0	0
T58	0	2	0	0
T77	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	565	0	0
T1	67248	2	0	0
T2	43674	0	0	0
T3	13436	2	0	0
T4	109347	4	0	0
T5	0	3	0	0
T7	517430	1	0	0
T8	447645	1	0	0
T9	463854	0	0	0
T10	76863	0	0	0
T16	45286	0	0	0
T19	325328	3	0	0
T44	0	1	0	0
T58	0	1	0	0
T77	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	554	0	0
T1	67248	2	0	0
T2	43674	0	0	0
T3	13436	2	0	0
T4	109347	4	0	0
T5	0	2	0	0
T7	517430	1	0	0
T8	447645	1	0	0
T9	463854	0	0	0
T10	76863	0	0	0
T16	45286	0	0	0
T19	325328	2	0	0
T44	0	1	0	0
T58	0	1	0	0
T77	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	547	0	0
T1	67248	2	0	0
T2	43674	0	0	0
T3	13436	2	0	0
T4	109347	4	0	0
T5	0	2	0	0
T7	517430	1	0	0
T8	447645	1	0	0
T9	463854	0	0	0
T10	76863	0	0	0
T16	45286	0	0	0
T19	325328	2	0	0
T44	0	1	0	0
T58	0	1	0	0
T77	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	1969	0	0
T1	67248	4	0	0
T2	43674	0	0	0
T3	13436	0	0	0
T4	109347	1	0	0
T5	0	3	0	0
T7	517430	0	0	0
T8	447645	0	0	0
T9	463854	0	0	0
T10	76863	5	0	0
T16	45286	0	0	0
T19	325328	1	0	0
T20	0	1	0	0
T44	0	1	0	0
T91	0	1	0	0
T99	0	1	0	0
T100	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	180174	0	0
T1	67248	616	0	0
T2	43674	0	0	0
T3	13436	0	0	0
T4	109347	10	0	0
T5	0	432	0	0
T7	517430	0	0	0
T8	447645	0	0	0
T9	463854	0	0	0
T10	76863	674	0	0
T16	45286	0	0	0
T19	325328	1	0	0
T20	0	64	0	0
T44	0	7	0	0
T91	0	206	0	0
T99	0	375	0	0
T100	0	49	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	1879	0	0
T1	67248	2	0	0
T2	43674	0	0	0
T3	13436	0	0	0
T4	109347	0	0	0
T5	0	2	0	0
T7	517430	0	0	0
T8	447645	0	0	0
T9	463854	0	0	0
T10	76863	5	0	0
T16	45286	0	0	0
T19	325328	0	0	0
T22	0	8	0	0
T26	0	1	0	0
T54	0	1	0	0
T65	0	5	0	0
T99	0	1	0	0
T101	0	1	0	0
T122	0	4	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	68	0	0
T1	67248	2	0	0
T2	43674	0	0	0
T3	13436	0	0	0
T4	109347	0	0	0
T5	0	1	0	0
T7	517430	0	0	0
T8	447645	0	0	0
T9	463854	0	0	0
T10	76863	0	0	0
T16	45286	0	0	0
T19	325328	0	0	0
T20	0	1	0	0
T22	0	2	0	0
T36	0	1	0	0
T44	0	1	0	0
T54	0	2	0	0
T91	0	1	0	0
T100	0	1	0	0
T123	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	713551541	0	0
T1	67248	67165	0	0
T2	43674	43588	0	0
T3	13436	13357	0	0
T4	109347	109345	0	0
T7	517430	517421	0	0
T8	447645	447636	0	0
T9	463854	463848	0	0
T10	76863	76788	0	0
T16	45286	45221	0	0
T19	325328	325318	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	713551541	0	0
T1	67248	67165	0	0
T2	43674	43588	0	0
T3	13436	13357	0	0
T4	109347	109345	0	0
T7	517430	517421	0	0
T8	447645	447636	0	0
T9	463854	463848	0	0
T10	76863	76788	0	0
T16	45286	45221	0	0
T19	325328	325318	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	97	96.04
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	85	95.51
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	0	1
269	0	1
283	1	1
284	0	1
285	0	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	35	77.78
Logical	45	35	77.78
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T10,T8
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T10,T8

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T7,T10
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T8,T19

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T10,T8
1	0	1	Covered	T4,T34,T18
1	1	0	Covered	T1,T10,T8
1	1	1	Covered	T3,T10,T4

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T4
0	1	Covered	T3,T10,T91
1	0	Covered	T95,T15,T98

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T10,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T95,T15,T98

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T4
1	0	Not Covered
1	1	Covered	T3,T10,T91

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T10,T8
1	Covered	T72,T5,T55

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T10,T8,T19
1	Covered	T3,T8,T77

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T10,T8
1	Covered	T8,T4,T58

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T8,T4
1	Covered	T10,T8,T19

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T10,T8,T19

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T8,T19,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T3,T8,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T10,T4,T72

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	7	87.50	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Not Covered
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T3,T10,T8
Phase1St	198	Covered	T3,T10,T8
Phase2St	215	Covered	T3,T10,T8
Phase3St	233	Covered	T3,T10,T8
TerminalSt	249	Covered	T3,T10,T8
TimeoutSt	159	Covered	T3,T10,T4

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Not Covered
IdleSt->Phase0St	152	Covered	T3,T8,T19
IdleSt->TimeoutSt	159	Covered	T3,T10,T4
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T55,T27,T124
Phase0St->Phase1St	198	Covered	T3,T10,T8
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T55,T125,T126
Phase1St->Phase2St	215	Covered	T3,T10,T8
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T65,T127,T42
Phase2St->Phase3St	233	Covered	T3,T10,T8
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T8,T128,T126
Phase3St->TerminalSt	249	Covered	T3,T10,T8
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T3,T8,T4
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T3,T10,T4
TimeoutSt->Phase0St	172	Covered	T3,T10,T91

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	23	88.46
CASE	144	22	20	90.91
IF	283	2	1	50.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T8,T19
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T10,T4
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T10,T91
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T10,T4
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T10,T4
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T55,T124,T129
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T10,T8
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T10,T8
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T55,T125,T126
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T10,T8
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T10,T8
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T65,T127,T42
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T10,T8
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T10,T8
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T8,T128,T126
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T10,T8
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T10,T8
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T8,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T10,T8
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	14	82.35
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	14	82.35

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	713624352	0	0	0
CheckAccumTrig0_A	713624352	525	0	0
CheckAccumTrig1_A	713624352	32	0	0
CheckClr_A	713624352	249	0	0
CheckEn_A	713624352	296444880	0	0
CheckPhase0_A	713624352	623	0	0
CheckPhase1_A	713624352	612	0	0
CheckPhase2_A	713624352	604	0	0
CheckPhase3_A	713624352	590	0	0
CheckTimeout0_A	713624352	888	0	0
CheckTimeoutSt1_A	713624352	107854	0	0
CheckTimeoutSt2_A	713624352	779	0	0
CheckTimeoutStTrig_A	713624352	75	0	0
ErrorStAllEscAsserted_A	713624352	0	0	0
ErrorStIsTerminal_A	713624352	0	0	0
EscStateOut_A	713624352	713551541	0	0
u_state_regs_A	713624352	713551541	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	525	0	0
T3	13436	1	0	0
T4	109347	3	0	0
T5	0	2	0	0
T7	517430	0	0	0
T8	447645	3	0	0
T9	463854	0	0	0
T10	76863	0	0	0
T16	45286	0	0	0
T17	57289	0	0	0
T19	325328	1	0	0
T24	18620	0	0	0
T55	0	3	0	0
T58	0	4	0	0
T72	0	1	0	0
T77	0	1	0	0
T93	0	3	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	32	0	0
T15	194464	1	0	0
T20	42778	0	0	0
T21	0	1	0	0
T23	899851	0	0	0
T27	0	1	0	0
T36	0	1	0	0
T46	576287	0	0	0
T49	478918	0	0	0
T56	170137	0	0	0
T64	413422	0	0	0
T81	0	1	0	0
T95	40813	1	0	0
T96	108806	0	0	0
T97	89169	0	0	0
T98	0	1	0	0
T123	0	1	0	0
T130	0	1	0	0
T131	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	249	0	0
T3	13436	2	0	0
T4	109347	1	0	0
T7	517430	0	0	0
T8	447645	2	0	0
T9	463854	0	0	0
T10	76863	0	0	0
T15	0	1	0	0
T16	45286	0	0	0
T17	57289	0	0	0
T19	325328	0	0	0
T24	18620	0	0	0
T55	0	2	0	0
T58	0	3	0	0
T65	0	2	0	0
T93	0	3	0	0
T95	0	1	0	0
T98	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	296444880	0	0
T1	67248	67164	0	0
T2	43674	43587	0	0
T3	13436	2874	0	0
T4	109347	648513	0	0
T7	517430	15870	0	0
T8	447645	18698	0	0
T9	463854	461366	0	0
T10	76863	7232	0	0
T16	45286	45220	0	0
T19	325328	10146	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	623	0	0
T3	13436	2	0	0
T4	109347	3	0	0
T5	0	2	0	0
T7	517430	0	0	0
T8	447645	3	0	0
T9	463854	0	0	0
T10	76863	1	0	0
T16	45286	0	0	0
T17	57289	0	0	0
T19	325328	1	0	0
T24	18620	0	0	0
T58	0	4	0	0
T72	0	1	0	0
T77	0	1	0	0
T91	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	612	0	0
T3	13436	2	0	0
T4	109347	3	0	0
T5	0	2	0	0
T7	517430	0	0	0
T8	447645	3	0	0
T9	463854	0	0	0
T10	76863	1	0	0
T16	45286	0	0	0
T17	57289	0	0	0
T19	325328	1	0	0
T24	18620	0	0	0
T58	0	4	0	0
T72	0	1	0	0
T77	0	1	0	0
T91	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	604	0	0
T3	13436	2	0	0
T4	109347	3	0	0
T5	0	2	0	0
T7	517430	0	0	0
T8	447645	3	0	0
T9	463854	0	0	0
T10	76863	1	0	0
T16	45286	0	0	0
T17	57289	0	0	0
T19	325328	1	0	0
T24	18620	0	0	0
T58	0	4	0	0
T72	0	1	0	0
T77	0	1	0	0
T91	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	590	0	0
T3	13436	2	0	0
T4	109347	3	0	0
T5	0	2	0	0
T7	517430	0	0	0
T8	447645	2	0	0
T9	463854	0	0	0
T10	76863	1	0	0
T16	45286	0	0	0
T17	57289	0	0	0
T19	325328	1	0	0
T24	18620	0	0	0
T58	0	4	0	0
T72	0	1	0	0
T77	0	1	0	0
T91	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	888	0	0
T3	13436	2	0	0
T4	109347	12	0	0
T5	0	1	0	0
T7	517430	0	0	0
T8	447645	0	0	0
T9	463854	0	0	0
T10	76863	2	0	0
T15	0	1	0	0
T16	45286	0	0	0
T17	57289	0	0	0
T19	325328	0	0	0
T21	0	1	0	0
T24	18620	0	0	0
T91	0	1	0	0
T95	0	2	0	0
T98	0	1	0	0
T100	0	5	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	107854	0	0
T3	13436	464	0	0
T4	109347	595	0	0
T5	0	243	0	0
T7	517430	0	0	0
T8	447645	0	0	0
T9	463854	0	0	0
T10	76863	191	0	0
T15	0	4	0	0
T16	45286	0	0	0
T17	57289	0	0	0
T19	325328	0	0	0
T21	0	1	0	0
T24	18620	0	0	0
T91	0	5	0	0
T95	0	43	0	0
T98	0	18	0	0
T100	0	740	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	779	0	0
T3	13436	1	0	0
T4	109347	12	0	0
T5	0	1	0	0
T7	517430	0	0	0
T8	447645	0	0	0
T9	463854	0	0	0
T10	76863	1	0	0
T16	45286	0	0	0
T17	57289	0	0	0
T19	325328	0	0	0
T22	0	34	0	0
T24	18620	0	0	0
T95	0	1	0	0
T100	0	5	0	0
T122	0	2	0	0
T132	0	4	0	0
T133	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	75	0	0
T3	13436	1	0	0
T4	109347	0	0	0
T7	517430	0	0	0
T8	447645	0	0	0
T9	463854	0	0	0
T10	76863	1	0	0
T16	45286	0	0	0
T17	57289	0	0	0
T19	325328	0	0	0
T22	0	1	0	0
T24	18620	0	0	0
T54	0	1	0	0
T65	0	1	0	0
T91	0	1	0	0
T101	0	1	0	0
T103	0	1	0	0
T104	0	1	0	0
T133	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	713551541	0	0
T1	67248	67165	0	0
T2	43674	43588	0	0
T3	13436	13357	0	0
T4	109347	109345	0	0
T7	517430	517421	0	0
T8	447645	447636	0	0
T9	463854	463848	0	0
T10	76863	76788	0	0
T16	45286	45221	0	0
T19	325328	325318	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	713551541	0	0
T1	67248	67165	0	0
T2	43674	43588	0	0
T3	13436	13357	0	0
T4	109347	109345	0	0
T7	517430	517421	0	0
T8	447645	447636	0	0
T9	463854	463848	0	0
T10	76863	76788	0	0
T16	45286	45221	0	0
T19	325328	325318	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	97	96.04
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	85	95.51
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	0	1
269	0	1
283	1	1
284	0	1
285	0	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	36	80.00
Logical	45	36	80.00
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T7

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T7
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T7,T8

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T10,T8
1	0	1	Covered	T3,T8,T4
1	1	0	Covered	T1,T10,T8
1	1	1	Covered	T1,T10,T8

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T10,T8
0	1	Covered	T1,T10,T102
1	0	Covered	T5,T21,T54

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T10,T8
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T5,T21,T54

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T8
1	0	Covered	T75
1	1	Covered	T1,T10,T102

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T8,T4,T52

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T7
1	Covered	T10,T19,T40

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T10,T8
1	Covered	T1,T7,T18

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T7,T10
1	Covered	T3,T4,T34

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T3,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T3,T10,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T3,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T3,T7

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	7	87.50	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Not Covered
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T7
Phase1St	198	Covered	T1,T3,T7
Phase2St	215	Covered	T1,T3,T7
Phase3St	233	Covered	T1,T3,T7
TerminalSt	249	Covered	T1,T3,T7
TimeoutSt	159	Covered	T1,T10,T8

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Not Covered
IdleSt->Phase0St	152	Covered	T3,T7,T8
IdleSt->TimeoutSt	159	Covered	T1,T10,T8
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T4,T5,T69
Phase0St->Phase1St	198	Covered	T1,T3,T7
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T4,T110,T124
Phase1St->Phase2St	215	Covered	T1,T3,T7
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T5,T54,T69
Phase2St->Phase3St	233	Covered	T1,T3,T7
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T5,T134,T131
Phase3St->TerminalSt	249	Covered	T1,T3,T7
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T10,T4
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T8,T4
TimeoutSt->Phase0St	172	Covered	T1,T10,T5

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	23	88.46
CASE	144	22	20	90.91
IF	283	2	1	50.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T7,T8
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T10,T8
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T10,T5
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T10,T8
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T8,T4
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T4,T5,T69
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T7
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T7
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T4,T110,T124
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T7
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T7
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T5,T54,T69
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T7
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T5,T134,T131
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T10,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T7
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	14	82.35
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	14	82.35

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	713624352	0	0	0
CheckAccumTrig0_A	713624352	483	0	0
CheckAccumTrig1_A	713624352	27	0	0
CheckClr_A	713624352	204	0	0
CheckEn_A	713624352	347750150	0	0
CheckPhase0_A	713624352	551	0	0
CheckPhase1_A	713624352	541	0	0
CheckPhase2_A	713624352	535	0	0
CheckPhase3_A	713624352	524	0	0
CheckTimeout0_A	713624352	1577	0	0
CheckTimeoutSt1_A	713624352	171575	0	0
CheckTimeoutSt2_A	713624352	1495	0	0
CheckTimeoutStTrig_A	713624352	55	0	0
ErrorStAllEscAsserted_A	713624352	0	0	0
ErrorStIsTerminal_A	713624352	0	0	0
EscStateOut_A	713624352	713551541	0	0
u_state_regs_A	713624352	713551541	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	483	0	0
T3	13436	1	0	0
T4	109347	10	0	0
T7	517430	1	0	0
T8	447645	1	0	0
T9	463854	0	0	0
T10	76863	0	0	0
T16	45286	0	0	0
T17	57289	0	0	0
T18	0	1	0	0
T19	325328	1	0	0
T24	18620	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T40	0	1	0	0
T52	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	27	0	0
T5	415159	1	0	0
T6	236304	0	0	0
T21	0	1	0	0
T25	41226	0	0	0
T45	164427	0	0	0
T47	0	1	0	0
T54	0	1	0	0
T55	331026	0	0	0
T85	0	1	0	0
T86	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0
T89	0	1	0	0
T90	0	1	0	0
T91	18279	0	0	0
T92	22454	0	0	0
T93	22365	0	0	0
T94	48610	0	0	0
T95	40813	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	204	0	0
T1	67248	1	0	0
T2	43674	0	0	0
T3	13436	0	0	0
T4	109347	6	0	0
T5	0	6	0	0
T7	517430	0	0	0
T8	447645	0	0	0
T9	463854	0	0	0
T10	76863	1	0	0
T15	0	2	0	0
T16	45286	0	0	0
T19	325328	0	0	0
T26	0	2	0	0
T45	0	1	0	0
T63	0	1	0	0
T65	0	1	0	0
T68	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	347750150	0	0
T1	67248	50258	0	0
T2	43674	43587	0	0
T3	13436	586	0	0
T4	109347	622798	0	0
T7	517430	9335	0	0
T8	447645	28554	0	0
T9	463854	463325	0	0
T10	76863	72797	0	0
T16	45286	45220	0	0
T19	325328	10112	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	551	0	0
T1	67248	1	0	0
T2	43674	0	0	0
T3	13436	1	0	0
T4	109347	9	0	0
T7	517430	1	0	0
T8	447645	1	0	0
T9	463854	0	0	0
T10	76863	1	0	0
T16	45286	0	0	0
T18	0	1	0	0
T19	325328	1	0	0
T34	0	1	0	0
T35	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	541	0	0
T1	67248	1	0	0
T2	43674	0	0	0
T3	13436	1	0	0
T4	109347	8	0	0
T7	517430	1	0	0
T8	447645	1	0	0
T9	463854	0	0	0
T10	76863	1	0	0
T16	45286	0	0	0
T18	0	1	0	0
T19	325328	1	0	0
T34	0	1	0	0
T35	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	535	0	0
T1	67248	1	0	0
T2	43674	0	0	0
T3	13436	1	0	0
T4	109347	8	0	0
T7	517430	1	0	0
T8	447645	1	0	0
T9	463854	0	0	0
T10	76863	1	0	0
T16	45286	0	0	0
T18	0	1	0	0
T19	325328	1	0	0
T34	0	1	0	0
T35	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	524	0	0
T1	67248	1	0	0
T2	43674	0	0	0
T3	13436	1	0	0
T4	109347	8	0	0
T7	517430	1	0	0
T8	447645	1	0	0
T9	463854	0	0	0
T10	76863	1	0	0
T16	45286	0	0	0
T18	0	1	0	0
T19	325328	1	0	0
T34	0	1	0	0
T35	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	1577	0	0
T1	67248	2	0	0
T2	43674	0	0	0
T3	13436	0	0	0
T4	109347	1	0	0
T5	0	4	0	0
T6	0	1	0	0
T7	517430	0	0	0
T8	447645	1	0	0
T9	463854	0	0	0
T10	76863	1	0	0
T15	0	1	0	0
T16	45286	0	0	0
T19	325328	0	0	0
T20	0	5	0	0
T44	0	2	0	0
T56	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	171575	0	0
T1	67248	366	0	0
T2	43674	0	0	0
T3	13436	0	0	0
T4	109347	98	0	0
T5	0	595	0	0
T6	0	54	0	0
T7	517430	0	0	0
T8	447645	150	0	0
T9	463854	0	0	0
T10	76863	146	0	0
T15	0	23	0	0
T16	45286	0	0	0
T19	325328	0	0	0
T20	0	257	0	0
T44	0	189	0	0
T56	0	89	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	1495	0	0
T1	67248	1	0	0
T2	43674	0	0	0
T3	13436	0	0	0
T4	109347	1	0	0
T5	0	3	0	0
T6	0	1	0	0
T7	517430	0	0	0
T8	447645	1	0	0
T9	463854	0	0	0
T10	76863	0	0	0
T15	0	1	0	0
T16	45286	0	0	0
T19	325328	0	0	0
T20	0	5	0	0
T44	0	2	0	0
T56	0	1	0	0
T100	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	55	0	0
T1	67248	1	0	0
T2	43674	0	0	0
T3	13436	0	0	0
T4	109347	0	0	0
T7	517430	0	0	0
T8	447645	0	0	0
T9	463854	0	0	0
T10	76863	1	0	0
T16	45286	0	0	0
T19	325328	0	0	0
T47	0	1	0	0
T54	0	1	0	0
T68	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T102	0	1	0	0
T103	0	1	0	0
T104	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	713551541	0	0
T1	67248	67165	0	0
T2	43674	43588	0	0
T3	13436	13357	0	0
T4	109347	109345	0	0
T7	517430	517421	0	0
T8	447645	447636	0	0
T9	463854	463848	0	0
T10	76863	76788	0	0
T16	45286	45221	0	0
T19	325328	325318	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	713624352	713551541	0	0
T1	67248	67165	0	0
T2	43674	43588	0	0
T3	13436	13357	0	0
T4	109347	109345	0	0
T7	517430	517421	0	0
T8	447645	447636	0	0
T9	463854	463848	0	0
T10	76863	76788	0	0
T16	45286	45221	0	0
T19	325328	325318	0	0