Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	64412631	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

31239084

1

T1

884

T2

3298

T3

161

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	14279468	1			T1	329		T2	1293		T3	68
values[0x0]	39693193	1			T1	1116		T2	4255		T3	224
values[0x1]	41679054	1			T1	1100		T2	4353		T3	220

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	55041635	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

40610080

1

T1

1081

T2

4136

T3

219

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	314597	1			T1	6		T2	21		T4	16
valid_sources[0x01]	317118	1			T1	9		T2	52		T5	8
valid_sources[0x02]	310697	1			T1	9		T2	19		T5	5
valid_sources[0x03]	311122	1			T1	10		T2	39		T4	6
valid_sources[0x04]	317353	1			T1	13		T2	21		T7	1057
valid_sources[0x05]	336013	1			T1	13		T2	13		T4	8
valid_sources[0x06]	313178	1			T1	8		T2	41		T5	1
valid_sources[0x07]	319707	1			T1	5		T2	20		T5	2
valid_sources[0x08]	318328	1			T1	11		T2	31		T5	1
valid_sources[0x09]	320402	1			T1	8		T2	64		T3	20
valid_sources[0x0a]	311124	1			T1	11		T2	10		T4	6
valid_sources[0x0b]	309993	1			T1	6		T2	7		T4	2
valid_sources[0x0c]	316579	1			T1	15		T2	19		T4	3
valid_sources[0x0d]	312812	1			T1	10		T2	43		T4	10
valid_sources[0x0e]	317442	1			T1	9		T2	20		T5	1
valid_sources[0x0f]	312593	1			T1	9		T2	59		T3	8
valid_sources[0x10]	352228	1			T1	11		T2	37		T4	8
valid_sources[0x11]	312609	1			T1	9		T2	13		T3	11
valid_sources[0x12]	322146	1			T1	9		T2	53		T5	6
valid_sources[0x13]	315763	1			T1	8		T2	59		T3	1
valid_sources[0x14]	787111	1			T1	11		T2	75		T5	3
valid_sources[0x15]	315739	1			T1	3		T2	44		T7	1025
valid_sources[0x16]	324347	1			T1	7		T2	24		T3	11
valid_sources[0x17]	310557	1			T1	15		T2	45		T4	1
valid_sources[0x18]	307570	1			T1	11		T2	31		T3	2
valid_sources[0x19]	354447	1			T1	10		T2	25		T4	3
valid_sources[0x1a]	310396	1			T1	4		T2	33		T5	8
valid_sources[0x1b]	310700	1			T1	8		T2	32		T7	1028
valid_sources[0x1c]	316398	1			T1	11		T2	31		T4	6
valid_sources[0x1d]	320253	1			T1	8		T2	12		T4	15
valid_sources[0x1e]	317931	1			T1	14		T2	52		T5	2
valid_sources[0x1f]	344710	1			T1	11		T2	98		T4	1
valid_sources[0x20]	321094	1			T1	10		T2	51		T4	8
valid_sources[0x21]	313691	1			T1	6		T2	46		T4	8
valid_sources[0x22]	329561	1			T1	12		T2	35		T4	1
valid_sources[0x23]	306771	1			T1	9		T2	53		T4	14
valid_sources[0x24]	366759	1			T1	13		T2	26		T3	4
valid_sources[0x25]	313076	1			T1	12		T2	67		T4	1
valid_sources[0x26]	676849	1			T1	15		T2	56		T4	28
valid_sources[0x27]	316766	1			T1	6		T2	24		T4	5
valid_sources[0x28]	315595	1			T1	7		T2	29		T3	8
valid_sources[0x29]	319849	1			T1	18		T2	39		T3	7
valid_sources[0x2a]	329131	1			T1	10		T2	33		T7	1084
valid_sources[0x2b]	310486	1			T1	8		T2	74		T3	10
valid_sources[0x2c]	322174	1			T1	8		T2	57		T3	11
valid_sources[0x2d]	313714	1			T1	11		T2	48		T3	7
valid_sources[0x2e]	317521	1			T1	12		T2	49		T5	1
valid_sources[0x2f]	309048	1			T1	8		T2	38		T5	2
valid_sources[0x30]	317952	1			T1	7		T2	60		T4	8
valid_sources[0x31]	312278	1			T1	9		T2	48		T4	14
valid_sources[0x32]	318102	1			T1	12		T2	54		T5	3
valid_sources[0x33]	320833	1			T1	14		T2	37		T7	1033
valid_sources[0x34]	317284	1			T1	16		T2	48		T7	1113
valid_sources[0x35]	326023	1			T1	4		T2	7		T7	1058
valid_sources[0x36]	309103	1			T1	11		T2	57		T4	10
valid_sources[0x37]	329228	1			T1	9		T2	64		T3	5
valid_sources[0x38]	327439	1			T1	9		T2	46		T4	2
valid_sources[0x39]	323202	1			T1	4		T2	32		T3	15
valid_sources[0x3a]	319402	1			T1	18		T2	12		T4	19
valid_sources[0x3b]	803059	1			T1	11		T2	31		T4	5
valid_sources[0x3c]	311765	1			T1	10		T2	74		T4	1
valid_sources[0x3d]	324460	1			T1	5		T2	66		T7	1089
valid_sources[0x3e]	330786	1			T1	18		T2	7		T3	2
valid_sources[0x3f]	313086	1			T1	8		T2	45		T4	19
valid_sources[0x40]	329446	1			T1	8		T2	66		T3	3
valid_sources[0x41]	307478	1			T1	13		T2	42		T4	57
valid_sources[0x42]	315425	1			T1	5		T2	40		T4	11
valid_sources[0x43]	726988	1			T1	10		T2	8		T4	9
valid_sources[0x44]	326513	1			T1	13		T2	92		T5	4
valid_sources[0x45]	318227	1			T1	9		T2	77		T7	1043
valid_sources[0x46]	318251	1			T1	18		T2	14		T4	16
valid_sources[0x47]	316945	1			T1	11		T2	11		T4	7
valid_sources[0x48]	319215	1			T1	9		T2	13		T3	4
valid_sources[0x49]	308105	1			T1	11		T2	11		T4	12
valid_sources[0x4a]	334993	1			T1	19		T2	36		T3	12
valid_sources[0x4b]	316479	1			T1	14		T2	39		T5	2
valid_sources[0x4c]	760117	1			T1	11		T2	49		T3	7
valid_sources[0x4d]	317635	1			T1	4		T2	7		T3	8
valid_sources[0x4e]	325910	1			T1	13		T2	33		T5	1
valid_sources[0x4f]	797816	1			T1	8		T2	59		T7	1096
valid_sources[0x50]	322242	1			T1	15		T2	13		T3	2
valid_sources[0x51]	326634	1			T1	11		T2	37		T5	3
valid_sources[0x52]	318098	1			T1	10		T2	32		T5	9
valid_sources[0x53]	323858	1			T1	8		T2	54		T5	2
valid_sources[0x54]	314151	1			T1	10		T2	50		T4	18
valid_sources[0x55]	316064	1			T1	7		T2	53		T5	2
valid_sources[0x56]	313697	1			T1	8		T2	46		T3	8
valid_sources[0x57]	315649	1			T1	16		T2	37		T5	4
valid_sources[0x58]	323030	1			T1	15		T2	28		T7	1033
valid_sources[0x59]	308146	1			T1	8		T2	59		T3	27
valid_sources[0x5a]	792929	1			T1	14		T2	61		T4	6
valid_sources[0x5b]	642003	1			T1	7		T2	23		T4	12
valid_sources[0x5c]	330663	1			T1	12		T2	28		T3	3
valid_sources[0x5d]	310350	1			T1	5		T2	35		T4	6
valid_sources[0x5e]	341575	1			T1	12		T2	61		T5	2
valid_sources[0x5f]	313695	1			T1	7		T2	30		T5	2
valid_sources[0x60]	316393	1			T1	8		T2	9		T5	2
valid_sources[0x61]	315739	1			T1	13		T2	39		T7	1064
valid_sources[0x62]	325672	1			T1	10		T2	40		T3	8
valid_sources[0x63]	317607	1			T1	9		T2	49		T4	5
valid_sources[0x64]	644733	1			T1	9		T2	29		T4	27
valid_sources[0x65]	339315	1			T1	8		T2	76		T3	9
valid_sources[0x66]	343951	1			T1	6		T2	57		T4	12
valid_sources[0x67]	316717	1			T1	10		T2	19		T3	3
valid_sources[0x68]	311913	1			T1	8		T2	32		T3	38
valid_sources[0x69]	316925	1			T1	8		T2	50		T7	1021
valid_sources[0x6a]	316876	1			T1	13		T2	64		T4	1
valid_sources[0x6b]	328878	1			T1	14		T2	48		T4	15
valid_sources[0x6c]	710216	1			T1	8		T2	78		T5	2
valid_sources[0x6d]	714532	1			T1	6		T2	45		T7	1010
valid_sources[0x6e]	325927	1			T1	7		T2	17		T4	1
valid_sources[0x6f]	317039	1			T1	13		T2	35		T4	3
valid_sources[0x70]	315168	1			T1	10		T2	14		T3	1
valid_sources[0x71]	325710	1			T1	7		T2	44		T4	26
valid_sources[0x72]	315187	1			T1	13		T2	43		T7	1099
valid_sources[0x73]	311450	1			T1	7		T2	8		T5	2
valid_sources[0x74]	321753	1			T1	17		T2	85		T4	17
valid_sources[0x75]	319722	1			T1	10		T2	66		T4	5
valid_sources[0x76]	324810	1			T1	5		T2	57		T4	1
valid_sources[0x77]	310918	1			T1	7		T2	52		T4	1
valid_sources[0x78]	328127	1			T1	10		T2	51		T4	1
valid_sources[0x79]	315683	1			T1	8		T2	22		T4	7
valid_sources[0x7a]	315449	1			T1	10		T2	36		T5	3
valid_sources[0x7b]	602799	1			T1	10		T2	58		T5	6
valid_sources[0x7c]	321907	1			T1	12		T2	44		T3	4
valid_sources[0x7d]	596153	1			T1	4		T2	18		T3	3
valid_sources[0x7e]	604822	1			T1	8		T2	50		T5	3
valid_sources[0x7f]	312809	1			T1	8		T2	31		T7	1123
valid_sources[0x80]	648181	1			T1	9		T2	56		T4	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7134660

1

T1

179

T2

680

T3

34

values[0x0]

all_enables

biggest_size

15209692

1

T1

442

T2

1637

T3

82

values[0x1]

all_enables

biggest_size

8894732

1

T1

263

T2

981

T3

45