Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T19,T225,T226
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T5,T6

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	15036	0	0
DisabledNoTrigBkwd_A	2147483647	813356	0	0
DisabledNoTrigFwd_A	2147483647	1580685297	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15036	0	0
T8	114631	0	0	0
T9	265758	0	0	0
T10	439795	0	0	0
T14	26848	0	0	0
T15	234616	0	0	0
T16	295317	0	0	0
T17	279237	0	0	0
T19	1124	363	0	0
T20	31128	0	0	0
T21	40824	0	0	0
T28	1005400	0	0	0
T44	1836678	0	0	0
T45	70829	0	0	0
T126	1874770	0	0	0
T127	539072	0	0	0
T128	51272	0	0	0
T129	275409	0	0	0
T130	20627	0	0	0
T131	39397	0	0	0
T225	4077	538	0	0
T226	0	922	0	0
T227	3310	826	0	0
T228	0	890	0	0
T229	0	639	0	0
T230	0	271	0	0
T231	0	1881	0	0
T232	0	243	0	0
T233	0	332	0	0
T234	0	555	0	0
T235	0	834	0	0
T236	0	680	0	0
T237	0	1296	0	0
T238	0	560	0	0
T239	0	1296	0	0
T240	0	1187	0	0
T241	0	233	0	0
T242	0	678	0	0
T243	0	812	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	813356	0	0
T2	31258	9	0	0
T3	5798	0	0	0
T4	34711	0	0	0
T5	16866	0	0	0
T6	2225664	3815	0	0
T7	2824962	1	0	0
T8	458524	20	0	0
T9	797274	2	0	0
T10	439795	1713	0	0
T11	0	10	0	0
T14	80544	0	0	0
T15	703848	864	0	0
T16	295317	1001	0	0
T17	279237	372	0	0
T18	139632	0	0	0
T19	3372	15	0	0
T20	124512	29	0	0
T21	122472	110	0	0
T31	0	1	0	0
T32	0	1	0	0
T37	536977	994	0	0
T38	0	1	0	0
T39	0	62	0	0
T40	0	1	0	0
T41	0	93	0	0
T42	0	2759	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1580685297	0	0
T1	104588	76921	0	0
T2	125032	95566	0	0
T3	23192	17700	0	0
T4	138844	35344	0	0
T5	67464	9820	0	0
T6	2967552	753710	0	0
T7	3766616	1890763	0	0
T8	458524	1426608	0	0
T18	186176	92210	0	0
T19	4496	2592	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T6,T18

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T19,T228,T232
1	1	Covered	T2,T6,T18

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T6,T19

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	715908204	3243	0	0
DisabledNoTrigBkwd_A	715908204	224123	0	0
DisabledNoTrigFwd_A	715908204	387832513	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	3243	0	0
T8	114631	0	0	0
T9	265758	0	0	0
T10	439795	0	0	0
T14	26848	0	0	0
T15	234616	0	0	0
T16	295317	0	0	0
T17	279237	0	0	0
T19	1124	363	0	0
T20	31128	0	0	0
T21	40824	0	0	0
T228	0	890	0	0
T232	0	243	0	0
T238	0	560	0	0
T240	0	1187	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	224123	0	0
T2	31258	9	0	0
T3	5798	0	0	0
T4	34711	0	0	0
T5	16866	0	0	0
T6	741888	1411	0	0
T7	941654	0	0	0
T8	114631	0	0	0
T9	0	1	0	0
T10	0	1021	0	0
T16	0	989	0	0
T18	46544	0	0	0
T19	1124	15	0	0
T20	31128	0	0	0
T21	0	30	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	20	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	387832513	0	0
T1	26147	26071	0	0
T2	31258	7350	0	0
T3	5798	5701	0	0
T4	34711	8836	0	0
T5	16866	2435	0	0
T6	741888	1840	0	0
T7	941654	9942	0	0
T8	114631	807378	0	0
T18	46544	29417	0	0
T19	1124	642	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T18,T20
1	1	Covered	T1,T3,T5

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T227,T230,T233
1	1	Covered	T1,T3,T5

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T8,T20

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	715908204	2921	0	0
DisabledNoTrigBkwd_A	715908204	197941	0	0
DisabledNoTrigFwd_A	715908204	420206601	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	2921	0	0
T28	502700	0	0	0
T44	918339	0	0	0
T45	70829	0	0	0
T126	937385	0	0	0
T127	269536	0	0	0
T128	25636	0	0	0
T129	275409	0	0	0
T130	20627	0	0	0
T131	39397	0	0	0
T227	1655	826	0	0
T230	0	271	0	0
T233	0	332	0	0
T236	0	680	0	0
T243	0	812	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	197941	0	0
T8	114631	9	0	0
T9	265758	1	0	0
T10	439795	0	0	0
T11	0	10	0	0
T14	26848	0	0	0
T15	234616	562	0	0
T16	295317	5	0	0
T17	279237	0	0	0
T20	31128	14	0	0
T21	40824	4	0	0
T37	536977	1	0	0
T39	0	9	0	0
T40	0	1	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	420206601	0	0
T1	26147	2299	0	0
T2	31258	27665	0	0
T3	5798	3124	0	0
T4	34711	8836	0	0
T5	16866	2452	0	0
T6	741888	741799	0	0
T7	941654	5994	0	0
T8	114631	2615	0	0
T18	46544	8037	0	0
T19	1124	646	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T6,T18

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T225,T229,T231
1	1	Covered	T1,T6,T18

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T20,T15

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	715908204	4803	0	0
DisabledNoTrigBkwd_A	715908204	171024	0	0
DisabledNoTrigFwd_A	715908204	398697605	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	4803	0	0
T28	502700	0	0	0
T34	253557	0	0	0
T44	918339	0	0	0
T81	78731	0	0	0
T126	937385	0	0	0
T127	269536	0	0	0
T128	25636	0	0	0
T225	4077	538	0	0
T226	3778	0	0	0
T227	1655	0	0	0
T229	0	639	0	0
T231	0	1881	0	0
T235	0	834	0	0
T241	0	233	0	0
T242	0	678	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	171024	0	0
T6	741888	1349	0	0
T7	941654	0	0	0
T8	114631	0	0	0
T9	265758	0	0	0
T10	0	692	0	0
T14	26848	0	0	0
T15	234616	302	0	0
T17	0	2	0	0
T18	46544	0	0	0
T19	1124	0	0	0
T20	31128	12	0	0
T21	40824	39	0	0
T31	0	1	0	0
T32	0	1	0	0
T37	0	992	0	0
T39	0	13	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	398697605	0	0
T1	26147	22480	0	0
T2	31258	29387	0	0
T3	5798	5701	0	0
T4	34711	8836	0	0
T5	16866	2460	0	0
T6	741888	6459	0	0
T7	941654	938681	0	0
T8	114631	613953	0	0
T18	46544	36764	0	0
T19	1124	650	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Covered	T1,T6,T18
1	1	Covered	T3,T6,T18

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T226,T234,T237
1	1	Covered	T3,T6,T18

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	715908204	4069	0	0
DisabledNoTrigBkwd_A	715908204	220268	0	0
DisabledNoTrigFwd_A	715908204	373948578	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	4069	0	0
T28	502700	0	0	0
T44	918339	0	0	0
T45	70829	0	0	0
T126	937385	0	0	0
T127	269536	0	0	0
T128	25636	0	0	0
T129	275409	0	0	0
T130	20627	0	0	0
T226	3778	922	0	0
T227	1655	0	0	0
T234	0	555	0	0
T237	0	1296	0	0
T239	0	1296	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	220268	0	0
T6	741888	1055	0	0
T7	941654	1	0	0
T8	114631	11	0	0
T9	265758	0	0	0
T14	26848	0	0	0
T15	234616	0	0	0
T16	0	7	0	0
T17	0	370	0	0
T18	46544	0	0	0
T19	1124	0	0	0
T20	31128	3	0	0
T21	40824	37	0	0
T39	0	20	0	0
T41	0	93	0	0
T42	0	2759	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	373948578	0	0
T1	26147	26071	0	0
T2	31258	31164	0	0
T3	5798	3174	0	0
T4	34711	8836	0	0
T5	16866	2473	0	0
T6	741888	3612	0	0
T7	941654	936146	0	0
T8	114631	2662	0	0
T18	46544	17992	0	0
T19	1124	654	0	0