Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.72	100.00	93.62		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.56	100.00	97.78		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.56	100.00	97.78		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.63	100.00	97.78	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	44	93.62
Logical	47	44	93.62
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T22
1	1	1	Covered	T2,T5,T6

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T7,T19,T8
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T3,T18

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T18
0	1	Covered	T18,T21,T23
1	0	Covered	T24,T25,T26

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T18
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T24,T25,T26

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T18
1	0	Covered	T25,T27
1	1	Covered	T18,T21,T23

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T6,T7
1	Covered	T2,T18,T19

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T6,T18
1	Covered	T2,T8,T20

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T6,T18
1	Covered	T6,T20,T15

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T6,T18
1	Covered	T6,T21,T10

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T12,T13
1	0	Covered	T4,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T12,T13
1	0	Covered	T2,T6,T19

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T12,T13
1	0	Covered	T2,T6,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T12,T13
1	0	Covered	T2,T6,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T12,T13
1	0	Covered	T2,T19,T8

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T4,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T6,T18
Phase1St	198	Covered	T2,T6,T18
Phase2St	215	Covered	T2,T6,T18
Phase3St	233	Covered	T2,T6,T18
TerminalSt	249	Covered	T2,T6,T18
TimeoutSt	159	Covered	T1,T3,T18

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T4,T12,T13
IdleSt->Phase0St	152	Covered	T2,T6,T7
IdleSt->TimeoutSt	159	Covered	T1,T3,T18
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T2,T25,T28
Phase0St->Phase1St	198	Covered	T2,T6,T18
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T17,T29,T30
Phase1St->Phase2St	215	Covered	T2,T6,T18
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T31,T32,T28
Phase2St->Phase3St	233	Covered	T2,T6,T18
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T25,T33,T34
Phase3St->TerminalSt	249	Covered	T2,T6,T18
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T2,T18,T20
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T1,T3,T18
TimeoutSt->Phase0St	172	Covered	T18,T21,T23

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T5,T6
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T18
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T18,T21,T23
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T18
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T18
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T25,T28
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T6,T18
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T6,T18
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T17,T29,T30
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T6,T18
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T6,T18
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T31,T32,T28
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T6,T18
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T6,T18
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T25,T33,T34
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T6,T18
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T6,T18
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T18,T20
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T6,T18
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T4,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1022	0	0
CheckAccumTrig0_A	2147483647	2256	0	0
CheckAccumTrig1_A	2147483647	102	0	0
CheckClr_A	2147483647	971	0	0
CheckEn_A	2147483647	1242976467	0	0
CheckPhase0_A	2147483647	2576	0	0
CheckPhase1_A	2147483647	2545	0	0
CheckPhase2_A	2147483647	2499	0	0
CheckPhase3_A	2147483647	2452	0	0
CheckTimeout0_A	2147483647	5138	0	0
CheckTimeoutSt1_A	2147483647	631555	0	0
CheckTimeoutSt2_A	2147483647	4775	0	0
CheckTimeoutStTrig_A	2147483647	256	0	0
ErrorStAllEscAsserted_A	2147483647	4802	0	0
ErrorStIsTerminal_A	2147483647	3962	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1022	0	0
T4	138844	297	0	0
T5	67464	0	0	0
T6	2967552	0	0	0
T7	3766616	0	0	0
T8	458524	0	0	0
T12	0	156	0	0
T13	0	122	0	0
T14	107392	0	0	0
T15	938464	0	0	0
T18	186176	0	0	0
T19	4496	0	0	0
T20	124512	0	0	0
T35	0	314	0	0
T36	0	133	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2256	0	0
T2	31258	4	0	0
T3	5798	0	0	0
T4	34711	0	0	0
T5	16866	0	0	0
T6	2225664	3	0	0
T7	2824962	1	0	0
T8	458524	7	0	0
T9	797274	2	0	0
T10	439795	3	0	0
T11	0	1	0	0
T14	80544	0	0	0
T15	703848	3	0	0
T16	295317	4	0	0
T17	279237	3	0	0
T18	139632	0	0	0
T19	3372	1	0	0
T20	124512	5	0	0
T21	122472	4	0	0
T31	0	1	0	0
T32	0	1	0	0
T37	536977	3	0	0
T38	0	1	0	0
T39	0	9	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	11	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	102	0	0
T24	365238	1	0	0
T25	1591240	2	0	0
T26	0	1	0	0
T28	0	2	0	0
T33	323881	0	0	0
T34	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	490365	2	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	1099292	0	0	0
T60	327950	0	0	0
T61	915304	0	0	0
T62	25450	0	0	0
T63	693034	0	0	0
T64	553998	0	0	0
T65	418206	0	0	0
T66	456988	0	0	0
T67	64782	0	0	0
T68	695225	0	0	0
T69	14401	0	0	0
T70	240930	0	0	0
T71	256989	0	0	0
T72	549764	0	0	0
T73	80663	0	0	0
T74	8748	0	0	0
T75	551002	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	971	0	0
T2	31258	3	0	0
T3	5798	0	0	0
T4	34711	0	0	0
T5	16866	0	0	0
T6	741888	0	0	0
T7	941654	0	0	0
T8	114631	0	0	0
T9	531516	0	0	0
T10	879590	1	0	0
T14	26848	0	0	0
T15	469232	1	0	0
T16	590634	1	0	0
T17	558474	2	0	0
T18	46544	1	0	0
T19	1124	0	0	0
T20	62256	1	0	0
T21	81648	2	0	0
T25	0	11	0	0
T26	0	3	0	0
T30	0	1	0	0
T31	807574	1	0	0
T32	0	1	0	0
T33	0	2	0	0
T34	0	2	0	0
T37	1073954	0	0	0
T38	7859	0	0	0
T39	0	2	0	0
T41	0	3	0	0
T42	0	1	0	0
T66	0	1	0	0
T76	0	3	0	0
T77	0	1	0	0
T78	141605	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1242976467	0	0
T1	104588	76918	0	0
T2	125032	94487	0	0
T3	23192	17698	0	0
T4	1352	1044	0	0
T5	67464	9816	0	0
T6	2967552	745934	0	0
T7	3766616	1890761	0	0
T8	458524	1426607	0	0
T18	186176	92208	0	0
T19	4496	2592	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2576	0	0
T2	31258	3	0	0
T3	5798	0	0	0
T4	34711	0	0	0
T5	16866	0	0	0
T6	2225664	3	0	0
T7	2824962	1	0	0
T8	458524	7	0	0
T9	797274	2	0	0
T10	439795	3	0	0
T11	0	1	0	0
T14	80544	0	0	0
T15	703848	3	0	0
T16	295317	4	0	0
T17	279237	3	0	0
T18	139632	1	0	0
T19	3372	1	0	0
T20	124512	5	0	0
T21	122472	5	0	0
T31	0	1	0	0
T32	0	1	0	0
T37	536977	3	0	0
T38	0	1	0	0
T39	0	8	0	0
T40	0	1	0	0
T41	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2545	0	0
T2	31258	3	0	0
T3	5798	0	0	0
T4	34711	0	0	0
T5	16866	0	0	0
T6	2225664	3	0	0
T7	2824962	1	0	0
T8	458524	7	0	0
T9	797274	2	0	0
T10	439795	3	0	0
T11	0	1	0	0
T14	80544	0	0	0
T15	703848	3	0	0
T16	295317	4	0	0
T17	279237	2	0	0
T18	139632	1	0	0
T19	3372	1	0	0
T20	124512	5	0	0
T21	122472	5	0	0
T31	0	1	0	0
T32	0	1	0	0
T37	536977	3	0	0
T38	0	1	0	0
T39	0	8	0	0
T40	0	1	0	0
T41	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2499	0	0
T2	31258	3	0	0
T3	5798	0	0	0
T4	34711	0	0	0
T5	16866	0	0	0
T6	2225664	3	0	0
T7	2824962	1	0	0
T8	458524	6	0	0
T9	797274	2	0	0
T10	439795	3	0	0
T11	0	1	0	0
T14	80544	0	0	0
T15	703848	3	0	0
T16	295317	4	0	0
T17	279237	2	0	0
T18	139632	1	0	0
T19	3372	1	0	0
T20	124512	5	0	0
T21	122472	5	0	0
T32	0	1	0	0
T37	536977	3	0	0
T38	0	1	0	0
T39	0	8	0	0
T40	0	1	0	0
T41	0	1	0	0
T79	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2452	0	0
T2	31258	3	0	0
T3	5798	0	0	0
T4	34711	0	0	0
T5	16866	0	0	0
T6	2225664	3	0	0
T7	2824962	0	0	0
T8	458524	6	0	0
T9	797274	2	0	0
T10	439795	3	0	0
T11	0	1	0	0
T14	80544	0	0	0
T15	703848	3	0	0
T16	295317	4	0	0
T17	279237	2	0	0
T18	139632	1	0	0
T19	3372	1	0	0
T20	124512	5	0	0
T21	122472	5	0	0
T32	0	1	0	0
T37	536977	3	0	0
T38	0	1	0	0
T39	0	8	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	10	0	0
T79	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5138	0	0
T1	26147	3	0	0
T2	31258	0	0	0
T3	11596	2	0	0
T4	69422	0	0	0
T5	33732	0	0	0
T6	1483776	0	0	0
T7	3766616	0	0	0
T8	458524	0	0	0
T9	531516	0	0	0
T10	879590	0	0	0
T14	80544	0	0	0
T15	469232	0	0	0
T16	0	2	0	0
T18	186176	12	0	0
T19	4496	0	0	0
T20	93384	1	0	0
T21	81648	1	0	0
T23	0	21	0	0
T24	0	19	0	0
T25	0	20	0	0
T26	0	1	0	0
T28	0	13	0	0
T33	0	2	0	0
T34	0	7	0	0
T38	0	1	0	0
T39	0	3	0	0
T43	0	1	0	0
T44	0	99	0	0
T59	0	1	0	0
T77	0	1	0	0
T80	0	6	0	0
T81	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	631555	0	0
T1	26147	386	0	0
T2	31258	0	0	0
T3	11596	310	0	0
T4	69422	0	0	0
T5	33732	0	0	0
T6	1483776	0	0	0
T7	3766616	0	0	0
T8	458524	0	0	0
T9	531516	0	0	0
T10	879590	0	0	0
T14	80544	0	0	0
T15	469232	0	0	0
T16	0	93	0	0
T18	186176	1537	0	0
T19	4496	0	0	0
T20	93384	76	0	0
T21	81648	38	0	0
T23	0	1952	0	0
T24	0	1978	0	0
T25	0	3767	0	0
T26	0	7	0	0
T28	0	854	0	0
T33	0	264	0	0
T34	0	1627	0	0
T38	0	53	0	0
T39	0	622	0	0
T43	0	14	0	0
T44	0	16566	0	0
T59	0	172	0	0
T77	0	62	0	0
T80	0	1019	0	0
T81	0	172	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4775	0	0
T1	26147	3	0	0
T2	31258	0	0	0
T3	11596	2	0	0
T4	69422	0	0	0
T5	33732	0	0	0
T6	1483776	0	0	0
T7	3766616	0	0	0
T8	458524	0	0	0
T9	531516	0	0	0
T10	879590	0	0	0
T14	80544	0	0	0
T15	469232	0	0	0
T16	0	2	0	0
T18	186176	11	0	0
T19	4496	0	0	0
T20	93384	1	0	0
T21	81648	0	0	0
T23	0	19	0	0
T24	0	17	0	0
T25	0	15	0	0
T28	0	13	0	0
T33	0	2	0	0
T34	0	6	0	0
T38	0	1	0	0
T39	0	3	0	0
T44	0	106	0	0
T46	0	1	0	0
T47	0	1	0	0
T59	0	1	0	0
T77	0	1	0	0
T80	0	5	0	0
T82	0	8	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	256	0	0
T7	941654	0	0	0
T8	114631	0	0	0
T9	531516	0	0	0
T10	879590	0	0	0
T14	26848	0	0	0
T15	234616	0	0	0
T16	295317	0	0	0
T17	279237	0	0	0
T18	46544	1	0	0
T19	1124	0	0	0
T20	31128	0	0	0
T21	81648	1	0	0
T23	117396	2	0	0
T24	365238	1	0	0
T25	795620	3	0	0
T28	0	4	0	0
T31	403787	0	0	0
T34	0	2	0	0
T37	536977	0	0	0
T38	7859	0	0	0
T39	64795	0	0	0
T44	0	2	0	0
T46	0	1	0	0
T48	0	2	0	0
T75	0	1	0	0
T78	141605	0	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	5	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	2	0	0
T87	0	2	0	0
T88	0	1	0	0
T89	0	1	0	0
T90	17384	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4802	0	0
T4	138844	1346	0	0
T5	67464	0	0	0
T6	2967552	0	0	0
T7	3766616	0	0	0
T8	458524	0	0	0
T12	0	680	0	0
T13	0	723	0	0
T14	107392	0	0	0
T15	938464	0	0	0
T18	186176	0	0	0
T19	4496	0	0	0
T20	124512	0	0	0
T35	0	1387	0	0
T36	0	666	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3962	0	0
T4	138844	1106	0	0
T5	67464	0	0	0
T6	2967552	0	0	0
T7	3766616	0	0	0
T8	458524	0	0	0
T12	0	560	0	0
T13	0	603	0	0
T14	107392	0	0	0
T15	938464	0	0	0
T18	186176	0	0	0
T19	4496	0	0	0
T20	124512	0	0	0
T35	0	1147	0	0
T36	0	546	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	104588	104284	0	0
T2	125032	124656	0	0
T3	23192	22804	0	0
T4	356	52	0	0
T5	67464	67028	0	0
T6	2967552	2967196	0	0
T7	3766616	3766216	0	0
T8	458524	458492	0	0
T18	186176	185832	0	0
T19	4496	4272	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	104588	104284	0	0
T2	125032	124656	0	0
T3	23192	22804	0	0
T4	138844	35344	0	0
T5	67464	67028	0	0
T6	2967552	2967196	0	0
T7	3766616	3766216	0	0
T8	458524	458492	0	0
T18	186176	185832	0	0
T19	4496	4272	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T12,T13
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T5,T8,T20

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T7,T8,T15
1	1	0	Covered	T18,T21,T16
1	1	1	Covered	T1,T3,T18

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T18
0	1	Covered	T21,T34,T28
1	0	Covered	T48,T50,T51

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T18
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T48,T50,T51

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T18
1	0	Not Covered
1	1	Covered	T21,T34,T28

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T8,T20,T21
1	Covered	T15,T37,T40

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T15,T21,T16
1	Covered	T8,T20,T9

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T8,T20,T15
1	Covered	T21,T16,T39

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T8,T20,T15
1	Covered	T21,T42,T25

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T12,T13
1	0	Covered	T4,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T12,T13
1	0	Covered	T15,T21,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T12,T13
1	0	Covered	T20,T21,T37

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T12,T13
1	0	Covered	T8,T20,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T12,T13
1	0	Covered	T8,T20,T21

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T4,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T8,T20,T15
Phase1St	198	Covered	T8,T20,T15
Phase2St	215	Covered	T8,T20,T15
Phase3St	233	Covered	T8,T20,T15
TerminalSt	249	Covered	T8,T20,T15
TimeoutSt	159	Covered	T1,T3,T18

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T4,T12,T13
IdleSt->Phase0St	152	Covered	T8,T20,T15
IdleSt->TimeoutSt	159	Covered	T1,T3,T18
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T91,T92,T93
Phase0St->Phase1St	198	Covered	T8,T20,T15
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T94,T95,T96
Phase1St->Phase2St	215	Covered	T8,T20,T15
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T47,T97,T92
Phase2St->Phase3St	233	Covered	T8,T20,T15
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T87,T98,T99
Phase3St->TerminalSt	249	Covered	T8,T20,T15
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T15,T21,T16
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T3,T18
TimeoutSt->Phase0St	172	Covered	T21,T34,T28

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T8,T20
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T18
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T21,T34,T28
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T18
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T18
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T91,T92,T93
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T8,T20,T15
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T8,T20,T15
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T94,T95,T96
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T8,T20,T15
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T8,T20,T15
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T47,T97,T92
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T8,T20,T15
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T8,T15,T21
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T87,T98,T99
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T8,T20,T15
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T8,T20,T15
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T15,T21,T16
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T8,T20,T15
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T4,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	715908204	251	0	0
CheckAccumTrig0_A	715908204	488	0	0
CheckAccumTrig1_A	715908204	10	0	0
CheckClr_A	715908204	196	0	0
CheckEn_A	715743940	332724450	0	0
CheckPhase0_A	715908204	547	0	0
CheckPhase1_A	715908204	542	0	0
CheckPhase2_A	715908204	533	0	0
CheckPhase3_A	715908204	523	0	0
CheckTimeout0_A	715908204	831	0	0
CheckTimeoutSt1_A	715908204	120370	0	0
CheckTimeoutSt2_A	715908204	764	0	0
CheckTimeoutStTrig_A	715908204	57	0	0
ErrorStAllEscAsserted_A	715908204	1134	0	0
ErrorStIsTerminal_A	715908204	924	0	0
EscStateOut_A	715741710	715672057	0	0
u_state_regs_A	715908204	715749050	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	251	0	0
T4	34711	85	0	0
T5	16866	0	0	0
T6	741888	0	0	0
T7	941654	0	0	0
T8	114631	0	0	0
T12	0	44	0	0
T13	0	26	0	0
T14	26848	0	0	0
T15	234616	0	0	0
T18	46544	0	0	0
T19	1124	0	0	0
T20	31128	0	0	0
T35	0	69	0	0
T36	0	27	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	488	0	0
T8	114631	1	0	0
T9	265758	1	0	0
T10	439795	0	0	0
T11	0	1	0	0
T14	26848	0	0	0
T15	234616	2	0	0
T16	295317	2	0	0
T17	279237	0	0	0
T20	31128	1	0	0
T21	40824	1	0	0
T37	536977	1	0	0
T39	0	2	0	0
T40	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	10	0	0
T48	490365	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T67	64782	0	0	0
T68	695225	0	0	0
T69	14401	0	0	0
T70	240930	0	0	0
T71	256989	0	0	0
T72	549764	0	0	0
T73	80663	0	0	0
T74	8748	0	0	0
T75	551002	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	196	0	0
T9	265758	0	0	0
T10	439795	0	0	0
T15	234616	1	0	0
T16	295317	1	0	0
T17	279237	0	0	0
T21	40824	2	0	0
T25	0	2	0	0
T31	403787	0	0	0
T33	0	1	0	0
T34	0	2	0	0
T37	536977	0	0	0
T38	7859	0	0	0
T39	0	2	0	0
T41	0	1	0	0
T42	0	1	0	0
T66	0	1	0	0
T78	141605	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715743940	332724450	0	0
T1	26147	2299	0	0
T2	31258	27664	0	0
T3	5798	3124	0	0
T4	338	261	0	0
T5	16866	2451	0	0
T6	741888	741798	0	0
T7	941654	5994	0	0
T8	114631	2615	0	0
T18	46544	8037	0	0
T19	1124	646	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	547	0	0
T8	114631	1	0	0
T9	265758	1	0	0
T10	439795	0	0	0
T11	0	1	0	0
T14	26848	0	0	0
T15	234616	2	0	0
T16	295317	2	0	0
T17	279237	0	0	0
T20	31128	1	0	0
T21	40824	2	0	0
T37	536977	1	0	0
T39	0	2	0	0
T40	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	542	0	0
T8	114631	1	0	0
T9	265758	1	0	0
T10	439795	0	0	0
T11	0	1	0	0
T14	26848	0	0	0
T15	234616	2	0	0
T16	295317	2	0	0
T17	279237	0	0	0
T20	31128	1	0	0
T21	40824	2	0	0
T37	536977	1	0	0
T39	0	2	0	0
T40	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	533	0	0
T8	114631	1	0	0
T9	265758	1	0	0
T10	439795	0	0	0
T11	0	1	0	0
T14	26848	0	0	0
T15	234616	2	0	0
T16	295317	2	0	0
T17	279237	0	0	0
T20	31128	1	0	0
T21	40824	2	0	0
T37	536977	1	0	0
T39	0	2	0	0
T40	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	523	0	0
T8	114631	1	0	0
T9	265758	1	0	0
T10	439795	0	0	0
T11	0	1	0	0
T14	26848	0	0	0
T15	234616	2	0	0
T16	295317	2	0	0
T17	279237	0	0	0
T20	31128	1	0	0
T21	40824	2	0	0
T37	536977	1	0	0
T39	0	2	0	0
T40	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	831	0	0
T1	26147	3	0	0
T2	31258	0	0	0
T3	5798	1	0	0
T4	34711	0	0	0
T5	16866	0	0	0
T6	741888	0	0	0
T7	941654	0	0	0
T8	114631	0	0	0
T18	46544	3	0	0
T19	1124	0	0	0
T21	0	1	0	0
T25	0	4	0	0
T34	0	6	0	0
T39	0	3	0	0
T44	0	15	0	0
T59	0	1	0	0
T80	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	120370	0	0
T1	26147	386	0	0
T2	31258	0	0	0
T3	5798	155	0	0
T4	34711	0	0	0
T5	16866	0	0	0
T6	741888	0	0	0
T7	941654	0	0	0
T8	114631	0	0	0
T18	46544	410	0	0
T19	1124	0	0	0
T21	0	38	0	0
T25	0	995	0	0
T34	0	1525	0	0
T39	0	622	0	0
T44	0	2420	0	0
T59	0	172	0	0
T80	0	387	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	764	0	0
T1	26147	3	0	0
T2	31258	0	0	0
T3	5798	1	0	0
T4	34711	0	0	0
T5	16866	0	0	0
T6	741888	0	0	0
T7	941654	0	0	0
T8	114631	0	0	0
T18	46544	3	0	0
T19	1124	0	0	0
T25	0	4	0	0
T28	0	3	0	0
T34	0	5	0	0
T39	0	3	0	0
T44	0	15	0	0
T59	0	1	0	0
T80	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	57	0	0
T9	265758	0	0	0
T10	439795	0	0	0
T16	295317	0	0	0
T17	279237	0	0	0
T21	40824	1	0	0
T28	0	2	0	0
T31	403787	0	0	0
T34	0	1	0	0
T37	536977	0	0	0
T38	7859	0	0	0
T39	64795	0	0	0
T46	0	1	0	0
T48	0	1	0	0
T75	0	1	0	0
T78	141605	0	0	0
T82	0	2	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	1134	0	0
T4	34711	300	0	0
T5	16866	0	0	0
T6	741888	0	0	0
T7	941654	0	0	0
T8	114631	0	0	0
T12	0	183	0	0
T13	0	166	0	0
T14	26848	0	0	0
T15	234616	0	0	0
T18	46544	0	0	0
T19	1124	0	0	0
T20	31128	0	0	0
T35	0	338	0	0
T36	0	147	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	924	0	0
T4	34711	240	0	0
T5	16866	0	0	0
T6	741888	0	0	0
T7	941654	0	0	0
T8	114631	0	0	0
T12	0	153	0	0
T13	0	136	0	0
T14	26848	0	0	0
T15	234616	0	0	0
T18	46544	0	0	0
T19	1124	0	0	0
T20	31128	0	0	0
T35	0	278	0	0
T36	0	117	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715741710	715672057	0	0
T1	26147	26071	0	0
T2	31258	31164	0	0
T3	5798	5701	0	0
T4	89	13	0	0
T5	16866	16757	0	0
T6	741888	741799	0	0
T7	941654	941554	0	0
T8	114631	114623	0	0
T18	46544	46458	0	0
T19	1124	1068	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	715749050	0	0
T1	26147	26071	0	0
T2	31258	31164	0	0
T3	5798	5701	0	0
T4	34711	8836	0	0
T5	16866	16757	0	0
T6	741888	741799	0	0
T7	941654	941554	0	0
T8	114631	114623	0	0
T18	46544	46458	0	0
T19	1124	1068	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T12,T13
1	0	Covered	T3,T6,T18
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T6,T18

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T5,T6
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T6,T7,T8

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T18,T20
1	0	1	Covered	T9,T17,T37
1	1	0	Covered	T1,T18,T16
1	1	1	Covered	T3,T18,T20

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T18,T20
0	1	Covered	T44,T28,T82
1	0	Covered	T46,T82,T100

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T18,T20
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T46,T82,T100

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T18,T20
1	0	Not Covered
1	1	Covered	T44,T28,T82

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T17,T29,T101

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T7,T20,T21
1	Covered	T6,T8,T25

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T16,T39,T102

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T6,T8,T16
1	Covered	T7,T20,T21

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T12,T13
1	0	Covered	T4,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T12,T13
1	0	Covered	T6,T8,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T12,T13
1	0	Covered	T7,T8,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T12,T13
1	0	Covered	T6,T8,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T12,T13
1	0	Covered	T6,T20,T21

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T4,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T6,T7,T8
Phase1St	198	Covered	T6,T7,T8
Phase2St	215	Covered	T6,T7,T8
Phase3St	233	Covered	T6,T7,T8
TerminalSt	249	Covered	T6,T8,T20
TimeoutSt	159	Covered	T3,T18,T20

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T4,T12,T13
IdleSt->Phase0St	152	Covered	T6,T7,T8
IdleSt->TimeoutSt	159	Covered	T3,T18,T20
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T92,T103,T104
Phase0St->Phase1St	198	Covered	T6,T7,T8
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T29,T105,T99
Phase1St->Phase2St	215	Covered	T6,T7,T8
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T8,T42,T29
Phase2St->Phase3St	233	Covered	T6,T7,T8
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T7,T47,T106
Phase3St->TerminalSt	249	Covered	T6,T8,T20
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T8,T20,T16
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T3,T18,T20
TimeoutSt->Phase0St	172	Covered	T44,T28,T46

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T7,T8
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T18,T20
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T44,T28,T46
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T18,T20
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T18,T20
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T92,T103,T107
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T6,T7,T8
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T6,T7,T8
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T29,T105,T99
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T6,T7,T8
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T6,T7,T8
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T8,T42,T29
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T6,T7,T8
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T6,T7,T8
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T7,T47,T106
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T6,T8,T20
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T6,T7,T8
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T8,T20,T16
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T6,T8,T20
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T4,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	715908204	252	0	0
CheckAccumTrig0_A	715908204	537	0	0
CheckAccumTrig1_A	715908204	24	0	0
CheckClr_A	715908204	234	0	0
CheckEn_A	715743940	300752494	0	0
CheckPhase0_A	715908204	613	0	0
CheckPhase1_A	715908204	606	0	0
CheckPhase2_A	715908204	589	0	0
CheckPhase3_A	715908204	578	0	0
CheckTimeout0_A	715908204	1571	0	0
CheckTimeoutSt1_A	715908204	190744	0	0
CheckTimeoutSt2_A	715908204	1489	0	0
CheckTimeoutStTrig_A	715908204	56	0	0
ErrorStAllEscAsserted_A	715908204	1221	0	0
ErrorStIsTerminal_A	715908204	1011	0	0
EscStateOut_A	715741710	715672057	0	0
u_state_regs_A	715908204	715749050	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	252	0	0
T4	34711	61	0	0
T5	16866	0	0	0
T6	741888	0	0	0
T7	941654	0	0	0
T8	114631	0	0	0
T12	0	37	0	0
T13	0	39	0	0
T14	26848	0	0	0
T15	234616	0	0	0
T18	46544	0	0	0
T19	1124	0	0	0
T20	31128	0	0	0
T35	0	82	0	0
T36	0	33	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	537	0	0
T6	741888	1	0	0
T7	941654	1	0	0
T8	114631	6	0	0
T9	265758	0	0	0
T14	26848	0	0	0
T15	234616	0	0	0
T16	0	1	0	0
T17	0	1	0	0
T18	46544	0	0	0
T19	1124	0	0	0
T20	31128	2	0	0
T21	40824	1	0	0
T39	0	5	0	0
T41	0	1	0	0
T42	0	11	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	24	0	0
T46	119403	1	0	0
T82	0	1	0	0
T99	0	1	0	0
T100	0	1	0	0
T108	0	1	0	0
T109	0	1	0	0
T110	0	1	0	0
T111	0	1	0	0
T112	0	3	0	0
T113	0	1	0	0
T114	183186	0	0	0
T115	144748	0	0	0
T116	261476	0	0	0
T117	36850	0	0	0
T118	326747	0	0	0
T119	24125	0	0	0
T120	35992	0	0	0
T121	109779	0	0	0
T122	209075	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	234	0	0
T7	941654	1	0	0
T8	114631	5	0	0
T9	265758	0	0	0
T10	439795	0	0	0
T14	26848	0	0	0
T15	234616	0	0	0
T16	295317	1	0	0
T19	1124	0	0	0
T20	31128	1	0	0
T21	40824	0	0	0
T29	0	2	0	0
T34	0	3	0	0
T39	0	4	0	0
T41	0	1	0	0
T42	0	10	0	0
T80	0	4	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715743940	300752494	0	0
T1	26147	26070	0	0
T2	31258	31163	0	0
T3	5798	3174	0	0
T4	338	261	0	0
T5	16866	2472	0	0
T6	741888	594	0	0
T7	941654	936145	0	0
T8	114631	2662	0	0
T18	46544	17992	0	0
T19	1124	654	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	613	0	0
T6	741888	1	0	0
T7	941654	1	0	0
T8	114631	6	0	0
T9	265758	0	0	0
T14	26848	0	0	0
T15	234616	0	0	0
T16	0	1	0	0
T17	0	1	0	0
T18	46544	0	0	0
T19	1124	0	0	0
T20	31128	2	0	0
T21	40824	1	0	0
T39	0	5	0	0
T41	0	1	0	0
T42	0	11	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	606	0	0
T6	741888	1	0	0
T7	941654	1	0	0
T8	114631	6	0	0
T9	265758	0	0	0
T14	26848	0	0	0
T15	234616	0	0	0
T16	0	1	0	0
T17	0	1	0	0
T18	46544	0	0	0
T19	1124	0	0	0
T20	31128	2	0	0
T21	40824	1	0	0
T39	0	5	0	0
T41	0	1	0	0
T42	0	11	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	589	0	0
T6	741888	1	0	0
T7	941654	1	0	0
T8	114631	5	0	0
T9	265758	0	0	0
T14	26848	0	0	0
T15	234616	0	0	0
T16	0	1	0	0
T17	0	1	0	0
T18	46544	0	0	0
T19	1124	0	0	0
T20	31128	2	0	0
T21	40824	1	0	0
T39	0	5	0	0
T41	0	1	0	0
T42	0	10	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	578	0	0
T6	741888	1	0	0
T7	941654	0	0	0
T8	114631	5	0	0
T9	265758	0	0	0
T14	26848	0	0	0
T15	234616	0	0	0
T16	0	1	0	0
T17	0	1	0	0
T18	46544	0	0	0
T19	1124	0	0	0
T20	31128	2	0	0
T21	40824	1	0	0
T39	0	5	0	0
T41	0	1	0	0
T42	0	10	0	0
T102	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	1571	0	0
T3	5798	1	0	0
T4	34711	0	0	0
T5	16866	0	0	0
T6	741888	0	0	0
T7	941654	0	0	0
T8	114631	0	0	0
T14	26848	0	0	0
T16	0	1	0	0
T18	46544	4	0	0
T19	1124	0	0	0
T20	31128	1	0	0
T23	0	7	0	0
T24	0	2	0	0
T25	0	3	0	0
T33	0	1	0	0
T44	0	65	0	0
T80	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	190744	0	0
T3	5798	155	0	0
T4	34711	0	0	0
T5	16866	0	0	0
T6	741888	0	0	0
T7	941654	0	0	0
T8	114631	0	0	0
T14	26848	0	0	0
T16	0	47	0	0
T18	46544	527	0	0
T19	1124	0	0	0
T20	31128	76	0	0
T23	0	629	0	0
T24	0	110	0	0
T25	0	369	0	0
T33	0	134	0	0
T44	0	10815	0	0
T80	0	197	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	1489	0	0
T3	5798	1	0	0
T4	34711	0	0	0
T5	16866	0	0	0
T6	741888	0	0	0
T7	941654	0	0	0
T8	114631	0	0	0
T14	26848	0	0	0
T16	0	1	0	0
T18	46544	4	0	0
T19	1124	0	0	0
T20	31128	1	0	0
T23	0	7	0	0
T24	0	2	0	0
T25	0	3	0	0
T33	0	1	0	0
T44	0	64	0	0
T80	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	56	0	0
T28	502700	2	0	0
T44	918339	1	0	0
T45	70829	0	0	0
T48	0	1	0	0
T67	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T86	0	1	0	0
T123	0	1	0	0
T124	0	1	0	0
T125	0	2	0	0
T126	937385	0	0	0
T127	269536	0	0	0
T128	25636	0	0	0
T129	275409	0	0	0
T130	20627	0	0	0
T131	39397	0	0	0
T132	472155	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	1221	0	0
T4	34711	355	0	0
T5	16866	0	0	0
T6	741888	0	0	0
T7	941654	0	0	0
T8	114631	0	0	0
T12	0	178	0	0
T13	0	174	0	0
T14	26848	0	0	0
T15	234616	0	0	0
T18	46544	0	0	0
T19	1124	0	0	0
T20	31128	0	0	0
T35	0	336	0	0
T36	0	178	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	1011	0	0
T4	34711	295	0	0
T5	16866	0	0	0
T6	741888	0	0	0
T7	941654	0	0	0
T8	114631	0	0	0
T12	0	148	0	0
T13	0	144	0	0
T14	26848	0	0	0
T15	234616	0	0	0
T18	46544	0	0	0
T19	1124	0	0	0
T20	31128	0	0	0
T35	0	276	0	0
T36	0	148	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715741710	715672057	0	0
T1	26147	26071	0	0
T2	31258	31164	0	0
T3	5798	5701	0	0
T4	89	13	0	0
T5	16866	16757	0	0
T6	741888	741799	0	0
T7	941654	941554	0	0
T8	114631	114623	0	0
T18	46544	46458	0	0
T19	1124	1068	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	715749050	0	0
T1	26147	26071	0	0
T2	31258	31164	0	0
T3	5798	5701	0	0
T4	34711	8836	0	0
T5	16866	16757	0	0
T6	741888	741799	0	0
T7	941654	941554	0	0
T8	114631	114623	0	0
T18	46544	46458	0	0
T19	1124	1068	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T12,T13
1	0	Covered	T6,T18,T20
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T6,T18,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T18,T20

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T6,T20,T15

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T18
1	0	1	Covered	T15,T10,T37
1	1	0	Covered	T1,T18,T20
1	1	1	Covered	T18,T23,T24

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T18,T23,T24
0	1	Covered	T23,T80,T34
1	0	Covered	T25,T44,T28

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T18,T23,T24
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T25,T44,T28

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T23,T24
1	0	Covered	T25
1	1	Covered	T23,T80,T34

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T6,T20,T15
1	Covered	T17,T79,T29

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T6,T20,T15
1	Covered	T21,T17,T31

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T6,T21,T10
1	Covered	T20,T15,T32

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T20,T15,T21
1	Covered	T6,T10,T37

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T12,T13
1	0	Covered	T4,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T12,T13
1	0	Covered	T20,T15,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T12,T13
1	0	Covered	T6,T15,T21

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T12,T13
1	0	Covered	T6,T20,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T12,T13
1	0	Covered	T10,T37,T39

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T4,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T6,T20,T15
Phase1St	198	Covered	T6,T20,T15
Phase2St	215	Covered	T6,T20,T15
Phase3St	233	Covered	T6,T20,T15
TerminalSt	249	Covered	T6,T20,T15
TimeoutSt	159	Covered	T18,T23,T24

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T4,T12,T13
IdleSt->Phase0St	152	Covered	T6,T20,T15
IdleSt->TimeoutSt	159	Covered	T18,T23,T24
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T133,T86,T134
Phase0St->Phase1St	198	Covered	T6,T20,T15
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T17,T135,T136
Phase1St->Phase2St	215	Covered	T6,T20,T15
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T31,T86,T137
Phase2St->Phase3St	233	Covered	T6,T20,T15
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T25,T33,T95
Phase3St->TerminalSt	249	Covered	T6,T20,T15
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T20,T17,T41
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T18,T23,T24
TimeoutSt->Phase0St	172	Covered	T23,T25,T80

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T20,T15
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T23,T24
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T23,T25,T80
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T18,T23,T24
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T18,T23,T24
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T133,T134,T138
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T6,T20,T15
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T6,T20,T15
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T17,T135,T136
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T6,T20,T15
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T6,T20,T15
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T31,T86,T137
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T6,T20,T15
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T6,T20,T15
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T25,T33,T95
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T6,T20,T15
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T6,T20,T15
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T20,T17,T41
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T6,T20,T15
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T4,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	715908204	276	0	0
CheckAccumTrig0_A	715908204	477	0	0
CheckAccumTrig1_A	715908204	23	0	0
CheckClr_A	715908204	212	0	0
CheckEn_A	715743940	329342459	0	0
CheckPhase0_A	715908204	569	0	0
CheckPhase1_A	715908204	563	0	0
CheckPhase2_A	715908204	557	0	0
CheckPhase3_A	715908204	548	0	0
CheckTimeout0_A	715908204	1167	0	0
CheckTimeoutSt1_A	715908204	143004	0	0
CheckTimeoutSt2_A	715908204	1066	0	0
CheckTimeoutStTrig_A	715908204	77	0	0
ErrorStAllEscAsserted_A	715908204	1239	0	0
ErrorStIsTerminal_A	715908204	1029	0	0
EscStateOut_A	715741710	715672057	0	0
u_state_regs_A	715908204	715749050	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	276	0	0
T4	34711	72	0	0
T5	16866	0	0	0
T6	741888	0	0	0
T7	941654	0	0	0
T8	114631	0	0	0
T12	0	47	0	0
T13	0	47	0	0
T14	26848	0	0	0
T15	234616	0	0	0
T18	46544	0	0	0
T19	1124	0	0	0
T20	31128	0	0	0
T35	0	78	0	0
T36	0	32	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	477	0	0
T6	741888	1	0	0
T7	941654	0	0	0
T8	114631	0	0	0
T9	265758	0	0	0
T10	0	1	0	0
T14	26848	0	0	0
T15	234616	1	0	0
T17	0	2	0	0
T18	46544	0	0	0
T19	1124	0	0	0
T20	31128	2	0	0
T21	40824	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T37	0	1	0	0
T39	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	23	0	0
T25	795620	1	0	0
T28	0	2	0	0
T33	323881	0	0	0
T44	0	1	0	0
T48	0	1	0	0
T59	549646	0	0	0
T60	163975	0	0	0
T61	457652	0	0	0
T62	12725	0	0	0
T63	346517	0	0	0
T64	276999	0	0	0
T65	209103	0	0	0
T66	228494	0	0	0
T82	0	1	0	0
T86	0	1	0	0
T134	0	1	0	0
T139	0	2	0	0
T140	0	1	0	0
T141	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	212	0	0
T9	265758	0	0	0
T10	439795	0	0	0
T14	26848	0	0	0
T15	234616	0	0	0
T16	295317	0	0	0
T17	279237	2	0	0
T20	31128	1	0	0
T21	40824	0	0	0
T23	0	1	0	0
T25	0	5	0	0
T31	403787	1	0	0
T33	0	1	0	0
T37	536977	0	0	0
T41	0	1	0	0
T76	0	2	0	0
T142	0	1	0	0
T143	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715743940	329342459	0	0
T1	26147	22479	0	0
T2	31258	29386	0	0
T3	5798	5700	0	0
T4	338	261	0	0
T5	16866	2459	0	0
T6	741888	2960	0	0
T7	941654	938680	0	0
T8	114631	613953	0	0
T18	46544	36763	0	0
T19	1124	650	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	569	0	0
T6	741888	1	0	0
T7	941654	0	0	0
T8	114631	0	0	0
T9	265758	0	0	0
T10	0	1	0	0
T14	26848	0	0	0
T15	234616	1	0	0
T17	0	2	0	0
T18	46544	0	0	0
T19	1124	0	0	0
T20	31128	2	0	0
T21	40824	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T37	0	1	0	0
T39	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	563	0	0
T6	741888	1	0	0
T7	941654	0	0	0
T8	114631	0	0	0
T9	265758	0	0	0
T10	0	1	0	0
T14	26848	0	0	0
T15	234616	1	0	0
T17	0	1	0	0
T18	46544	0	0	0
T19	1124	0	0	0
T20	31128	2	0	0
T21	40824	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T37	0	1	0	0
T39	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	557	0	0
T6	741888	1	0	0
T7	941654	0	0	0
T8	114631	0	0	0
T9	265758	0	0	0
T10	0	1	0	0
T14	26848	0	0	0
T15	234616	1	0	0
T17	0	1	0	0
T18	46544	0	0	0
T19	1124	0	0	0
T20	31128	2	0	0
T21	40824	1	0	0
T32	0	1	0	0
T37	0	1	0	0
T39	0	1	0	0
T79	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	548	0	0
T6	741888	1	0	0
T7	941654	0	0	0
T8	114631	0	0	0
T9	265758	0	0	0
T10	0	1	0	0
T14	26848	0	0	0
T15	234616	1	0	0
T17	0	1	0	0
T18	46544	0	0	0
T19	1124	0	0	0
T20	31128	2	0	0
T21	40824	1	0	0
T32	0	1	0	0
T37	0	1	0	0
T39	0	1	0	0
T79	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	1167	0	0
T7	941654	0	0	0
T8	114631	0	0	0
T9	265758	0	0	0
T10	439795	0	0	0
T14	26848	0	0	0
T15	234616	0	0	0
T18	46544	2	0	0
T19	1124	0	0	0
T20	31128	0	0	0
T21	40824	0	0	0
T23	0	5	0	0
T24	0	14	0	0
T25	0	5	0	0
T28	0	13	0	0
T33	0	1	0	0
T34	0	1	0	0
T44	0	19	0	0
T80	0	1	0	0
T81	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	143004	0	0
T7	941654	0	0	0
T8	114631	0	0	0
T9	265758	0	0	0
T10	439795	0	0	0
T14	26848	0	0	0
T15	234616	0	0	0
T18	46544	269	0	0
T19	1124	0	0	0
T20	31128	0	0	0
T21	40824	0	0	0
T23	0	299	0	0
T24	0	1636	0	0
T25	0	867	0	0
T28	0	854	0	0
T33	0	130	0	0
T34	0	102	0	0
T44	0	3331	0	0
T80	0	34	0	0
T81	0	172	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	1066	0	0
T7	941654	0	0	0
T8	114631	0	0	0
T9	265758	0	0	0
T10	439795	0	0	0
T14	26848	0	0	0
T15	234616	0	0	0
T18	46544	2	0	0
T19	1124	0	0	0
T20	31128	0	0	0
T21	40824	0	0	0
T23	0	3	0	0
T24	0	14	0	0
T25	0	4	0	0
T28	0	10	0	0
T33	0	1	0	0
T44	0	17	0	0
T46	0	1	0	0
T47	0	1	0	0
T82	0	8	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	77	0	0
T23	117396	2	0	0
T24	365238	0	0	0
T25	795620	0	0	0
T28	0	1	0	0
T34	0	1	0	0
T44	0	1	0	0
T59	549646	0	0	0
T60	163975	0	0	0
T61	457652	0	0	0
T62	12725	0	0	0
T63	346517	0	0	0
T64	276999	0	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	3	0	0
T90	17384	0	0	0
T116	0	1	0	0
T128	0	1	0	0
T144	0	4	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	1239	0	0
T4	34711	357	0	0
T5	16866	0	0	0
T6	741888	0	0	0
T7	941654	0	0	0
T8	114631	0	0	0
T12	0	175	0	0
T13	0	195	0	0
T14	26848	0	0	0
T15	234616	0	0	0
T18	46544	0	0	0
T19	1124	0	0	0
T20	31128	0	0	0
T35	0	346	0	0
T36	0	166	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	1029	0	0
T4	34711	297	0	0
T5	16866	0	0	0
T6	741888	0	0	0
T7	941654	0	0	0
T8	114631	0	0	0
T12	0	145	0	0
T13	0	165	0	0
T14	26848	0	0	0
T15	234616	0	0	0
T18	46544	0	0	0
T19	1124	0	0	0
T20	31128	0	0	0
T35	0	286	0	0
T36	0	136	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715741710	715672057	0	0
T1	26147	26071	0	0
T2	31258	31164	0	0
T3	5798	5701	0	0
T4	89	13	0	0
T5	16866	16757	0	0
T6	741888	741799	0	0
T7	941654	941554	0	0
T8	114631	114623	0	0
T18	46544	46458	0	0
T19	1124	1068	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	715749050	0	0
T1	26147	26071	0	0
T2	31258	31164	0	0
T3	5798	5701	0	0
T4	34711	8836	0	0
T5	16866	16757	0	0
T6	741888	741799	0	0
T7	941654	941554	0	0
T8	114631	114623	0	0
T18	46544	46458	0	0
T19	1124	1068	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	44	97.78
Logical	45	44	97.78
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T12,T13
1	0	Covered	T2,T6,T18
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T6,T18

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T5,T6
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T22
1	1	1	Covered	T2,T6,T19

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T18,T21
1	0	1	Covered	T19,T8,T10
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T18,T16,T38

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T18,T16,T38
0	1	Covered	T18,T24,T25
1	0	Covered	T24,T25,T26

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T18,T16,T38
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T24,T25,T26

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T16,T38
1	0	Covered	T27
1	1	Covered	T18,T24,T25

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T6,T21
1	Covered	T2,T18,T19

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T6,T18
1	Covered	T2,T10,T11

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T18,T19
1	Covered	T6,T9,T38

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T6,T18
1	Covered	T21,T10,T37

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T12,T13
1	0	Covered	T4,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T12,T13
1	0	Covered	T2,T6,T19

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T12,T13
1	0	Covered	T2,T18,T19

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T12,T13
1	0	Covered	T2,T18,T19

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T12,T13
1	0	Covered	T2,T19,T21

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T4,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T6,T18
Phase1St	198	Covered	T2,T6,T18
Phase2St	215	Covered	T2,T6,T18
Phase3St	233	Covered	T2,T6,T18
TerminalSt	249	Covered	T2,T6,T18
TimeoutSt	159	Covered	T18,T16,T38

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T4,T12,T13
IdleSt->Phase0St	152	Covered	T2,T6,T19
IdleSt->TimeoutSt	159	Covered	T18,T16,T38
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T2,T25,T28
Phase0St->Phase1St	198	Covered	T2,T6,T18
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T30,T43,T49
Phase1St->Phase2St	215	Covered	T2,T6,T18
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T32,T28,T82
Phase2St->Phase3St	233	Covered	T2,T6,T18
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T34,T28,T83
Phase3St->TerminalSt	249	Covered	T2,T6,T18
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T2,T18,T10
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T18,T16,T38
TimeoutSt->Phase0St	172	Covered	T18,T24,T25

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T6,T19
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T16,T38
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T18,T24,T25
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T18,T16,T38
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T18,T16,T38
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T2,T25,T28
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T6,T18
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T6,T18
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T30,T43,T49
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T6,T18
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T6,T18
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T32,T28,T82
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T6,T18
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T6,T18
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T34,T28,T83
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T6,T18
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T6,T18
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T18,T10
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T6,T18
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T4,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	715908204	243	0	0
CheckAccumTrig0_A	715908204	754	0	0
CheckAccumTrig1_A	715908204	45	0	0
CheckClr_A	715908204	329	0	0
CheckEn_A	715743940	280157064	0	0
CheckPhase0_A	715908204	847	0	0
CheckPhase1_A	715908204	834	0	0
CheckPhase2_A	715908204	820	0	0
CheckPhase3_A	715908204	803	0	0
CheckTimeout0_A	715908204	1569	0	0
CheckTimeoutSt1_A	715908204	177437	0	0
CheckTimeoutSt2_A	715908204	1456	0	0
CheckTimeoutStTrig_A	715908204	66	0	0
ErrorStAllEscAsserted_A	715908204	1208	0	0
ErrorStIsTerminal_A	715908204	998	0	0
EscStateOut_A	715741710	715672057	0	0
u_state_regs_A	715908204	715749050	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	243	0	0
T4	34711	79	0	0
T5	16866	0	0	0
T6	741888	0	0	0
T7	941654	0	0	0
T8	114631	0	0	0
T12	0	28	0	0
T13	0	10	0	0
T14	26848	0	0	0
T15	234616	0	0	0
T18	46544	0	0	0
T19	1124	0	0	0
T20	31128	0	0	0
T35	0	85	0	0
T36	0	41	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	754	0	0
T2	31258	4	0	0
T3	5798	0	0	0
T4	34711	0	0	0
T5	16866	0	0	0
T6	741888	1	0	0
T7	941654	0	0	0
T8	114631	0	0	0
T9	0	1	0	0
T10	0	2	0	0
T16	0	1	0	0
T18	46544	0	0	0
T19	1124	1	0	0
T20	31128	0	0	0
T21	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	45	0	0
T24	365238	1	0	0
T25	795620	1	0	0
T26	0	1	0	0
T34	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T49	0	1	0	0
T59	549646	0	0	0
T60	163975	0	0	0
T61	457652	0	0	0
T62	12725	0	0	0
T63	346517	0	0	0
T64	276999	0	0	0
T65	209103	0	0	0
T66	228494	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	329	0	0
T2	31258	3	0	0
T3	5798	0	0	0
T4	34711	0	0	0
T5	16866	0	0	0
T6	741888	0	0	0
T7	941654	0	0	0
T8	114631	0	0	0
T10	0	1	0	0
T18	46544	1	0	0
T19	1124	0	0	0
T20	31128	0	0	0
T25	0	4	0	0
T26	0	3	0	0
T30	0	1	0	0
T32	0	1	0	0
T41	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715743940	280157064	0	0
T1	26147	26070	0	0
T2	31258	6274	0	0
T3	5798	5700	0	0
T4	338	261	0	0
T5	16866	2434	0	0
T6	741888	582	0	0
T7	941654	9942	0	0
T8	114631	807377	0	0
T18	46544	29416	0	0
T19	1124	642	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	847	0	0
T2	31258	3	0	0
T3	5798	0	0	0
T4	34711	0	0	0
T5	16866	0	0	0
T6	741888	1	0	0
T7	941654	0	0	0
T8	114631	0	0	0
T9	0	1	0	0
T10	0	2	0	0
T16	0	1	0	0
T18	46544	1	0	0
T19	1124	1	0	0
T20	31128	0	0	0
T21	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	834	0	0
T2	31258	3	0	0
T3	5798	0	0	0
T4	34711	0	0	0
T5	16866	0	0	0
T6	741888	1	0	0
T7	941654	0	0	0
T8	114631	0	0	0
T9	0	1	0	0
T10	0	2	0	0
T16	0	1	0	0
T18	46544	1	0	0
T19	1124	1	0	0
T20	31128	0	0	0
T21	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	820	0	0
T2	31258	3	0	0
T3	5798	0	0	0
T4	34711	0	0	0
T5	16866	0	0	0
T6	741888	1	0	0
T7	941654	0	0	0
T8	114631	0	0	0
T9	0	1	0	0
T10	0	2	0	0
T16	0	1	0	0
T18	46544	1	0	0
T19	1124	1	0	0
T20	31128	0	0	0
T21	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	803	0	0
T2	31258	3	0	0
T3	5798	0	0	0
T4	34711	0	0	0
T5	16866	0	0	0
T6	741888	1	0	0
T7	941654	0	0	0
T8	114631	0	0	0
T9	0	1	0	0
T10	0	2	0	0
T16	0	1	0	0
T18	46544	1	0	0
T19	1124	1	0	0
T20	31128	0	0	0
T21	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	1569	0	0
T7	941654	0	0	0
T8	114631	0	0	0
T9	265758	0	0	0
T10	439795	0	0	0
T14	26848	0	0	0
T15	234616	0	0	0
T16	0	1	0	0
T18	46544	3	0	0
T19	1124	0	0	0
T20	31128	0	0	0
T21	40824	0	0	0
T23	0	9	0	0
T24	0	3	0	0
T25	0	8	0	0
T26	0	1	0	0
T38	0	1	0	0
T43	0	1	0	0
T77	0	1	0	0
T80	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	177437	0	0
T7	941654	0	0	0
T8	114631	0	0	0
T9	265758	0	0	0
T10	439795	0	0	0
T14	26848	0	0	0
T15	234616	0	0	0
T16	0	46	0	0
T18	46544	331	0	0
T19	1124	0	0	0
T20	31128	0	0	0
T21	40824	0	0	0
T23	0	1024	0	0
T24	0	232	0	0
T25	0	1536	0	0
T26	0	7	0	0
T38	0	53	0	0
T43	0	14	0	0
T77	0	62	0	0
T80	0	401	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	1456	0	0
T7	941654	0	0	0
T8	114631	0	0	0
T9	265758	0	0	0
T10	439795	0	0	0
T14	26848	0	0	0
T15	234616	0	0	0
T16	0	1	0	0
T18	46544	2	0	0
T19	1124	0	0	0
T20	31128	0	0	0
T21	40824	0	0	0
T23	0	9	0	0
T24	0	1	0	0
T25	0	4	0	0
T34	0	1	0	0
T38	0	1	0	0
T44	0	10	0	0
T77	0	1	0	0
T80	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	66	0	0
T7	941654	0	0	0
T8	114631	0	0	0
T9	265758	0	0	0
T10	439795	0	0	0
T14	26848	0	0	0
T15	234616	0	0	0
T18	46544	1	0	0
T19	1124	0	0	0
T20	31128	0	0	0
T21	40824	0	0	0
T24	0	1	0	0
T25	0	3	0	0
T28	0	1	0	0
T44	0	1	0	0
T48	0	1	0	0
T86	0	2	0	0
T87	0	2	0	0
T88	0	1	0	0
T89	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	1208	0	0
T4	34711	334	0	0
T5	16866	0	0	0
T6	741888	0	0	0
T7	941654	0	0	0
T8	114631	0	0	0
T12	0	144	0	0
T13	0	188	0	0
T14	26848	0	0	0
T15	234616	0	0	0
T18	46544	0	0	0
T19	1124	0	0	0
T20	31128	0	0	0
T35	0	367	0	0
T36	0	175	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	998	0	0
T4	34711	274	0	0
T5	16866	0	0	0
T6	741888	0	0	0
T7	941654	0	0	0
T8	114631	0	0	0
T12	0	114	0	0
T13	0	158	0	0
T14	26848	0	0	0
T15	234616	0	0	0
T18	46544	0	0	0
T19	1124	0	0	0
T20	31128	0	0	0
T35	0	307	0	0
T36	0	145	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715741710	715672057	0	0
T1	26147	26071	0	0
T2	31258	31164	0	0
T3	5798	5701	0	0
T4	89	13	0	0
T5	16866	16757	0	0
T6	741888	741799	0	0
T7	941654	941554	0	0
T8	114631	114623	0	0
T18	46544	46458	0	0
T19	1124	1068	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	715908204	715749050	0	0
T1	26147	26071	0	0
T2	31258	31164	0	0
T3	5798	5701	0	0
T4	34711	8836	0	0
T5	16866	16757	0	0
T6	741888	741799	0	0
T7	941654	941554	0	0
T8	114631	114623	0	0
T18	46544	46458	0	0
T19	1124	1068	0	0