Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T97,T226,T227
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T15,T17

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	15207	0	0
DisabledNoTrigBkwd_A	2147483647	897051	0	0
DisabledNoTrigFwd_A	2147483647	1677902545	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15207	0	0
T20	443010	0	0	0
T21	592077	0	0	0
T61	30964	0	0	0
T68	45490	0	0	0
T69	80050	0	0	0
T70	24384	0	0	0
T76	12581	0	0	0
T81	69874	0	0	0
T82	76215	0	0	0
T97	1233	439	0	0
T98	38325	0	0	0
T213	746244	0	0	0
T214	111399	0	0	0
T215	949549	0	0	0
T216	11255	0	0	0
T217	77009	0	0	0
T218	175450	0	0	0
T220	0	486	0	0
T226	0	997	0	0
T227	4733	1543	0	0
T228	0	960	0	0
T229	0	763	0	0
T230	0	545	0	0
T231	935	169	0	0
T232	0	347	0	0
T233	0	624	0	0
T234	0	966	0	0
T235	0	639	0	0
T236	0	688	0	0
T237	0	1098	0	0
T238	0	491	0	0
T239	0	698	0	0
T240	0	1522	0	0
T241	0	1020	0	0
T242	0	531	0	0
T243	0	681	0	0
T244	509041	0	0	0
T245	24869	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	897051	0	0
T1	266532	16	0	0
T2	1036434	0	0	0
T3	2969025	0	0	0
T4	1785736	6	0	0
T5	486216	26	0	0
T6	1898544	459	0	0
T7	215578	4043	0	0
T11	118692	720	0	0
T12	357293	2306	0	0
T13	0	4306	0	0
T14	0	1952	0	0
T15	1201356	684	0	0
T16	405582	0	0	0
T17	138117	7	0	0
T18	91652	7	0	0
T19	302904	719	0	0
T23	0	8669	0	0
T30	54069	82	0	0
T42	0	1115	0	0
T43	0	1569	0	0
T44	0	7	0	0
T45	0	814	0	0
T47	14284	0	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1677902545	0	0
T1	355376	201210	0	0
T2	1381912	694949	0	0
T3	3958700	2959910	0	0
T4	1785736	1210592	0	0
T5	486216	402942	0	0
T6	1898544	988275	0	0
T15	1601808	433570	0	0
T16	540776	528265	0	0
T17	184156	139893	0	0
T18	91652	69443	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T15
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T97,T226,T239
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T15,T17

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	744250956	3154	0	0
DisabledNoTrigBkwd_A	744250956	267906	0	0
DisabledNoTrigFwd_A	744250956	355274864	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	3154	0	0
T20	443010	0	0	0
T21	592077	0	0	0
T68	45490	0	0	0
T69	80050	0	0	0
T70	24384	0	0	0
T76	12581	0	0	0
T81	69874	0	0	0
T82	76215	0	0	0
T97	1233	439	0	0
T98	38325	0	0	0
T226	0	997	0	0
T239	0	698	0	0
T241	0	1020	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	267906	0	0
T1	88844	5	0	0
T2	345478	0	0	0
T3	989675	0	0	0
T4	446434	0	0	0
T5	121554	26	0	0
T6	474636	1	0	0
T7	0	598	0	0
T12	0	7	0	0
T13	0	2206	0	0
T15	400452	295	0	0
T16	135194	0	0	0
T17	46039	7	0	0
T18	22913	0	0	0
T19	0	303	0	0
T30	0	82	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	355274864	0	0
T1	88844	69410	0	0
T2	345478	310353	0	0
T3	989675	582	0	0
T4	446434	376495	0	0
T5	121554	59767	0	0
T6	474636	474070	0	0
T15	400452	14107	0	0
T16	135194	135124	0	0
T17	46039	2055	0	0
T18	22913	22853	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T15
1	1	Covered	T1,T3,T15

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T231,T233,T236
1	1	Covered	T1,T3,T15

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T6,T19

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	744250956	3110	0	0
DisabledNoTrigBkwd_A	744250956	209712	0	0
DisabledNoTrigFwd_A	744250956	439430089	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	3110	0	0
T61	30964	0	0	0
T213	746244	0	0	0
T214	111399	0	0	0
T215	949549	0	0	0
T216	11255	0	0	0
T217	77009	0	0	0
T218	175450	0	0	0
T231	935	169	0	0
T233	0	624	0	0
T236	0	688	0	0
T237	0	1098	0	0
T242	0	531	0	0
T244	509041	0	0	0
T245	24869	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	209712	0	0
T4	446434	6	0	0
T5	121554	0	0	0
T6	474636	2	0	0
T7	215578	306	0	0
T11	118692	375	0	0
T12	357293	2295	0	0
T14	0	1939	0	0
T18	22913	0	0	0
T19	302904	93	0	0
T23	0	6493	0	0
T30	54069	0	0	0
T44	0	7	0	0
T45	0	814	0	0
T47	14284	0	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	439430089	0	0
T1	88844	29609	0	0
T2	345478	37107	0	0
T3	989675	985258	0	0
T4	446434	11233	0	0
T5	121554	105731	0	0
T6	474636	12242	0	0
T15	400452	370545	0	0
T16	135194	122893	0	0
T17	46039	45946	0	0
T18	22913	22853	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T15
1	1	Covered	T1,T15,T18

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T227,T229,T230
1	1	Covered	T1,T15,T18

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T15,T18

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	744250956	5211	0	0
DisabledNoTrigBkwd_A	744250956	208666	0	0
DisabledNoTrigFwd_A	744250956	457195455	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	5211	0	0
T103	450205	0	0	0
T123	64522	0	0	0
T227	4733	1543	0	0
T229	0	763	0	0
T230	0	545	0	0
T232	0	347	0	0
T238	0	491	0	0
T240	0	1522	0	0
T246	129897	0	0	0
T247	250278	0	0	0
T248	203133	0	0	0
T249	19921	0	0	0
T250	612481	0	0	0
T251	670832	0	0	0
T252	25552	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	208666	0	0
T1	88844	1	0	0
T2	345478	0	0	0
T3	989675	0	0	0
T4	446434	0	0	0
T5	121554	0	0	0
T6	474636	456	0	0
T7	0	383	0	0
T12	0	4	0	0
T13	0	6	0	0
T14	0	4	0	0
T15	400452	224	0	0
T16	135194	0	0	0
T17	46039	0	0	0
T18	22913	7	0	0
T19	0	53	0	0
T23	0	1841	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	457195455	0	0
T1	88844	45603	0	0
T2	345478	2092	0	0
T3	989675	984464	0	0
T4	446434	432126	0	0
T5	121554	121548	0	0
T6	474636	27819	0	0
T15	400452	39031	0	0
T16	135194	135124	0	0
T17	46039	45946	0	0
T18	22913	884	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T15,T19

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T228,T220,T234
1	1	Covered	T1,T15,T19

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T15,T19

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	744250956	3732	0	0
DisabledNoTrigBkwd_A	744250956	210767	0	0
DisabledNoTrigFwd_A	744250956	426002137	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	3732	0	0
T10	34056	0	0	0
T101	419412	0	0	0
T220	0	486	0	0
T228	3609	960	0	0
T229	4305	0	0	0
T234	0	966	0	0
T235	0	639	0	0
T243	0	681	0	0
T253	130549	0	0	0
T254	940536	0	0	0
T255	30861	0	0	0
T256	29690	0	0	0
T257	33018	0	0	0
T258	115906	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	210767	0	0
T1	88844	10	0	0
T2	345478	0	0	0
T3	989675	0	0	0
T4	446434	0	0	0
T5	121554	0	0	0
T6	474636	0	0	0
T7	0	2756	0	0
T11	0	345	0	0
T13	0	2094	0	0
T14	0	9	0	0
T15	400452	165	0	0
T16	135194	0	0	0
T17	46039	0	0	0
T18	22913	0	0	0
T19	0	270	0	0
T23	0	335	0	0
T42	0	1115	0	0
T43	0	1569	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	426002137	0	0
T1	88844	56588	0	0
T2	345478	345397	0	0
T3	989675	989606	0	0
T4	446434	390738	0	0
T5	121554	115896	0	0
T6	474636	474144	0	0
T15	400452	9887	0	0
T16	135194	135124	0	0
T17	46039	45946	0	0
T18	22913	22853	0	0