Unified Coverage Report :: Module :: alert_handler_ping_timer

Module : alert_handler_ping_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.46	100.00	97.30		60.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_ping_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_ping_timer	99.46	100.00	97.30		100.00	100.00	100.00

---

Module Instance : tb.dut.u_ping_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.46	100.00	97.30		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.57	100.00	97.44	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_buf_spurious_alert_ping	100.00	100.00
u_prim_buf_spurious_esc_ping	100.00	100.00
u_prim_count_cnt	100.00			100.00
u_prim_count_esc_cnt	100.00			100.00
u_prim_double_lfsr	100.00	100.00	100.00	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_ping_timer

	Line No.	Total	Covered	Percent
TOTAL		62	62	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
ALWAYS	85	3	3	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
ALWAYS	141	4	4	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	233	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	278	1	1	100.00
CONT_ASSIGN	279	1	1	100.00
ALWAYS	331	37	37	100.00
ALWAYS	426	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_ping_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_ping_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
78	1	1
81	1	1
82	1	1
85	1	1
86	1	1
88	1	1
99	1	1
134	1	1
141	1	1
142	1	1
144	1	1
145	1	1
			MISSING_ELSE
152	1	1
156	1	1
196	1	1
233	1	1
234	1	1
264	1	1
265	1	1
268	1	1
278	1	1
279	1	1
331	1	1
332	1	1
333	1	1
334	1	1
335	1	1
336	1	1
338	1	1
339	1	1
341	1	1
346	1	1
347	1	1
348	1	1
			MISSING_ELSE
353	1	1
354	1	1
355	1	1
			MISSING_ELSE
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
369	1	1
			MISSING_ELSE
			MISSING_ELSE
375	1	1
376	1	1
377	1	1
			MISSING_ELSE
384	1	1
385	1	1
386	1	1
387	1	1
388	1	1
389	1	1
390	1	1
			MISSING_ELSE
			MISSING_ELSE
399	1	1
400	1	1
412	1	1
413	1	1
414	1	1
415	1	1
			MISSING_ELSE
426	3	3

---

Cond Coverage for Module : alert_handler_ping_timer

	Total	Covered	Percent
Conditions	37	36	97.30
Logical	37	36	97.30
Non-Logical	0	0
Event	0	0

 LINE       78
 EXPRESSION ((reseed_timer_q > '0) ? ((reseed_timer_q - 1'b1)) : (reseed_en ? ({wait_cyc_mask_i, {ReseedLfsrExtraBits {1'b1}}}) : '0))
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       78
 SUB-EXPRESSION (reseed_en ? ({wait_cyc_mask_i, {ReseedLfsrExtraBits {1'b1}}}) : '0)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       81
 EXPRESSION (reseed_timer_q == '0)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (edn_req_o & edn_ack_i)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       99
 EXPRESSION (reseed_en ? edn_data_i[(alert_pkg::LfsrWidth - 1):0] : '0)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       117
 EXPRESSION (reseed_en || cnt_set)
             ----1----    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       134
 EXPRESSION 
 Number  Term
      1  (lfsr_state[alert_pkg::PING_CNT_DW+:IdDw] >= alert_pkg::NAlerts) ? ((lfsr_state[alert_pkg::PING_CNT_DW+:IdDw] - alert_pkg::NAlerts)) : lfsr_state[alert_pkg::PING_CNT_DW+:IdDw])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       196
 EXPRESSION ((esc_cnt >= 2'((alert_pkg::N_ESC_SEV - 1))) && esc_cnt_en)
             ---------------------1---------------------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       233
 EXPRESSION (cnt == '0)
            -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       234
 EXPRESSION (wait_cnt_set || timeout_cnt_set)
             ------1-----    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       268
 EXPRESSION (wait_cnt_set ? ((wait_cyc & wait_cyc_mask_i)) : ping_timeout_cyc_i)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       365
 EXPRESSION (timer_expired || ((|(alert_ping_ok_i & alert_ping_req_o))) || ((!id_vld)))
             ------1------    --------------------2--------------------    -----3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T2,T3,T4
0	0	1	Covered	T3,T5,T6
0	1	0	Covered	T3,T6,T7
1	0	0	Covered	T2,T4,T5

 LINE       385
 EXPRESSION (timer_expired || ((|(esc_ping_ok_i & esc_ping_req_o))))
             ------1------    ------------------2------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T3,T4,T5
1	0	Covered	T2,T4,T5

 LINE       412
 EXPRESSION (lfsr_err || cnt_error || esc_cnt_error)
             ----1---    ----2----    ------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T8,T9,T10
0	1	0	Covered	T8,T9,T10
1	0	0	Covered	T8,T9,T10

---

FSM Coverage for Module : alert_handler_ping_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	10	6	60.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AlertPingSt	354	Covered	T2,T3,T4
AlertWaitSt	347	Covered	T2,T3,T4
EscPingSt	376	Covered	T2,T3,T4
EscWaitSt	366	Covered	T2,T3,T4
FsmErrorSt	413	Covered	T8,T9,T10
InitSt	345	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AlertPingSt->EscWaitSt	366	Covered	T2,T3,T4
AlertPingSt->FsmErrorSt	413	Not Covered
AlertWaitSt->AlertPingSt	354	Covered	T2,T3,T4
AlertWaitSt->FsmErrorSt	413	Covered	T8,T9,T10
EscPingSt->AlertWaitSt	386	Covered	T2,T3,T4
EscPingSt->FsmErrorSt	413	Not Covered
EscWaitSt->EscPingSt	376	Covered	T2,T3,T4
EscWaitSt->FsmErrorSt	413	Not Covered
InitSt->AlertWaitSt	347	Covered	T2,T3,T4
InitSt->FsmErrorSt	413	Not Covered

---

Branch Coverage for Module : alert_handler_ping_timer

	Line No.	Total	Covered	Percent
Branches		32	32	100.00
TERNARY	78	3	3	100.00
TERNARY	99	2	2	100.00
TERNARY	134	2	2	100.00
TERNARY	268	2	2	100.00
IF	85	2	2	100.00
IF	141	3	3	100.00
CASE	341	14	14	100.00
IF	412	2	2	100.00
IF	426	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_ping_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_ping_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	78	((reseed_timer_q > '0)) ? 
-2-:	78	(reseed_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	99	(reseed_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	134	((lfsr_state[alert_pkg::PING_CNT_DW+:IdDw] >= alert_pkg::NAlerts)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	268	(wait_cnt_set) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	85	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	141	if ((!rst_ni))
-2-:	144	if (cnt_set)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	341	case (state_q)
-2-:	346	if (en_i)
-3-:	353	if (timer_expired)
-4-:	365	if (((timer_expired || (|(alert_ping_ok_i & alert_ping_req_o))) || (!id_vld)))
-5-:	368	if (timer_expired)
-6-:	375	if (timer_expired)
-7-:	385	if ((timer_expired || (|(esc_ping_ok_i & esc_ping_req_o))))
-8-:	389	if (timer_expired)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
InitSt	1	-	-	-	-	-	-	Covered	T2,T3,T4
InitSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
AlertWaitSt	-	1	-	-	-	-	-	Covered	T2,T3,T4
AlertWaitSt	-	0	-	-	-	-	-	Covered	T2,T3,T4
AlertPingSt	-	-	1	1	-	-	-	Covered	T2,T4,T5
AlertPingSt	-	-	1	0	-	-	-	Covered	T3,T5,T6
AlertPingSt	-	-	0	-	-	-	-	Covered	T2,T3,T4
EscWaitSt	-	-	-	-	1	-	-	Covered	T2,T3,T4
EscWaitSt	-	-	-	-	0	-	-	Covered	T2,T3,T4
EscPingSt	-	-	-	-	-	1	1	Covered	T2,T4,T5
EscPingSt	-	-	-	-	-	1	0	Covered	T3,T4,T5
EscPingSt	-	-	-	-	-	0	-	Covered	T2,T3,T4
FsmErrorSt	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	412	if (((lfsr_err || cnt_error) || esc_cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	426	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_ping_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertPingOH_A	744250956	194199	0	0
EscPingOH_A	744250956	124302	0	0
MaxIdDw_A	635	635	0	0
PingOH0_A	744250956	744076518	0	0
WaitCycMaskIsRightAlignedMask_A	744250956	744076518	0	0
WaitCycMaskMin_A	744250956	744076518	0	0
u_state_regs_A	744250956	744076518	0	0

AlertPingOH_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	194199	0	0
T2	345478	470	0	0
T3	989675	12	0	0
T4	446434	1369	0	0
T5	121554	4200	0	0
T6	474636	312	0	0
T7	0	31	0	0
T11	0	317	0	0
T12	0	230	0	0
T13	0	139	0	0
T14	0	76	0	0
T15	400452	0	0	0
T16	135194	0	0	0
T17	46039	0	0	0
T18	22913	0	0	0
T19	302904	0	0	0

EscPingOH_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	124302	0	0
T2	345478	678	0	0
T3	989675	75	0	0
T4	446434	609	0	0
T5	121554	1745	0	0
T6	474636	355	0	0
T7	0	20	0	0
T11	0	85	0	0
T12	0	270	0	0
T13	0	270	0	0
T14	0	85	0	0
T15	400452	0	0	0
T16	135194	0	0	0
T17	46039	0	0	0
T18	22913	0	0	0
T19	302904	0	0	0

MaxIdDw_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	635	635	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

PingOH0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	744076518	0	0
T1	88844	88587	0	0
T2	345478	345397	0	0
T3	989675	989606	0	0
T4	446434	446369	0	0
T5	121554	121548	0	0
T6	474636	474630	0	0
T15	400452	400376	0	0
T16	135194	135124	0	0
T17	46039	45946	0	0
T18	22913	22853	0	0

WaitCycMaskIsRightAlignedMask_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	744076518	0	0
T1	88844	88587	0	0
T2	345478	345397	0	0
T3	989675	989606	0	0
T4	446434	446369	0	0
T5	121554	121548	0	0
T6	474636	474630	0	0
T15	400452	400376	0	0
T16	135194	135124	0	0
T17	46039	45946	0	0
T18	22913	22853	0	0

WaitCycMaskMin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	744076518	0	0
T1	88844	88587	0	0
T2	345478	345397	0	0
T3	989675	989606	0	0
T4	446434	446369	0	0
T5	121554	121548	0	0
T6	474636	474630	0	0
T15	400452	400376	0	0
T16	135194	135124	0	0
T17	46039	45946	0	0
T18	22913	22853	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	744076518	0	0
T1	88844	88587	0	0
T2	345478	345397	0	0
T3	989675	989606	0	0
T4	446434	446369	0	0
T5	121554	121548	0	0
T6	474636	474630	0	0
T15	400452	400376	0	0
T16	135194	135124	0	0
T17	46039	45946	0	0
T18	22913	22853	0	0

Line Coverage for Instance : tb.dut.u_ping_timer

	Line No.	Total	Covered	Percent
TOTAL		62	62	100.00
CONT_ASSIGN	78	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
ALWAYS	85	3	3	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
ALWAYS	141	4	4	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
CONT_ASSIGN	233	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	278	1	1	100.00
CONT_ASSIGN	279	1	1	100.00
ALWAYS	331	37	37	100.00
ALWAYS	426	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_ping_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_ping_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
78	1	1
81	1	1
82	1	1
85	1	1
86	1	1
88	1	1
99	1	1
134	1	1
141	1	1
142	1	1
144	1	1
145	1	1
			MISSING_ELSE
152	1	1
156	1	1
196	1	1
233	1	1
234	1	1
264	1	1
265	1	1
268	1	1
278	1	1
279	1	1
331	1	1
332	1	1
333	1	1
334	1	1
335	1	1
336	1	1
338	1	1
339	1	1
341	1	1
346	1	1
347	1	1
348	1	1
			MISSING_ELSE
353	1	1
354	1	1
355	1	1
			MISSING_ELSE
364	1	1
365	1	1
366	1	1
367	1	1
368	1	1
369	1	1
			MISSING_ELSE
			MISSING_ELSE
375	1	1
376	1	1
377	1	1
			MISSING_ELSE
384	1	1
385	1	1
386	1	1
387	1	1
388	1	1
389	1	1
390	1	1
			MISSING_ELSE
			MISSING_ELSE
399	1	1
400	1	1
412	1	1
413	1	1
414	1	1
415	1	1
			MISSING_ELSE
426	3	3

---

Cond Coverage for Instance : tb.dut.u_ping_timer

	Total	Covered	Percent
Conditions	37	36	97.30
Logical	37	36	97.30
Non-Logical	0	0
Event	0	0

 LINE       78
 EXPRESSION ((reseed_timer_q > '0) ? ((reseed_timer_q - 1'b1)) : (reseed_en ? ({wait_cyc_mask_i, {ReseedLfsrExtraBits {1'b1}}}) : '0))
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       78
 SUB-EXPRESSION (reseed_en ? ({wait_cyc_mask_i, {ReseedLfsrExtraBits {1'b1}}}) : '0)
                 ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       81
 EXPRESSION (reseed_timer_q == '0)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (edn_req_o & edn_ack_i)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       99
 EXPRESSION (reseed_en ? edn_data_i[(alert_pkg::LfsrWidth - 1):0] : '0)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       117
 EXPRESSION (reseed_en || cnt_set)
             ----1----    ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3

 LINE       134
 EXPRESSION 
 Number  Term
      1  (lfsr_state[alert_pkg::PING_CNT_DW+:IdDw] >= alert_pkg::NAlerts) ? ((lfsr_state[alert_pkg::PING_CNT_DW+:IdDw] - alert_pkg::NAlerts)) : lfsr_state[alert_pkg::PING_CNT_DW+:IdDw])

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       196
 EXPRESSION ((esc_cnt >= 2'((alert_pkg::N_ESC_SEV - 1))) && esc_cnt_en)
             ---------------------1---------------------    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       233
 EXPRESSION (cnt == '0)
            -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       234
 EXPRESSION (wait_cnt_set || timeout_cnt_set)
             ------1-----    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       268
 EXPRESSION (wait_cnt_set ? ((wait_cyc & wait_cyc_mask_i)) : ping_timeout_cyc_i)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       365
 EXPRESSION (timer_expired || ((|(alert_ping_ok_i & alert_ping_req_o))) || ((!id_vld)))
             ------1------    --------------------2--------------------    -----3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T2,T3,T4
0	0	1	Covered	T3,T5,T6
0	1	0	Covered	T3,T6,T7
1	0	0	Covered	T2,T4,T5

 LINE       385
 EXPRESSION (timer_expired || ((|(esc_ping_ok_i & esc_ping_req_o))))
             ------1------    ------------------2------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T4
0	1	Covered	T3,T4,T5
1	0	Covered	T2,T4,T5

 LINE       412
 EXPRESSION (lfsr_err || cnt_error || esc_cnt_error)
             ----1---    ----2----    ------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T8,T9,T10
0	1	0	Covered	T8,T9,T10
1	0	0	Covered	T8,T9,T10

---

FSM Coverage for Instance : tb.dut.u_ping_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AlertPingSt	354	Covered	T2,T3,T4
AlertWaitSt	347	Covered	T2,T3,T4
EscPingSt	376	Covered	T2,T3,T4
EscWaitSt	366	Covered	T2,T3,T4
FsmErrorSt	413	Covered	T8,T9,T10
InitSt	345	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
AlertPingSt->EscWaitSt	366	Covered	T2,T3,T4
AlertPingSt->FsmErrorSt	413	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
AlertWaitSt->AlertPingSt	354	Covered	T2,T3,T4
AlertWaitSt->FsmErrorSt	413	Covered	T8,T9,T10
EscPingSt->AlertWaitSt	386	Covered	T2,T3,T4
EscPingSt->FsmErrorSt	413	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
EscWaitSt->EscPingSt	376	Covered	T2,T3,T4
EscWaitSt->FsmErrorSt	413	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
InitSt->AlertWaitSt	347	Covered	T2,T3,T4
InitSt->FsmErrorSt	413	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.

---

Branch Coverage for Instance : tb.dut.u_ping_timer

	Line No.	Total	Covered	Percent
Branches		32	32	100.00
TERNARY	78	3	3	100.00
TERNARY	99	2	2	100.00
TERNARY	134	2	2	100.00
TERNARY	268	2	2	100.00
IF	85	2	2	100.00
IF	141	3	3	100.00
CASE	341	14	14	100.00
IF	412	2	2	100.00
IF	426	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_ping_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_ping_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	78	((reseed_timer_q > '0)) ? 
-2-:	78	(reseed_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	99	(reseed_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	134	((lfsr_state[alert_pkg::PING_CNT_DW+:IdDw] >= alert_pkg::NAlerts)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	268	(wait_cnt_set) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	85	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	141	if ((!rst_ni))
-2-:	144	if (cnt_set)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	341	case (state_q)
-2-:	346	if (en_i)
-3-:	353	if (timer_expired)
-4-:	365	if (((timer_expired || (|(alert_ping_ok_i & alert_ping_req_o))) || (!id_vld)))
-5-:	368	if (timer_expired)
-6-:	375	if (timer_expired)
-7-:	385	if ((timer_expired || (|(esc_ping_ok_i & esc_ping_req_o))))
-8-:	389	if (timer_expired)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
InitSt	1	-	-	-	-	-	-	Covered	T2,T3,T4
InitSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
AlertWaitSt	-	1	-	-	-	-	-	Covered	T2,T3,T4
AlertWaitSt	-	0	-	-	-	-	-	Covered	T2,T3,T4
AlertPingSt	-	-	1	1	-	-	-	Covered	T2,T4,T5
AlertPingSt	-	-	1	0	-	-	-	Covered	T3,T5,T6
AlertPingSt	-	-	0	-	-	-	-	Covered	T2,T3,T4
EscWaitSt	-	-	-	-	1	-	-	Covered	T2,T3,T4
EscWaitSt	-	-	-	-	0	-	-	Covered	T2,T3,T4
EscPingSt	-	-	-	-	-	1	1	Covered	T2,T4,T5
EscPingSt	-	-	-	-	-	1	0	Covered	T3,T4,T5
EscPingSt	-	-	-	-	-	0	-	Covered	T2,T3,T4
FsmErrorSt	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	412	if (((lfsr_err || cnt_error) || esc_cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	426	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_ping_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertPingOH_A	744250956	194199	0	0
EscPingOH_A	744250956	124302	0	0
MaxIdDw_A	635	635	0	0
PingOH0_A	744250956	744076518	0	0
WaitCycMaskIsRightAlignedMask_A	744250956	744076518	0	0
WaitCycMaskMin_A	744250956	744076518	0	0
u_state_regs_A	744250956	744076518	0	0

AlertPingOH_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	194199	0	0
T2	345478	470	0	0
T3	989675	12	0	0
T4	446434	1369	0	0
T5	121554	4200	0	0
T6	474636	312	0	0
T7	0	31	0	0
T11	0	317	0	0
T12	0	230	0	0
T13	0	139	0	0
T14	0	76	0	0
T15	400452	0	0	0
T16	135194	0	0	0
T17	46039	0	0	0
T18	22913	0	0	0
T19	302904	0	0	0

EscPingOH_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	124302	0	0
T2	345478	678	0	0
T3	989675	75	0	0
T4	446434	609	0	0
T5	121554	1745	0	0
T6	474636	355	0	0
T7	0	20	0	0
T11	0	85	0	0
T12	0	270	0	0
T13	0	270	0	0
T14	0	85	0	0
T15	400452	0	0	0
T16	135194	0	0	0
T17	46039	0	0	0
T18	22913	0	0	0
T19	302904	0	0	0

MaxIdDw_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	635	635	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

PingOH0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	744076518	0	0
T1	88844	88587	0	0
T2	345478	345397	0	0
T3	989675	989606	0	0
T4	446434	446369	0	0
T5	121554	121548	0	0
T6	474636	474630	0	0
T15	400452	400376	0	0
T16	135194	135124	0	0
T17	46039	45946	0	0
T18	22913	22853	0	0

WaitCycMaskIsRightAlignedMask_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	744076518	0	0
T1	88844	88587	0	0
T2	345478	345397	0	0
T3	989675	989606	0	0
T4	446434	446369	0	0
T5	121554	121548	0	0
T6	474636	474630	0	0
T15	400452	400376	0	0
T16	135194	135124	0	0
T17	46039	45946	0	0
T18	22913	22853	0	0

WaitCycMaskMin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	744076518	0	0
T1	88844	88587	0	0
T2	345478	345397	0	0
T3	989675	989606	0	0
T4	446434	446369	0	0
T5	121554	121548	0	0
T6	474636	474630	0	0
T15	400452	400376	0	0
T16	135194	135124	0	0
T17	46039	45946	0	0
T18	22913	22853	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	744076518	0	0
T1	88844	88587	0	0
T2	345478	345397	0	0
T3	989675	989606	0	0
T4	446434	446369	0	0
T5	121554	121548	0	0
T6	474636	474630	0	0
T15	400452	400376	0	0
T16	135194	135124	0	0
T17	46039	45946	0	0
T18	22913	22853	0	0