Module Definition
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Module : prim_alert_receiver
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_alert_0/rtl/prim_alert_receiver.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.gen_alerts[0].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[1].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[2].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[3].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[4].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[5].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[6].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[7].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[8].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[9].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[10].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[11].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[12].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[13].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[14].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[15].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[16].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[17].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[18].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[19].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[20].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[21].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[22].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[23].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[24].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[25].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[26].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[27].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[28].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[29].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[30].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[31].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[32].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[33].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[34].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[35].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[36].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[37].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[38].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[39].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[40].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[41].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[42].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[43].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[44].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[45].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[46].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[47].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[48].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[49].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[50].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[51].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[52].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[53].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[54].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[55].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[56].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[57].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[58].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[59].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[60].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[61].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[62].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[63].u_alert_receiver 100.00 100.00
tb.dut.gen_alerts[64].u_alert_receiver 100.00 100.00



Module Instance : tb.dut.gen_alerts[0].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[1].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[2].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[3].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[4].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[5].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[6].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[7].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[8].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[9].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[10].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[11].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[12].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[13].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[14].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[15].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[16].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[17].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[18].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[19].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[20].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[21].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[22].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[23].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[24].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[25].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[26].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[27].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[28].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[29].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[30].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[31].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[32].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[33].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[34].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[35].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[36].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[37].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[38].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[39].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[40].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[41].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[42].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[43].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[44].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[45].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.gen_alerts[46].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[47].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[48].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.gen_alerts[49].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[50].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.gen_alerts[51].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[52].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.gen_alerts[53].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.gen_alerts[54].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.gen_alerts[55].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.gen_alerts[56].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.gen_alerts[57].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.gen_alerts[58].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[59].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
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Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.gen_alerts[60].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.gen_alerts[61].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[62].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
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Module Instance : tb.dut.gen_alerts[63].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
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Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_alerts[64].u_alert_receiver

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T2,T3,T5 Yes T2,T3,T5 INPUT
ping_ok_o Yes Yes T3,T6,T131 Yes T3,T6,T131 OUTPUT
integ_fail_o Yes Yes T18,T7,T43 Yes T18,T7,T43 OUTPUT
alert_o Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T5,T42 Yes T14,T259,T74 OUTPUT
alert_rx_o.ping_p Yes Yes T14,T259,T74 Yes T2,T5,T42 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T15 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[0].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T3,T131,T118 Yes T3,T131,T118 INPUT
ping_ok_o Yes Yes T3,T131,T259 Yes T3,T131,T259 OUTPUT
integ_fail_o Yes Yes T74,T24,T28 Yes T74,T24,T28 OUTPUT
alert_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T15 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T118,T259,T20 Yes T259,T20,T21 OUTPUT
alert_rx_o.ping_p Yes Yes T259,T20,T21 Yes T118,T259,T20 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T15 INPUT
alert_tx_i.alert_p Yes Yes T1,T15,T16 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[1].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T5,T259,T45 Yes T5,T259,T45 INPUT
ping_ok_o Yes Yes T259,T45,T24 Yes T259,T45,T24 OUTPUT
integ_fail_o Yes Yes T25,T48,T77 Yes T25,T48,T77 OUTPUT
alert_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T15 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T259,T24 Yes T259,T24,T25 OUTPUT
alert_rx_o.ping_p Yes Yes T259,T24,T25 Yes T5,T259,T24 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T15 INPUT
alert_tx_i.alert_p Yes Yes T1,T15,T16 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[2].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T2,T42,T259 Yes T2,T42,T259 INPUT
ping_ok_o Yes Yes T42,T259,T46 Yes T42,T259,T46 OUTPUT
integ_fail_o Yes Yes T18,T7,T43 Yes T18,T7,T43 OUTPUT
alert_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T15 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T42,T259 Yes T259,T74,T25 OUTPUT
alert_rx_o.ping_p Yes Yes T259,T74,T25 Yes T2,T42,T259 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T15 INPUT
alert_tx_i.alert_p Yes Yes T1,T15,T16 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[3].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T131,T259,T46 Yes T131,T259,T46 INPUT
ping_ok_o Yes Yes T131,T259,T46 Yes T131,T259,T46 OUTPUT
integ_fail_o Yes Yes T18,T19,T7 Yes T18,T19,T7 OUTPUT
alert_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T15 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T259,T74,T20 Yes T259,T74,T20 OUTPUT
alert_rx_o.ping_p Yes Yes T259,T74,T20 Yes T259,T74,T20 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T15 INPUT
alert_tx_i.alert_p Yes Yes T1,T15,T16 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[4].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T6,T13,T14 Yes T6,T13,T14 INPUT
ping_ok_o Yes Yes T6,T13,T14 Yes T6,T13,T14 OUTPUT
integ_fail_o Yes Yes T1,T43,T74 Yes T1,T43,T74 OUTPUT
alert_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T15 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T13,T14,T42 Yes T14,T259,T74 OUTPUT
alert_rx_o.ping_p Yes Yes T14,T259,T74 Yes T13,T14,T42 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T15 INPUT
alert_tx_i.alert_p Yes Yes T1,T15,T16 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[5].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T4,T131,T43 Yes T4,T131,T43 INPUT
ping_ok_o Yes Yes T131,T43,T259 Yes T131,T43,T259 OUTPUT
integ_fail_o Yes Yes T18,T43,T24 Yes T18,T43,T24 OUTPUT
alert_o Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
alert_rx_o.ping_n Yes Yes T4,T131,T43 Yes T259,T45,T21 OUTPUT
alert_rx_o.ping_p Yes Yes T259,T45,T21 Yes T4,T131,T43 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T15 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[6].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T12,T14,T43 Yes T12,T14,T43 INPUT
ping_ok_o Yes Yes T12,T14,T43 Yes T12,T14,T43 OUTPUT
integ_fail_o Yes Yes T19,T43,T20 Yes T19,T43,T20 OUTPUT
alert_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T15 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T12,T14,T43 Yes T12,T259,T260 OUTPUT
alert_rx_o.ping_p Yes Yes T12,T259,T260 Yes T12,T14,T43 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T15 INPUT
alert_tx_i.alert_p Yes Yes T1,T15,T16 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[7].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T131,T42,T118 Yes T131,T42,T118 INPUT
ping_ok_o Yes Yes T42,T259,T74 Yes T42,T259,T74 OUTPUT
integ_fail_o Yes Yes T19,T7,T23 Yes T19,T7,T23 OUTPUT
alert_o Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
alert_rx_o.ping_n Yes Yes T131,T42,T118 Yes T131,T42,T259 OUTPUT
alert_rx_o.ping_p Yes Yes T131,T42,T259 Yes T131,T42,T118 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T15 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[8].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T13,T131,T42 Yes T13,T131,T42 INPUT
ping_ok_o Yes Yes T13,T131,T42 Yes T13,T131,T42 OUTPUT
integ_fail_o Yes Yes T7,T23,T24 Yes T7,T23,T24 OUTPUT
alert_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T15 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T13,T131,T42 Yes T259,T74,T20 OUTPUT
alert_rx_o.ping_p Yes Yes T259,T74,T20 Yes T13,T131,T42 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T15 INPUT
alert_tx_i.alert_p Yes Yes T1,T15,T16 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[9].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T6,T7,T42 Yes T6,T7,T42 INPUT
ping_ok_o Yes Yes T6,T7,T42 Yes T6,T7,T42 OUTPUT
integ_fail_o Yes Yes T74,T24,T95 Yes T74,T24,T95 OUTPUT
alert_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T15 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T42,T43 Yes T7,T42,T259 OUTPUT
alert_rx_o.ping_p Yes Yes T7,T42,T259 Yes T7,T42,T43 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T15 INPUT
alert_tx_i.alert_p Yes Yes T1,T15,T16 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[10].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T5,T12,T13 Yes T5,T12,T13 INPUT
ping_ok_o Yes Yes T12,T13,T259 Yes T12,T13,T259 OUTPUT
integ_fail_o Yes Yes T7,T44,T74 Yes T7,T44,T74 OUTPUT
alert_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T15 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T12,T13 Yes T12,T259,T74 OUTPUT
alert_rx_o.ping_p Yes Yes T12,T259,T74 Yes T5,T12,T13 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T15 INPUT
alert_tx_i.alert_p Yes Yes T1,T15,T16 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[11].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T6,T42,T43 Yes T6,T42,T43 INPUT
ping_ok_o Yes Yes T6,T42,T43 Yes T6,T42,T43 OUTPUT
integ_fail_o Yes Yes T19,T7,T23 Yes T19,T7,T23 OUTPUT
alert_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T15 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T42,T43,T259 Yes T42,T259,T20 OUTPUT
alert_rx_o.ping_p Yes Yes T42,T259,T20 Yes T42,T43,T259 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T15 INPUT
alert_tx_i.alert_p Yes Yes T1,T15,T16 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[12].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T5,T259,T46 Yes T5,T259,T46 INPUT
ping_ok_o Yes Yes T259,T46,T20 Yes T259,T46,T20 OUTPUT
integ_fail_o Yes Yes T19,T74,T20 Yes T19,T74,T20 OUTPUT
alert_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T15 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T259,T20 Yes T5,T259,T20 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T259,T20 Yes T5,T259,T20 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T15 INPUT
alert_tx_i.alert_p Yes Yes T1,T15,T16 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[13].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T5,T6,T13 Yes T5,T6,T13 INPUT
ping_ok_o Yes Yes T6,T13,T259 Yes T6,T13,T259 OUTPUT
integ_fail_o Yes Yes T43,T74,T20 Yes T43,T74,T20 OUTPUT
alert_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T15 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T13,T259 Yes T259,T74,T20 OUTPUT
alert_rx_o.ping_p Yes Yes T259,T74,T20 Yes T5,T13,T259 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T15 INPUT
alert_tx_i.alert_p Yes Yes T1,T15,T16 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[14].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T12,T43,T259 Yes T12,T43,T259 INPUT
ping_ok_o Yes Yes T12,T43,T259 Yes T12,T43,T259 OUTPUT
integ_fail_o Yes Yes T18,T44,T74 Yes T18,T44,T74 OUTPUT
alert_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T15 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T12,T43,T259 Yes T259,T21,T260 OUTPUT
alert_rx_o.ping_p Yes Yes T259,T21,T260 Yes T12,T43,T259 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T15 INPUT
alert_tx_i.alert_p Yes Yes T1,T15,T16 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[15].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T5,T7,T12 Yes T5,T7,T12 INPUT
ping_ok_o Yes Yes T7,T12,T13 Yes T7,T12,T13 OUTPUT
integ_fail_o Yes Yes T19,T7,T43 Yes T19,T7,T43 OUTPUT
alert_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T15 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T7,T12 Yes T5,T7,T12 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T7,T12 Yes T5,T7,T12 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T15 INPUT
alert_tx_i.alert_p Yes Yes T1,T15,T16 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[16].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T42,T259,T94 Yes T42,T259,T94 INPUT
ping_ok_o Yes Yes T42,T259,T94 Yes T42,T259,T94 OUTPUT
integ_fail_o Yes Yes T19,T23,T43 Yes T19,T23,T43 OUTPUT
alert_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T15 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T42,T259,T20 Yes T42,T259,T20 OUTPUT
alert_rx_o.ping_p Yes Yes T42,T259,T20 Yes T42,T259,T20 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T15 INPUT
alert_tx_i.alert_p Yes Yes T1,T15,T16 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[17].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T5,T6,T42 Yes T5,T6,T42 INPUT
ping_ok_o Yes Yes T6,T42,T259 Yes T6,T42,T259 OUTPUT
integ_fail_o Yes Yes T1,T18,T19 Yes T1,T18,T19 OUTPUT
alert_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T15 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T42,T259 Yes T42,T259,T74 OUTPUT
alert_rx_o.ping_p Yes Yes T42,T259,T74 Yes T5,T42,T259 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T15 INPUT
alert_tx_i.alert_p Yes Yes T1,T15,T16 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[18].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T3,T13,T259 Yes T3,T13,T259 INPUT
ping_ok_o Yes Yes T3,T13,T259 Yes T3,T13,T259 OUTPUT
integ_fail_o Yes Yes T19,T74,T20 Yes T19,T74,T20 OUTPUT
alert_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T15 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T13,T259,T20 Yes T259,T20,T21 OUTPUT
alert_rx_o.ping_p Yes Yes T259,T20,T21 Yes T13,T259,T20 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T15 INPUT
alert_tx_i.alert_p Yes Yes T1,T15,T16 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[19].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T6,T259,T74 Yes T6,T259,T74 INPUT
ping_ok_o Yes Yes T6,T259,T74 Yes T6,T259,T74 OUTPUT
integ_fail_o Yes Yes T18,T19,T7 Yes T18,T19,T7 OUTPUT
alert_o Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
alert_rx_o.ping_n Yes Yes T259,T74,T25 Yes T259,T74,T25 OUTPUT
alert_rx_o.ping_p Yes Yes T259,T74,T25 Yes T259,T74,T25 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T15 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[20].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T12,T13,T131 Yes T12,T13,T131 INPUT
ping_ok_o Yes Yes T12,T13,T131 Yes T12,T13,T131 OUTPUT
integ_fail_o Yes Yes T19,T7,T44 Yes T19,T7,T44 OUTPUT
alert_o Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
alert_rx_o.ping_n Yes Yes T12,T13,T42 Yes T12,T42,T43 OUTPUT
alert_rx_o.ping_p Yes Yes T12,T42,T43 Yes T12,T13,T42 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T15 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[21].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T6,T11,T42 Yes T6,T11,T42 INPUT
ping_ok_o Yes Yes T6,T42,T259 Yes T6,T42,T259 OUTPUT
integ_fail_o Yes Yes T7,T23,T24 Yes T7,T23,T24 OUTPUT
alert_o Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
alert_rx_o.ping_n Yes Yes T11,T42,T259 Yes T259,T20,T78 OUTPUT
alert_rx_o.ping_p Yes Yes T259,T20,T78 Yes T11,T42,T259 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T15 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[22].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T11,T43,T259 Yes T11,T43,T259 INPUT
ping_ok_o Yes Yes T43,T259,T74 Yes T43,T259,T74 OUTPUT
integ_fail_o Yes Yes T7,T74,T24 Yes T7,T74,T24 OUTPUT
alert_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T15 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T11,T43,T259 Yes T259,T78,T260 OUTPUT
alert_rx_o.ping_p Yes Yes T259,T78,T260 Yes T11,T43,T259 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T15 INPUT
alert_tx_i.alert_p Yes Yes T1,T15,T16 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[23].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T3,T42,T259 Yes T3,T42,T259 INPUT
ping_ok_o Yes Yes T3,T42,T259 Yes T3,T42,T259 OUTPUT
integ_fail_o Yes Yes T18,T7,T23 Yes T18,T7,T23 OUTPUT
alert_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T15 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T42,T259,T74 Yes T42,T259,T74 OUTPUT
alert_rx_o.ping_p Yes Yes T42,T259,T74 Yes T42,T259,T74 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T15 INPUT
alert_tx_i.alert_p Yes Yes T1,T15,T16 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[24].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T12,T259,T46 Yes T12,T259,T46 INPUT
ping_ok_o Yes Yes T12,T259,T46 Yes T12,T259,T46 OUTPUT
integ_fail_o Yes Yes T18,T19,T74 Yes T18,T19,T74 OUTPUT
alert_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T15 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T12,T259,T74 Yes T12,T259,T74 OUTPUT
alert_rx_o.ping_p Yes Yes T12,T259,T74 Yes T12,T259,T74 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T15 INPUT
alert_tx_i.alert_p Yes Yes T1,T15,T16 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[25].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T2,T13,T259 Yes T2,T13,T259 INPUT
ping_ok_o Yes Yes T13,T259,T46 Yes T13,T259,T46 OUTPUT
integ_fail_o Yes Yes T1,T7,T24 Yes T1,T7,T24 OUTPUT
alert_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T15 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T13,T259 Yes T13,T259,T21 OUTPUT
alert_rx_o.ping_p Yes Yes T13,T259,T21 Yes T2,T13,T259 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T15 INPUT
alert_tx_i.alert_p Yes Yes T1,T15,T16 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[26].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T5,T6,T131 Yes T5,T6,T131 INPUT
ping_ok_o Yes Yes T6,T131,T259 Yes T6,T131,T259 OUTPUT
integ_fail_o Yes Yes T18,T23,T43 Yes T18,T23,T43 OUTPUT
alert_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T15 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T259,T74 Yes T259,T20,T260 OUTPUT
alert_rx_o.ping_p Yes Yes T259,T20,T260 Yes T5,T259,T74 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T15 INPUT
alert_tx_i.alert_p Yes Yes T1,T15,T16 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[27].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T11,T12,T43 Yes T11,T12,T43 INPUT
ping_ok_o Yes Yes T11,T12,T43 Yes T11,T12,T43 OUTPUT
integ_fail_o Yes Yes T1,T18,T7 Yes T1,T18,T7 OUTPUT
alert_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T15 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T12,T43,T259 Yes T259,T20,T77 OUTPUT
alert_rx_o.ping_p Yes Yes T259,T20,T77 Yes T12,T43,T259 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T15 INPUT
alert_tx_i.alert_p Yes Yes T1,T15,T16 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[28].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
ping_ok_o Yes Yes T6,T12,T131 Yes T6,T12,T131 OUTPUT
integ_fail_o Yes Yes T74,T24,T95 Yes T74,T24,T95 OUTPUT
alert_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T15 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T4,T5,T6 Yes T12,T259,T20 OUTPUT
alert_rx_o.ping_p Yes Yes T12,T259,T20 Yes T4,T5,T6 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T15 INPUT
alert_tx_i.alert_p Yes Yes T1,T15,T16 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[29].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T131,T259,T74 Yes T131,T259,T74 INPUT
ping_ok_o Yes Yes T131,T259,T74 Yes T131,T259,T74 OUTPUT
integ_fail_o Yes Yes T18,T23,T43 Yes T18,T23,T43 OUTPUT
alert_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T15 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T259,T74,T20 Yes T259,T74,T20 OUTPUT
alert_rx_o.ping_p Yes Yes T259,T74,T20 Yes T259,T74,T20 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T15 INPUT
alert_tx_i.alert_p Yes Yes T1,T15,T16 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[30].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T5,T259,T46 Yes T5,T259,T46 INPUT
ping_ok_o Yes Yes T259,T46,T20 Yes T259,T46,T20 OUTPUT
integ_fail_o Yes Yes T19,T7,T23 Yes T19,T7,T23 OUTPUT
alert_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T15 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T259,T20 Yes T259,T20,T25 OUTPUT
alert_rx_o.ping_p Yes Yes T259,T20,T25 Yes T5,T259,T20 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T15 INPUT
alert_tx_i.alert_p Yes Yes T1,T15,T16 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[31].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T4,T259,T74 Yes T4,T259,T74 INPUT
ping_ok_o Yes Yes T259,T74,T20 Yes T259,T74,T20 OUTPUT
integ_fail_o Yes Yes T19,T43,T20 Yes T19,T43,T20 OUTPUT
alert_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T15 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T4,T259,T74 Yes T259,T74,T20 OUTPUT
alert_rx_o.ping_p Yes Yes T259,T74,T20 Yes T4,T259,T74 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T15 INPUT
alert_tx_i.alert_p Yes Yes T1,T15,T16 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[32].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T14,T42,T259 Yes T14,T42,T259 INPUT
ping_ok_o Yes Yes T14,T42,T259 Yes T14,T42,T259 OUTPUT
integ_fail_o Yes Yes T1,T23,T25 Yes T1,T23,T25 OUTPUT
alert_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T15 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T14,T42,T259 Yes T42,T259,T74 OUTPUT
alert_rx_o.ping_p Yes Yes T42,T259,T74 Yes T14,T42,T259 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T15 INPUT
alert_tx_i.alert_p Yes Yes T1,T15,T16 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[33].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T6,T259,T74 Yes T6,T259,T74 INPUT
ping_ok_o Yes Yes T6,T259,T74 Yes T6,T259,T74 OUTPUT
integ_fail_o Yes Yes T23,T43,T27 Yes T23,T43,T27 OUTPUT
alert_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T15 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T259,T74,T20 Yes T259,T74,T20 OUTPUT
alert_rx_o.ping_p Yes Yes T259,T74,T20 Yes T259,T74,T20 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T15 INPUT
alert_tx_i.alert_p Yes Yes T1,T15,T16 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[34].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T12,T14,T42 Yes T12,T14,T42 INPUT
ping_ok_o Yes Yes T12,T14,T42 Yes T12,T14,T42 OUTPUT
integ_fail_o Yes Yes T7,T43,T20 Yes T7,T43,T20 OUTPUT
alert_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T15 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T12,T14,T42 Yes T12,T259,T74 OUTPUT
alert_rx_o.ping_p Yes Yes T12,T259,T74 Yes T12,T14,T42 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T15 INPUT
alert_tx_i.alert_p Yes Yes T1,T15,T16 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[35].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T2,T12,T259 Yes T2,T12,T259 INPUT
ping_ok_o Yes Yes T12,T259,T46 Yes T12,T259,T46 OUTPUT
integ_fail_o Yes Yes T1,T19,T7 Yes T1,T19,T7 OUTPUT
alert_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T15 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T12,T259 Yes T259,T74,T20 OUTPUT
alert_rx_o.ping_p Yes Yes T259,T74,T20 Yes T2,T12,T259 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T15 INPUT
alert_tx_i.alert_p Yes Yes T1,T15,T16 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[36].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T12,T13,T259 Yes T12,T13,T259 INPUT
ping_ok_o Yes Yes T12,T13,T259 Yes T12,T13,T259 OUTPUT
integ_fail_o Yes Yes T7,T23,T43 Yes T7,T23,T43 OUTPUT
alert_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T15 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T12,T13,T259 Yes T259,T21,T25 OUTPUT
alert_rx_o.ping_p Yes Yes T259,T21,T25 Yes T12,T13,T259 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T15 INPUT
alert_tx_i.alert_p Yes Yes T1,T15,T16 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[37].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T12,T42,T259 Yes T12,T42,T259 INPUT
ping_ok_o Yes Yes T12,T42,T259 Yes T12,T42,T259 OUTPUT
integ_fail_o Yes Yes T7,T23,T43 Yes T7,T23,T43 OUTPUT
alert_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T15 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T12,T42,T259 Yes T12,T42,T259 OUTPUT
alert_rx_o.ping_p Yes Yes T12,T42,T259 Yes T12,T42,T259 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T15 INPUT
alert_tx_i.alert_p Yes Yes T1,T15,T16 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[38].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T6,T14,T259 Yes T6,T14,T259 INPUT
ping_ok_o Yes Yes T6,T14,T259 Yes T6,T14,T259 OUTPUT
integ_fail_o Yes Yes T23,T74,T24 Yes T23,T74,T24 OUTPUT
alert_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T15 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T14,T259,T74 Yes T259,T20,T78 OUTPUT
alert_rx_o.ping_p Yes Yes T259,T20,T78 Yes T14,T259,T74 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T15 INPUT
alert_tx_i.alert_p Yes Yes T1,T15,T16 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[39].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T6,T7,T12 Yes T6,T7,T12 INPUT
ping_ok_o Yes Yes T6,T7,T12 Yes T6,T7,T12 OUTPUT
integ_fail_o Yes Yes T18,T19,T23 Yes T18,T19,T23 OUTPUT
alert_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T15 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T12,T259 Yes T7,T259,T20 OUTPUT
alert_rx_o.ping_p Yes Yes T7,T259,T20 Yes T7,T12,T259 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T15 INPUT
alert_tx_i.alert_p Yes Yes T1,T15,T16 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[40].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T4,T11,T43 Yes T4,T11,T43 INPUT
ping_ok_o Yes Yes T11,T43,T259 Yes T11,T43,T259 OUTPUT
integ_fail_o Yes Yes T18,T7,T23 Yes T18,T7,T23 OUTPUT
alert_o Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
alert_rx_o.ping_n Yes Yes T4,T11,T43 Yes T259,T46,T74 OUTPUT
alert_rx_o.ping_p Yes Yes T259,T46,T74 Yes T4,T11,T43 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T15 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[41].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T3,T4,T13 Yes T3,T4,T13 INPUT
ping_ok_o Yes Yes T3,T13,T42 Yes T3,T13,T42 OUTPUT
integ_fail_o Yes Yes T19,T20,T21 Yes T19,T20,T21 OUTPUT
alert_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T15 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T4,T13,T42 Yes T259,T74,T20 OUTPUT
alert_rx_o.ping_p Yes Yes T259,T74,T20 Yes T4,T13,T42 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T15 INPUT
alert_tx_i.alert_p Yes Yes T1,T15,T16 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[42].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T5,T259,T74 Yes T5,T259,T74 INPUT
ping_ok_o Yes Yes T259,T74,T94 Yes T259,T74,T94 OUTPUT
integ_fail_o Yes Yes T1,T7,T23 Yes T1,T7,T23 OUTPUT
alert_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T15 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T259,T74 Yes T5,T259,T74 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T259,T74 Yes T5,T259,T74 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T15 INPUT
alert_tx_i.alert_p Yes Yes T1,T15,T16 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[43].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T6,T12,T259 Yes T6,T12,T259 INPUT
ping_ok_o Yes Yes T6,T12,T259 Yes T6,T12,T259 OUTPUT
integ_fail_o Yes Yes T1,T44,T24 Yes T1,T44,T24 OUTPUT
alert_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T15 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T6,T12,T259 Yes T259,T20,T25 OUTPUT
alert_rx_o.ping_p Yes Yes T259,T20,T25 Yes T6,T12,T259 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T15 INPUT
alert_tx_i.alert_p Yes Yes T1,T15,T16 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[44].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T6,T131,T42 Yes T6,T131,T42 INPUT
ping_ok_o Yes Yes T131,T42,T43 Yes T131,T42,T43 OUTPUT
integ_fail_o Yes Yes T1,T23,T44 Yes T1,T23,T44 OUTPUT
alert_o Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T3,T15 Yes T1,T3,T15 OUTPUT
alert_rx_o.ping_n Yes Yes T6,T131,T42 Yes T42,T259,T25 OUTPUT
alert_rx_o.ping_p Yes Yes T42,T259,T25 Yes T6,T131,T42 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_tx_i.alert_p Yes Yes T1,T3,T15 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[45].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T42,T259,T74 Yes T42,T259,T74 INPUT
ping_ok_o Yes Yes T42,T259,T74 Yes T42,T259,T74 OUTPUT
integ_fail_o Yes Yes T18,T19,T74 Yes T18,T19,T74 OUTPUT
alert_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T15 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T42,T259,T74 Yes T259,T20,T25 OUTPUT
alert_rx_o.ping_p Yes Yes T259,T20,T25 Yes T42,T259,T74 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T15 INPUT
alert_tx_i.alert_p Yes Yes T1,T15,T16 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[46].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T3,T42,T259 Yes T3,T42,T259 INPUT
ping_ok_o Yes Yes T3,T42,T259 Yes T3,T42,T259 OUTPUT
integ_fail_o Yes Yes T1,T18,T7 Yes T1,T18,T7 OUTPUT
alert_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T15 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T42,T259,T20 Yes T42,T259,T20 OUTPUT
alert_rx_o.ping_p Yes Yes T42,T259,T20 Yes T42,T259,T20 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T15 INPUT
alert_tx_i.alert_p Yes Yes T1,T15,T16 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[47].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T131,T43,T259 Yes T131,T43,T259 INPUT
ping_ok_o Yes Yes T131,T43,T259 Yes T131,T43,T259 OUTPUT
integ_fail_o Yes Yes T19,T7,T43 Yes T19,T7,T43 OUTPUT
alert_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T15 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T43,T259,T74 Yes T259,T20,T25 OUTPUT
alert_rx_o.ping_p Yes Yes T259,T20,T25 Yes T43,T259,T74 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T15 INPUT
alert_tx_i.alert_p Yes Yes T1,T15,T16 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[48].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T6,T7,T12 Yes T6,T7,T12 INPUT
ping_ok_o Yes Yes T6,T7,T12 Yes T6,T7,T12 OUTPUT
integ_fail_o Yes Yes T18,T19,T21 Yes T18,T19,T21 OUTPUT
alert_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T15 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T7,T12,T259 Yes T7,T259,T21 OUTPUT
alert_rx_o.ping_p Yes Yes T7,T259,T21 Yes T7,T12,T259 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T15 INPUT
alert_tx_i.alert_p Yes Yes T1,T15,T16 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[49].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T5,T14,T259 Yes T5,T14,T259 INPUT
ping_ok_o Yes Yes T14,T259,T20 Yes T14,T259,T20 OUTPUT
integ_fail_o Yes Yes T19,T23,T43 Yes T19,T23,T43 OUTPUT
alert_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T15 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T14,T259 Yes T5,T259,T20 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T259,T20 Yes T5,T14,T259 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T15 INPUT
alert_tx_i.alert_p Yes Yes T1,T15,T16 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[50].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T13,T42,T259 Yes T13,T42,T259 INPUT
ping_ok_o Yes Yes T13,T42,T259 Yes T13,T42,T259 OUTPUT
integ_fail_o Yes Yes T1,T44,T74 Yes T1,T44,T74 OUTPUT
alert_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T15 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T13,T42,T259 Yes T13,T259,T74 OUTPUT
alert_rx_o.ping_p Yes Yes T13,T259,T74 Yes T13,T42,T259 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T15 INPUT
alert_tx_i.alert_p Yes Yes T1,T15,T16 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[51].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T259,T74,T94 Yes T259,T74,T94 INPUT
ping_ok_o Yes Yes T259,T74,T94 Yes T259,T74,T94 OUTPUT
integ_fail_o Yes Yes T1,T18,T19 Yes T1,T18,T19 OUTPUT
alert_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T15 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T259,T74,T21 Yes T259,T21,T78 OUTPUT
alert_rx_o.ping_p Yes Yes T259,T21,T78 Yes T259,T74,T21 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T15 INPUT
alert_tx_i.alert_p Yes Yes T1,T15,T16 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[52].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T6,T13,T259 Yes T6,T13,T259 INPUT
ping_ok_o Yes Yes T6,T13,T259 Yes T6,T13,T259 OUTPUT
integ_fail_o Yes Yes T1,T18,T7 Yes T1,T18,T7 OUTPUT
alert_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T15 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T13,T259,T25 Yes T259,T71,T260 OUTPUT
alert_rx_o.ping_p Yes Yes T259,T71,T260 Yes T13,T259,T25 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T15 INPUT
alert_tx_i.alert_p Yes Yes T1,T15,T16 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[53].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T6,T12,T259 Yes T6,T12,T259 INPUT
ping_ok_o Yes Yes T6,T12,T259 Yes T6,T12,T259 OUTPUT
integ_fail_o Yes Yes T23,T20,T48 Yes T23,T20,T48 OUTPUT
alert_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T15 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T12,T259,T74 Yes T259,T21,T260 OUTPUT
alert_rx_o.ping_p Yes Yes T259,T21,T260 Yes T12,T259,T74 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T15 INPUT
alert_tx_i.alert_p Yes Yes T1,T15,T16 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[54].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T5,T13,T42 Yes T5,T13,T42 INPUT
ping_ok_o Yes Yes T13,T42,T43 Yes T13,T42,T43 OUTPUT
integ_fail_o Yes Yes T23,T43,T74 Yes T23,T43,T74 OUTPUT
alert_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T15 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T13,T42 Yes T5,T42,T259 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T42,T259 Yes T5,T13,T42 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T15 INPUT
alert_tx_i.alert_p Yes Yes T1,T15,T16 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[55].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T11,T12,T259 Yes T11,T12,T259 INPUT
ping_ok_o Yes Yes T11,T12,T259 Yes T11,T12,T259 OUTPUT
integ_fail_o Yes Yes T24,T21,T25 Yes T24,T21,T25 OUTPUT
alert_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T15 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T12,T259,T21 Yes T12,T259,T21 OUTPUT
alert_rx_o.ping_p Yes Yes T12,T259,T21 Yes T12,T259,T21 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T15 INPUT
alert_tx_i.alert_p Yes Yes T1,T15,T16 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[56].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T5,T6,T13 Yes T5,T6,T13 INPUT
ping_ok_o Yes Yes T6,T13,T131 Yes T6,T13,T131 OUTPUT
integ_fail_o Yes Yes T18,T44,T74 Yes T18,T44,T74 OUTPUT
alert_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T15 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T13,T259 Yes T5,T13,T259 OUTPUT
alert_rx_o.ping_p Yes Yes T5,T13,T259 Yes T5,T13,T259 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T15 INPUT
alert_tx_i.alert_p Yes Yes T1,T15,T16 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[57].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T11,T13,T14 Yes T11,T13,T14 INPUT
ping_ok_o Yes Yes T11,T13,T14 Yes T11,T13,T14 OUTPUT
integ_fail_o Yes Yes T19,T7,T43 Yes T19,T7,T43 OUTPUT
alert_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T15 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T13,T14,T42 Yes T13,T118,T259 OUTPUT
alert_rx_o.ping_p Yes Yes T13,T118,T259 Yes T13,T14,T42 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T15 INPUT
alert_tx_i.alert_p Yes Yes T1,T15,T16 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[58].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T3,T131,T259 Yes T3,T131,T259 INPUT
ping_ok_o Yes Yes T3,T131,T259 Yes T3,T131,T259 OUTPUT
integ_fail_o Yes Yes T19,T23,T44 Yes T19,T23,T44 OUTPUT
alert_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T15 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T259,T74,T20 Yes T259,T20,T78 OUTPUT
alert_rx_o.ping_p Yes Yes T259,T20,T78 Yes T259,T74,T20 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T15 INPUT
alert_tx_i.alert_p Yes Yes T1,T15,T16 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[59].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T2,T4,T6 Yes T2,T4,T6 INPUT
ping_ok_o Yes Yes T6,T259,T94 Yes T6,T259,T94 OUTPUT
integ_fail_o Yes Yes T19,T7,T23 Yes T19,T7,T23 OUTPUT
alert_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T15 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T4,T259 Yes T259,T21,T78 OUTPUT
alert_rx_o.ping_p Yes Yes T259,T21,T78 Yes T2,T4,T259 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T15 INPUT
alert_tx_i.alert_p Yes Yes T1,T15,T16 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[60].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T6,T12,T14 Yes T6,T12,T14 INPUT
ping_ok_o Yes Yes T6,T12,T14 Yes T6,T12,T14 OUTPUT
integ_fail_o Yes Yes T43,T24,T21 Yes T43,T24,T21 OUTPUT
alert_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T15 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T12,T14,T42 Yes T12,T259,T21 OUTPUT
alert_rx_o.ping_p Yes Yes T12,T259,T21 Yes T12,T14,T42 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T15 INPUT
alert_tx_i.alert_p Yes Yes T1,T15,T16 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[61].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T2,T13,T42 Yes T2,T13,T42 INPUT
ping_ok_o Yes Yes T13,T42,T259 Yes T13,T42,T259 OUTPUT
integ_fail_o Yes Yes T1,T7,T23 Yes T1,T7,T23 OUTPUT
alert_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T15 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T2,T13,T42 Yes T259,T21,T260 OUTPUT
alert_rx_o.ping_p Yes Yes T259,T21,T260 Yes T2,T13,T42 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T15 INPUT
alert_tx_i.alert_p Yes Yes T1,T15,T16 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[62].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T5,T7,T43 Yes T5,T7,T43 INPUT
ping_ok_o Yes Yes T7,T43,T259 Yes T7,T43,T259 OUTPUT
integ_fail_o Yes Yes T74,T95,T20 Yes T74,T95,T20 OUTPUT
alert_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T15 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T5,T7,T43 Yes T7,T259,T24 OUTPUT
alert_rx_o.ping_p Yes Yes T7,T259,T24 Yes T5,T7,T43 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T15 INPUT
alert_tx_i.alert_p Yes Yes T1,T15,T16 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[63].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T13,T42,T259 Yes T13,T42,T259 INPUT
ping_ok_o Yes Yes T13,T42,T259 Yes T13,T42,T259 OUTPUT
integ_fail_o Yes Yes T19,T43,T24 Yes T19,T43,T24 OUTPUT
alert_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T15 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T13,T42,T259 Yes T259,T20,T260 OUTPUT
alert_rx_o.ping_p Yes Yes T259,T20,T260 Yes T13,T42,T259 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T15 INPUT
alert_tx_i.alert_p Yes Yes T1,T15,T16 Yes T1,T3,T15 INPUT

Toggle Coverage for Instance : tb.dut.gen_alerts[64].u_alert_receiver
TotalCoveredPercent
Totals 13 13 100.00
Total Bits 32 32 100.00
Total Bits 0->1 16 16 100.00
Total Bits 1->0 16 16 100.00

Ports 13 13 100.00
Port Bits 32 32 100.00
Port Bits 0->1 16 16 100.00
Port Bits 1->0 16 16 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T19,T7 Yes T1,T2,T3 INPUT
init_trig_i[3:0] Yes Yes T1,T19,T7 Yes T1,T2,T15 INPUT
ping_req_i Yes Yes T4,T131,T259 Yes T4,T131,T259 INPUT
ping_ok_o Yes Yes T131,T259,T74 Yes T131,T259,T74 OUTPUT
integ_fail_o Yes Yes T7,T23,T43 Yes T7,T23,T43 OUTPUT
alert_o Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ack_n Yes Yes T1,T2,T3 Yes T1,T2,T15 OUTPUT
alert_rx_o.ack_p Yes Yes T1,T15,T16 Yes T1,T15,T16 OUTPUT
alert_rx_o.ping_n Yes Yes T4,T259,T74 Yes T259,T78,T260 OUTPUT
alert_rx_o.ping_p Yes Yes T259,T78,T260 Yes T4,T259,T74 OUTPUT
alert_tx_i.alert_n Yes Yes T1,T2,T3 Yes T1,T2,T15 INPUT
alert_tx_i.alert_p Yes Yes T1,T15,T16 Yes T1,T3,T15 INPUT

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