Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T15,T17
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T15,T17

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T15,T17

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T17,T18
1	0	1	Covered	T2,T3,T15
1	1	0	Covered	T1,T18,T19
1	1	1	Covered	T1,T18,T19

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T18,T19
0	1	Covered	T1,T18,T19
1	0	Covered	T7,T20,T21

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T18,T19
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T7,T20,T21

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T19
1	0	Covered	T22
1	1	Covered	T1,T18,T19

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T15,T17
1	Covered	T1,T18,T19

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T15,T17
1	Covered	T1,T15,T6

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T15,T18
1	Covered	T15,T17,T4

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T15,T17
1	Covered	T5,T6,T19

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T4,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T15,T17

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T18,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T15,T4

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T15,T17
Phase1St	198	Covered	T1,T15,T17
Phase2St	215	Covered	T1,T15,T17
Phase3St	233	Covered	T1,T15,T17
TerminalSt	249	Covered	T1,T15,T17
TimeoutSt	159	Covered	T1,T18,T19

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T1,T15,T17
IdleSt->TimeoutSt	159	Covered	T1,T18,T19
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T1,T19,T23
Phase0St->Phase1St	198	Covered	T1,T15,T17
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T24,T25,T26
Phase1St->Phase2St	215	Covered	T1,T15,T17
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T12,T27,T28
Phase2St->Phase3St	233	Covered	T1,T15,T17
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T21,T29,T27
Phase3St->TerminalSt	249	Covered	T1,T15,T17
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T1,T19,T7
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T1,T19,T7
TimeoutSt->Phase0St	172	Covered	T1,T18,T7

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T15,T17
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T18,T19
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T18,T7
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T18,T19
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T7
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T19,T23
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T15,T17
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T15,T17
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T24,T25,T26
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T15,T17
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T15,T17
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T12,T27,T28
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T15,T17
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T15,T17
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T21,T29,T27
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T15,T17
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T15,T17
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T19,T7,T30
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T15,T17
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1065	0	0
CheckAccumTrig0_A	2147483647	2516	0	0
CheckAccumTrig1_A	2147483647	121	0	0
CheckClr_A	2147483647	1162	0	0
CheckEn_A	2147483647	1287497974	0	0
CheckPhase0_A	2147483647	2859	0	0
CheckPhase1_A	2147483647	2806	0	0
CheckPhase2_A	2147483647	2733	0	0
CheckPhase3_A	2147483647	2685	0	0
CheckTimeout0_A	2147483647	6068	0	0
CheckTimeoutSt1_A	2147483647	581009	0	0
CheckTimeoutSt2_A	2147483647	5662	0	0
CheckTimeoutStTrig_A	2147483647	278	0	0
ErrorStAllEscAsserted_A	2147483647	5900	0	0
ErrorStIsTerminal_A	2147483647	4940	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1065	0	0
T8	122204	260	0	0
T9	0	285	0	0
T10	0	150	0	0
T31	0	236	0	0
T32	0	134	0	0
T33	1158988	0	0	0
T34	1582932	0	0	0
T35	418440	0	0	0
T36	179668	0	0	0
T37	1443880	0	0	0
T38	573512	0	0	0
T39	2693896	0	0	0
T40	3338724	0	0	0
T41	1439708	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2516	0	0
T1	177688	2	0	0
T2	690956	0	0	0
T3	1979350	0	0	0
T4	1785736	1	0	0
T5	486216	1	0	0
T6	1898544	3	0	0
T7	431156	5	0	0
T11	237384	2	0	0
T12	357293	4	0	0
T13	0	5	0	0
T14	0	5	0	0
T15	1201356	3	0	0
T16	405582	0	0	0
T17	138117	1	0	0
T18	91652	0	0	0
T19	605808	18	0	0
T23	0	19	0	0
T30	54069	3	0	0
T42	0	1	0	0
T43	0	4	0	0
T44	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	14284	0	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	121	0	0
T7	215578	1	0	0
T11	118692	0	0	0
T12	357293	0	0	0
T13	386904	0	0	0
T14	128978	0	0	0
T20	443010	1	0	0
T21	592077	1	0	0
T25	532626	0	0	0
T27	764538	1	0	0
T30	54069	0	0	0
T47	14284	0	0	0
T48	149995	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	2	0	0
T57	0	2	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	2	0	0
T65	13562	0	0	0
T66	6589	0	0	0
T67	66757	0	0	0
T68	45490	0	0	0
T69	80050	0	0	0
T70	24384	0	0	0
T71	199177	0	0	0
T72	47722	0	0	0
T73	51932	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1162	0	0
T1	88844	2	0	0
T2	345478	0	0	0
T3	989675	0	0	0
T4	446434	0	0	0
T5	121554	0	0	0
T6	474636	0	0	0
T7	215578	1	0	0
T11	118692	0	0	0
T12	357293	1	0	0
T13	386904	0	0	0
T14	257956	2	0	0
T15	400452	0	0	0
T16	135194	0	0	0
T17	46039	0	0	0
T18	22913	0	0	0
T19	302904	4	0	0
T20	0	4	0	0
T21	0	7	0	0
T23	0	5	0	0
T24	0	14	0	0
T25	0	5	0	0
T30	54069	2	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	3	0	0
T47	14284	0	0	0
T48	0	2	0	0
T65	13562	0	0	0
T66	6589	1	0	0
T67	66757	0	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	2	0	0
T77	0	2	0	0
T78	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1287497974	0	0
T1	355376	192727	0	0
T2	1381912	694947	0	0
T3	3958700	2959907	0	0
T4	1785736	1210589	0	0
T5	486216	402942	0	0
T6	1898544	541538	0	0
T15	1601808	414647	0	0
T16	540776	528261	0	0
T17	184156	139890	0	0
T18	91652	69440	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2859	0	0
T1	266532	3	0	0
T2	1036434	0	0	0
T3	2969025	0	0	0
T4	1785736	1	0	0
T5	486216	1	0	0
T6	1898544	3	0	0
T7	215578	9	0	0
T11	118692	2	0	0
T12	357293	4	0	0
T13	0	5	0	0
T14	0	5	0	0
T15	1201356	3	0	0
T16	405582	0	0	0
T17	138117	1	0	0
T18	91652	1	0	0
T19	302904	18	0	0
T23	0	22	0	0
T30	54069	3	0	0
T42	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T47	14284	0	0	0
T67	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2806	0	0
T1	266532	3	0	0
T2	1036434	0	0	0
T3	2969025	0	0	0
T4	1785736	1	0	0
T5	486216	1	0	0
T6	1898544	3	0	0
T7	215578	9	0	0
T11	118692	2	0	0
T12	357293	4	0	0
T13	0	4	0	0
T14	0	5	0	0
T15	1201356	3	0	0
T16	405582	0	0	0
T17	138117	1	0	0
T18	91652	1	0	0
T19	302904	18	0	0
T23	0	21	0	0
T30	54069	3	0	0
T42	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T47	14284	0	0	0
T67	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2733	0	0
T1	266532	3	0	0
T2	1036434	0	0	0
T3	2969025	0	0	0
T4	1785736	1	0	0
T5	486216	1	0	0
T6	1898544	3	0	0
T7	215578	8	0	0
T11	118692	2	0	0
T12	357293	3	0	0
T13	0	4	0	0
T14	0	5	0	0
T15	1201356	3	0	0
T16	405582	0	0	0
T17	138117	1	0	0
T18	91652	1	0	0
T19	302904	18	0	0
T23	0	21	0	0
T30	54069	3	0	0
T42	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T47	14284	0	0	0
T67	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2685	0	0
T1	266532	3	0	0
T2	1036434	0	0	0
T3	2969025	0	0	0
T4	1785736	1	0	0
T5	486216	1	0	0
T6	1898544	3	0	0
T7	215578	8	0	0
T11	118692	2	0	0
T12	357293	3	0	0
T13	0	4	0	0
T14	0	5	0	0
T15	1201356	3	0	0
T16	405582	0	0	0
T17	138117	1	0	0
T18	91652	1	0	0
T19	302904	18	0	0
T23	0	21	0	0
T30	54069	3	0	0
T42	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T47	14284	0	0	0
T67	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	6068	0	0
T1	355376	44	0	0
T2	1381912	0	0	0
T3	3958700	0	0	0
T4	1785736	0	0	0
T5	486216	0	0	0
T6	1898544	0	0	0
T7	0	110	0	0
T15	1601808	0	0	0
T16	540776	0	0	0
T17	184156	0	0	0
T18	91652	1	0	0
T19	0	15	0	0
T20	0	27	0	0
T21	0	2	0	0
T23	0	24	0	0
T24	0	14	0	0
T43	0	1	0	0
T44	0	2	0	0
T47	0	1	0	0
T67	0	19	0	0
T74	0	2	0	0
T76	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	15	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	581009	0	0
T1	355376	3225	0	0
T2	1381912	0	0	0
T3	3958700	0	0	0
T4	1785736	0	0	0
T5	486216	0	0	0
T6	1898544	0	0	0
T7	0	13259	0	0
T15	1601808	0	0	0
T16	540776	0	0	0
T17	184156	0	0	0
T18	91652	141	0	0
T19	0	2064	0	0
T20	0	4868	0	0
T21	0	124	0	0
T23	0	1817	0	0
T24	0	2974	0	0
T43	0	171	0	0
T44	0	85	0	0
T47	0	141	0	0
T67	0	4025	0	0
T74	0	363	0	0
T76	0	94	0	0
T79	0	14	0	0
T80	0	58	0	0
T81	0	59	0	0
T82	0	2450	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5662	0	0
T1	355376	41	0	0
T2	1381912	0	0	0
T3	3958700	0	0	0
T4	1785736	0	0	0
T5	486216	0	0	0
T6	1898544	0	0	0
T7	0	106	0	0
T15	1601808	0	0	0
T16	540776	0	0	0
T17	184156	0	0	0
T18	91652	0	0	0
T19	0	14	0	0
T20	0	45	0	0
T23	0	20	0	0
T24	0	7	0	0
T27	0	355	0	0
T43	0	1	0	0
T44	0	2	0	0
T47	0	1	0	0
T67	0	17	0	0
T74	0	2	0	0
T76	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	14	0	0
T83	0	8	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	278	0	0
T1	88844	3	0	0
T2	345478	0	0	0
T3	989675	0	0	0
T4	446434	0	0	0
T5	243108	0	0	0
T6	949272	0	0	0
T15	400452	0	0	0
T16	135194	0	0	0
T17	46039	0	0	0
T18	45826	1	0	0
T19	302904	1	0	0
T20	443010	10	0	0
T24	610649	5	0	0
T27	0	7	0	0
T39	0	3	0	0
T48	0	2	0	0
T52	0	2	0	0
T53	0	1	0	0
T76	12581	0	0	0
T79	0	1	0	0
T81	69874	0	0	0
T82	76215	0	0	0
T84	0	2	0	0
T85	0	1	0	0
T86	0	1	0	0
T87	0	1	0	0
T88	0	2	0	0
T89	0	3	0	0
T90	0	1	0	0
T91	0	2	0	0
T92	0	2	0	0
T93	0	1	0	0
T94	336328	0	0	0
T95	7850	0	0	0
T96	1705	0	0	0
T97	1233	0	0	0
T98	38325	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5900	0	0
T8	122204	1464	0	0
T9	0	1497	0	0
T10	0	779	0	0
T31	0	1456	0	0
T32	0	704	0	0
T33	1158988	0	0	0
T34	1582932	0	0	0
T35	418440	0	0	0
T36	179668	0	0	0
T37	1443880	0	0	0
T38	573512	0	0	0
T39	2693896	0	0	0
T40	3338724	0	0	0
T41	1439708	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4940	0	0
T8	122204	1224	0	0
T9	0	1257	0	0
T10	0	659	0	0
T31	0	1216	0	0
T32	0	584	0	0
T33	1158988	0	0	0
T34	1582932	0	0	0
T35	418440	0	0	0
T36	179668	0	0	0
T37	1443880	0	0	0
T38	573512	0	0	0
T39	2693896	0	0	0
T40	3338724	0	0	0
T41	1439708	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	355376	354348	0	0
T2	1381912	1381588	0	0
T3	3958700	3958424	0	0
T4	1785736	1785476	0	0
T5	486216	486192	0	0
T6	1898544	1898520	0	0
T15	1601808	1601504	0	0
T16	540776	540496	0	0
T17	184156	183784	0	0
T18	91652	91412	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	355376	354348	0	0
T2	1381912	1381588	0	0
T3	3958700	3958424	0	0
T4	1785736	1785476	0	0
T5	486216	486192	0	0
T6	1898544	1898520	0	0
T15	1601808	1601504	0	0
T16	540776	540496	0	0
T17	184156	183784	0	0
T18	91652	91412	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T15,T17
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T15,T17

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T15,T17

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T17,T19
1	0	1	Covered	T2,T15,T4
1	1	0	Covered	T1,T18,T19
1	1	1	Covered	T1,T19,T7

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T19,T7
0	1	Covered	T1,T79,T24
1	0	Covered	T20,T21,T48

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T19,T7
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T20,T21,T48

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T7
1	0	Not Covered
1	1	Covered	T1,T79,T24

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T15,T17
1	Covered	T19,T30,T12

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T17,T5,T6
1	Covered	T1,T15,T19

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T15,T5
1	Covered	T17,T6,T19

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T15,T17
1	Covered	T5,T19,T66

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T19,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T17,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T6,T19,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T15,T6

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T15,T17
Phase1St	198	Covered	T1,T15,T17
Phase2St	215	Covered	T1,T15,T17
Phase3St	233	Covered	T1,T15,T17
TerminalSt	249	Covered	T1,T15,T17
TimeoutSt	159	Covered	T1,T19,T7

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T1,T15,T17
IdleSt->TimeoutSt	159	Covered	T1,T19,T7
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T1,T19,T23
Phase0St->Phase1St	198	Covered	T1,T15,T17
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T25,T26,T99
Phase1St->Phase2St	215	Covered	T1,T15,T17
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T12,T27,T100
Phase2St->Phase3St	233	Covered	T1,T15,T17
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T29,T27,T52
Phase3St->TerminalSt	249	Covered	T1,T15,T17
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T19,T7
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T19,T7
TimeoutSt->Phase0St	172	Covered	T1,T79,T24

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T15,T17
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T7
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T79,T24
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T7
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T7
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T19,T23
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T15,T17
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T15,T17
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T25,T26,T99
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T15,T17
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T15,T17
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T12,T27,T100
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T15,T17
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T15,T17
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T29,T27,T52
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T15,T17
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T15,T17
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T7,T30,T66
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T15,T17
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	744250956	251	0	0
CheckAccumTrig0_A	744250956	937	0	0
CheckAccumTrig1_A	744250956	55	0	0
CheckClr_A	744250956	465	0	0
CheckEn_A	744089981	237522896	0	0
CheckPhase0_A	744250956	1035	0	0
CheckPhase1_A	744250956	1007	0	0
CheckPhase2_A	744250956	977	0	0
CheckPhase3_A	744250956	953	0	0
CheckTimeout0_A	744250956	1896	0	0
CheckTimeoutSt1_A	744250956	196694	0	0
CheckTimeoutSt2_A	744250956	1766	0	0
CheckTimeoutStTrig_A	744250956	72	0	0
ErrorStAllEscAsserted_A	744250956	1448	0	0
ErrorStIsTerminal_A	744250956	1208	0	0
EscStateOut_A	744088754	744016179	0	0
u_state_regs_A	744250956	744076518	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	251	0	0
T8	30551	62	0	0
T9	0	76	0	0
T10	0	24	0	0
T31	0	61	0	0
T32	0	28	0	0
T33	289747	0	0	0
T34	395733	0	0	0
T35	104610	0	0	0
T36	44917	0	0	0
T37	360970	0	0	0
T38	143378	0	0	0
T39	673474	0	0	0
T40	834681	0	0	0
T41	359927	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	937	0	0
T1	88844	1	0	0
T2	345478	0	0	0
T3	989675	0	0	0
T4	446434	0	0	0
T5	121554	1	0	0
T6	474636	1	0	0
T7	0	3	0	0
T12	0	2	0	0
T13	0	1	0	0
T15	400452	1	0	0
T16	135194	0	0	0
T17	46039	1	0	0
T18	22913	0	0	0
T19	0	6	0	0
T30	0	3	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	55	0	0
T20	443010	1	0	0
T21	592077	1	0	0
T25	532626	0	0	0
T48	149995	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T53	0	1	0	0
T55	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T68	45490	0	0	0
T69	80050	0	0	0
T70	24384	0	0	0
T71	199177	0	0	0
T72	47722	0	0	0
T73	51932	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	465	0	0
T1	88844	2	0	0
T2	345478	0	0	0
T3	989675	0	0	0
T4	446434	0	0	0
T5	121554	0	0	0
T6	474636	0	0	0
T7	0	1	0	0
T12	0	1	0	0
T15	400452	0	0	0
T16	135194	0	0	0
T17	46039	0	0	0
T18	22913	0	0	0
T19	0	1	0	0
T23	0	2	0	0
T24	0	2	0	0
T30	0	2	0	0
T42	0	1	0	0
T66	0	1	0	0
T74	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744089981	237522896	0	0
T1	88844	69408	0	0
T2	345478	310352	0	0
T3	989675	582	0	0
T4	446434	376494	0	0
T5	121554	59767	0	0
T6	474636	27333	0	0
T15	400452	10019	0	0
T16	135194	135123	0	0
T17	46039	2055	0	0
T18	22913	22852	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	1035	0	0
T1	88844	1	0	0
T2	345478	0	0	0
T3	989675	0	0	0
T4	446434	0	0	0
T5	121554	1	0	0
T6	474636	1	0	0
T7	0	3	0	0
T12	0	2	0	0
T13	0	1	0	0
T15	400452	1	0	0
T16	135194	0	0	0
T17	46039	1	0	0
T18	22913	0	0	0
T19	0	5	0	0
T30	0	3	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	1007	0	0
T1	88844	1	0	0
T2	345478	0	0	0
T3	989675	0	0	0
T4	446434	0	0	0
T5	121554	1	0	0
T6	474636	1	0	0
T7	0	3	0	0
T12	0	2	0	0
T13	0	1	0	0
T15	400452	1	0	0
T16	135194	0	0	0
T17	46039	1	0	0
T18	22913	0	0	0
T19	0	5	0	0
T30	0	3	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	977	0	0
T1	88844	1	0	0
T2	345478	0	0	0
T3	989675	0	0	0
T4	446434	0	0	0
T5	121554	1	0	0
T6	474636	1	0	0
T7	0	3	0	0
T12	0	1	0	0
T13	0	1	0	0
T15	400452	1	0	0
T16	135194	0	0	0
T17	46039	1	0	0
T18	22913	0	0	0
T19	0	5	0	0
T30	0	3	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	953	0	0
T1	88844	1	0	0
T2	345478	0	0	0
T3	989675	0	0	0
T4	446434	0	0	0
T5	121554	1	0	0
T6	474636	1	0	0
T7	0	3	0	0
T12	0	1	0	0
T13	0	1	0	0
T15	400452	1	0	0
T16	135194	0	0	0
T17	46039	1	0	0
T18	22913	0	0	0
T19	0	5	0	0
T30	0	3	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	1896	0	0
T1	88844	4	0	0
T2	345478	0	0	0
T3	989675	0	0	0
T4	446434	0	0	0
T5	121554	0	0	0
T6	474636	0	0	0
T7	0	1	0	0
T15	400452	0	0	0
T16	135194	0	0	0
T17	46039	0	0	0
T18	22913	0	0	0
T19	0	1	0	0
T23	0	3	0	0
T24	0	5	0	0
T67	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	3	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	196694	0	0
T1	88844	778	0	0
T2	345478	0	0	0
T3	989675	0	0	0
T4	446434	0	0	0
T5	121554	0	0	0
T6	474636	0	0	0
T7	0	158	0	0
T15	400452	0	0	0
T16	135194	0	0	0
T17	46039	0	0	0
T18	22913	0	0	0
T19	0	467	0	0
T23	0	241	0	0
T24	0	1140	0	0
T67	0	179	0	0
T79	0	14	0	0
T80	0	58	0	0
T81	0	59	0	0
T82	0	521	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	1766	0	0
T1	88844	2	0	0
T2	345478	0	0	0
T3	989675	0	0	0
T4	446434	0	0	0
T5	121554	0	0	0
T6	474636	0	0	0
T7	0	1	0	0
T15	400452	0	0	0
T16	135194	0	0	0
T17	46039	0	0	0
T18	22913	0	0	0
T19	0	1	0	0
T20	0	11	0	0
T23	0	3	0	0
T24	0	3	0	0
T67	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	3	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	72	0	0
T1	88844	2	0	0
T2	345478	0	0	0
T3	989675	0	0	0
T4	446434	0	0	0
T5	121554	0	0	0
T6	474636	0	0	0
T15	400452	0	0	0
T16	135194	0	0	0
T17	46039	0	0	0
T18	22913	0	0	0
T20	0	1	0	0
T24	0	2	0	0
T27	0	3	0	0
T39	0	1	0	0
T48	0	1	0	0
T52	0	1	0	0
T79	0	1	0	0
T88	0	2	0	0
T89	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	1448	0	0
T8	30551	384	0	0
T9	0	377	0	0
T10	0	193	0	0
T31	0	330	0	0
T32	0	164	0	0
T33	289747	0	0	0
T34	395733	0	0	0
T35	104610	0	0	0
T36	44917	0	0	0
T37	360970	0	0	0
T38	143378	0	0	0
T39	673474	0	0	0
T40	834681	0	0	0
T41	359927	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	1208	0	0
T8	30551	324	0	0
T9	0	317	0	0
T10	0	163	0	0
T31	0	270	0	0
T32	0	134	0	0
T33	289747	0	0	0
T34	395733	0	0	0
T35	104610	0	0	0
T36	44917	0	0	0
T37	360970	0	0	0
T38	143378	0	0	0
T39	673474	0	0	0
T40	834681	0	0	0
T41	359927	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744088754	744016179	0	0
T1	88844	88587	0	0
T2	345478	345397	0	0
T3	989675	989606	0	0
T4	446434	446369	0	0
T5	121554	121548	0	0
T6	474636	474630	0	0
T15	400452	400376	0	0
T16	135194	135124	0	0
T17	46039	45946	0	0
T18	22913	22853	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	744076518	0	0
T1	88844	88587	0	0
T2	345478	345397	0	0
T3	989675	989606	0	0
T4	446434	446369	0	0
T5	121554	121548	0	0
T6	474636	474630	0	0
T15	400452	400376	0	0
T16	135194	135124	0	0
T17	46039	45946	0	0
T18	22913	22853	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T4,T6
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T6

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T4,T6,T19

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T19,T7
1	0	1	Covered	T3,T15,T16
1	1	0	Covered	T1,T18,T19
1	1	1	Covered	T1,T19,T7

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T19,T7
0	1	Covered	T24,T20,T27
1	0	Covered	T7,T52,T54

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T19,T7
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T7,T52,T54

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T7
1	0	Not Covered
1	1	Covered	T24,T20,T27

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T6,T19
1	Covered	T19,T11,T12

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T19,T7
1	Covered	T6,T19,T23

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T6,T19,T7
1	Covered	T4,T19,T23

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T6,T19
1	Covered	T7,T14,T23

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T4,T19,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T4,T6,T19

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T19,T11,T23

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T4,T6,T19

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T4,T6,T19
Phase1St	198	Covered	T4,T6,T19
Phase2St	215	Covered	T4,T6,T19
Phase3St	233	Covered	T4,T6,T19
TerminalSt	249	Covered	T4,T6,T19
TimeoutSt	159	Covered	T1,T19,T7

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T4,T6,T19
IdleSt->TimeoutSt	159	Covered	T1,T19,T7
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T23,T33,T101
Phase0St->Phase1St	198	Covered	T4,T6,T19
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T102,T103,T101
Phase1St->Phase2St	215	Covered	T4,T6,T19
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T27,T28,T104
Phase2St->Phase3St	233	Covered	T4,T6,T19
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T33,T101,T105
Phase3St->TerminalSt	249	Covered	T4,T6,T19
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T19,T7,T14
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T19,T7
TimeoutSt->Phase0St	172	Covered	T7,T24,T20

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T19
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T7
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T7,T24,T20
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T7
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T7
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T23,T33,T101
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T4,T6,T19
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T4,T6,T19
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T103,T101,T106
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T4,T6,T19
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T4,T6,T19
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T27,T28,T104
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T4,T6,T19
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T4,T6,T19
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T33,T101,T105
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T4,T6,T19
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T4,T6,T19
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T19,T14,T23
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T4,T6,T19
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	744250956	265	0	0
CheckAccumTrig0_A	744250956	569	0	0
CheckAccumTrig1_A	744250956	19	0	0
CheckClr_A	744250956	265	0	0
CheckEn_A	744089981	358784760	0	0
CheckPhase0_A	744250956	645	0	0
CheckPhase1_A	744250956	638	0	0
CheckPhase2_A	744250956	623	0	0
CheckPhase3_A	744250956	610	0	0
CheckTimeout0_A	744250956	905	0	0
CheckTimeoutSt1_A	744250956	105512	0	0
CheckTimeoutSt2_A	744250956	821	0	0
CheckTimeoutStTrig_A	744250956	63	0	0
ErrorStAllEscAsserted_A	744250956	1438	0	0
ErrorStIsTerminal_A	744250956	1198	0	0
EscStateOut_A	744088754	744016179	0	0
u_state_regs_A	744250956	744076518	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	265	0	0
T8	30551	51	0	0
T9	0	80	0	0
T10	0	45	0	0
T31	0	62	0	0
T32	0	27	0	0
T33	289747	0	0	0
T34	395733	0	0	0
T35	104610	0	0	0
T36	44917	0	0	0
T37	360970	0	0	0
T38	143378	0	0	0
T39	673474	0	0	0
T40	834681	0	0	0
T41	359927	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	569	0	0
T4	446434	1	0	0
T5	121554	0	0	0
T6	474636	1	0	0
T7	215578	0	0	0
T11	118692	1	0	0
T12	357293	1	0	0
T14	0	2	0	0
T18	22913	0	0	0
T19	302904	7	0	0
T23	0	8	0	0
T30	54069	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	14284	0	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	19	0	0
T7	215578	1	0	0
T11	118692	0	0	0
T12	357293	0	0	0
T13	386904	0	0	0
T14	128978	0	0	0
T30	54069	0	0	0
T47	14284	0	0	0
T52	0	1	0	0
T54	0	1	0	0
T56	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	2	0	0
T65	13562	0	0	0
T66	6589	0	0	0
T67	66757	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	265	0	0
T7	215578	0	0	0
T11	118692	0	0	0
T12	357293	0	0	0
T13	386904	0	0	0
T14	128978	1	0	0
T19	302904	3	0	0
T21	0	4	0	0
T23	0	2	0	0
T24	0	2	0	0
T30	54069	0	0	0
T47	14284	0	0	0
T48	0	2	0	0
T65	13562	0	0	0
T66	6589	0	0	0
T75	0	1	0	0
T76	0	2	0	0
T77	0	2	0	0
T78	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744089981	358784760	0	0
T1	88844	29607	0	0
T2	345478	37107	0	0
T3	989675	985257	0	0
T4	446434	11233	0	0
T5	121554	105731	0	0
T6	474636	12242	0	0
T15	400452	370544	0	0
T16	135194	122892	0	0
T17	46039	45945	0	0
T18	22913	22852	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	645	0	0
T4	446434	1	0	0
T5	121554	0	0	0
T6	474636	1	0	0
T7	215578	1	0	0
T11	118692	1	0	0
T12	357293	1	0	0
T14	0	2	0	0
T18	22913	0	0	0
T19	302904	7	0	0
T23	0	7	0	0
T30	54069	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T47	14284	0	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	638	0	0
T4	446434	1	0	0
T5	121554	0	0	0
T6	474636	1	0	0
T7	215578	1	0	0
T11	118692	1	0	0
T12	357293	1	0	0
T14	0	2	0	0
T18	22913	0	0	0
T19	302904	7	0	0
T23	0	7	0	0
T30	54069	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T47	14284	0	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	623	0	0
T4	446434	1	0	0
T5	121554	0	0	0
T6	474636	1	0	0
T7	215578	1	0	0
T11	118692	1	0	0
T12	357293	1	0	0
T14	0	2	0	0
T18	22913	0	0	0
T19	302904	7	0	0
T23	0	7	0	0
T30	54069	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T47	14284	0	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	610	0	0
T4	446434	1	0	0
T5	121554	0	0	0
T6	474636	1	0	0
T7	215578	1	0	0
T11	118692	1	0	0
T12	357293	1	0	0
T14	0	2	0	0
T18	22913	0	0	0
T19	302904	7	0	0
T23	0	7	0	0
T30	54069	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T47	14284	0	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	905	0	0
T1	88844	21	0	0
T2	345478	0	0	0
T3	989675	0	0	0
T4	446434	0	0	0
T5	121554	0	0	0
T6	474636	0	0	0
T7	0	3	0	0
T15	400452	0	0	0
T16	135194	0	0	0
T17	46039	0	0	0
T18	22913	0	0	0
T19	0	9	0	0
T20	0	11	0	0
T23	0	9	0	0
T24	0	4	0	0
T47	0	1	0	0
T67	0	7	0	0
T76	0	1	0	0
T82	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	105512	0	0
T1	88844	1455	0	0
T2	345478	0	0	0
T3	989675	0	0	0
T4	446434	0	0	0
T5	121554	0	0	0
T6	474636	0	0	0
T7	0	406	0	0
T15	400452	0	0	0
T16	135194	0	0	0
T17	46039	0	0	0
T18	22913	0	0	0
T19	0	1018	0	0
T20	0	1866	0	0
T23	0	980	0	0
T24	0	925	0	0
T47	0	141	0	0
T67	0	1614	0	0
T76	0	94	0	0
T82	0	360	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	821	0	0
T1	88844	21	0	0
T2	345478	0	0	0
T3	989675	0	0	0
T4	446434	0	0	0
T5	121554	0	0	0
T6	474636	0	0	0
T7	0	2	0	0
T15	400452	0	0	0
T16	135194	0	0	0
T17	46039	0	0	0
T18	22913	0	0	0
T19	0	9	0	0
T20	0	8	0	0
T23	0	9	0	0
T24	0	2	0	0
T47	0	1	0	0
T67	0	7	0	0
T76	0	1	0	0
T82	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	63	0	0
T20	443010	3	0	0
T24	610649	1	0	0
T27	0	2	0	0
T53	0	1	0	0
T76	12581	0	0	0
T81	69874	0	0	0
T82	76215	0	0	0
T85	0	1	0	0
T87	0	1	0	0
T89	0	2	0	0
T90	0	1	0	0
T92	0	1	0	0
T93	0	1	0	0
T94	336328	0	0	0
T95	7850	0	0	0
T96	1705	0	0	0
T97	1233	0	0	0
T98	38325	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	1438	0	0
T8	30551	344	0	0
T9	0	360	0	0
T10	0	202	0	0
T31	0	363	0	0
T32	0	169	0	0
T33	289747	0	0	0
T34	395733	0	0	0
T35	104610	0	0	0
T36	44917	0	0	0
T37	360970	0	0	0
T38	143378	0	0	0
T39	673474	0	0	0
T40	834681	0	0	0
T41	359927	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	1198	0	0
T8	30551	284	0	0
T9	0	300	0	0
T10	0	172	0	0
T31	0	303	0	0
T32	0	139	0	0
T33	289747	0	0	0
T34	395733	0	0	0
T35	104610	0	0	0
T36	44917	0	0	0
T37	360970	0	0	0
T38	143378	0	0	0
T39	673474	0	0	0
T40	834681	0	0	0
T41	359927	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744088754	744016179	0	0
T1	88844	88587	0	0
T2	345478	345397	0	0
T3	989675	989606	0	0
T4	446434	446369	0	0
T5	121554	121548	0	0
T6	474636	474630	0	0
T15	400452	400376	0	0
T16	135194	135124	0	0
T17	46039	45946	0	0
T18	22913	22853	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	744076518	0	0
T1	88844	88587	0	0
T2	345478	345397	0	0
T3	989675	989606	0	0
T4	446434	446369	0	0
T5	121554	121548	0	0
T6	474636	474630	0	0
T15	400452	400376	0	0
T16	135194	135124	0	0
T17	46039	45946	0	0
T18	22913	22853	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T15,T19
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T15,T19

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T15,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T15,T19,T7

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T19,T7
1	0	1	Covered	T15,T7,T12
1	1	0	Covered	T1,T18,T19
1	1	1	Covered	T1,T19,T7

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T19,T7
0	1	Covered	T1,T19,T7
1	0	Covered	T21,T107,T28

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T19,T7
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T21,T107,T28

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T7
1	0	Not Covered
1	1	Covered	T1,T19,T7

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T15,T19
1	Covered	T19,T7,T13

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T15,T19,T7
1	Covered	T1,T19,T7

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T19,T7
1	Covered	T15,T19,T7

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T15,T19
1	Covered	T23,T42,T74

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T15,T19

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T15,T19,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T15,T19,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T15,T19

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T15,T19
Phase1St	198	Covered	T1,T15,T19
Phase2St	215	Covered	T1,T15,T19
Phase3St	233	Covered	T1,T15,T19
TerminalSt	249	Covered	T1,T15,T19
TimeoutSt	159	Covered	T1,T19,T7

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T15,T19,T7
IdleSt->TimeoutSt	159	Covered	T1,T19,T7
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T21,T27,T52
Phase0St->Phase1St	198	Covered	T1,T15,T19
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T13,T23,T108
Phase1St->Phase2St	215	Covered	T1,T15,T19
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T7,T27,T102
Phase2St->Phase3St	233	Covered	T1,T15,T19
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T104,T59,T101
Phase3St->TerminalSt	249	Covered	T1,T15,T19
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T19,T7
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T19,T7
TimeoutSt->Phase0St	172	Covered	T1,T19,T7

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T15,T19,T7
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T7
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T7
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T7
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T7
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T21,T27,T52
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T15,T19
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T15,T19
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T13,T23,T108
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T15,T19
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T15,T19
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T7,T27,T101
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T15,T19
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T15,T19
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T104,T59,T101
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T15,T19
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T15,T19
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T19,T13,T67
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T15,T19
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	744250956	278	0	0
CheckAccumTrig0_A	744250956	509	0	0
CheckAccumTrig1_A	744250956	21	0	0
CheckClr_A	744250956	205	0	0
CheckEn_A	744089981	326716697	0	0
CheckPhase0_A	744250956	587	0	0
CheckPhase1_A	744250956	580	0	0
CheckPhase2_A	744250956	565	0	0
CheckPhase3_A	744250956	560	0	0
CheckTimeout0_A	744250956	1384	0	0
CheckTimeoutSt1_A	744250956	119494	0	0
CheckTimeoutSt2_A	744250956	1294	0	0
CheckTimeoutStTrig_A	744250956	68	0	0
ErrorStAllEscAsserted_A	744250956	1518	0	0
ErrorStIsTerminal_A	744250956	1278	0	0
EscStateOut_A	744088754	744016179	0	0
u_state_regs_A	744250956	744076518	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	278	0	0
T8	30551	87	0	0
T9	0	64	0	0
T10	0	39	0	0
T31	0	55	0	0
T32	0	33	0	0
T33	289747	0	0	0
T34	395733	0	0	0
T35	104610	0	0	0
T36	44917	0	0	0
T37	360970	0	0	0
T38	143378	0	0	0
T39	673474	0	0	0
T40	834681	0	0	0
T41	359927	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	509	0	0
T4	446434	0	0	0
T5	121554	0	0	0
T6	474636	0	0	0
T7	215578	1	0	0
T11	118692	1	0	0
T13	0	3	0	0
T14	0	1	0	0
T15	400452	1	0	0
T16	135194	0	0	0
T17	46039	0	0	0
T18	22913	0	0	0
T19	302904	3	0	0
T23	0	7	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	21	0	0
T21	592077	1	0	0
T25	532626	0	0	0
T28	0	1	0	0
T48	149995	0	0	0
T71	199177	0	0	0
T72	47722	0	0	0
T73	51932	0	0	0
T77	234843	0	0	0
T78	554240	0	0	0
T107	0	1	0	0
T109	0	1	0	0
T110	0	1	0	0
T111	0	1	0	0
T112	0	1	0	0
T113	0	1	0	0
T114	0	1	0	0
T115	0	1	0	0
T116	187178	0	0	0
T117	128073	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	205	0	0
T7	215578	1	0	0
T11	118692	0	0	0
T12	357293	0	0	0
T13	386904	2	0	0
T14	128978	0	0	0
T19	302904	1	0	0
T21	0	3	0	0
T23	0	6	0	0
T24	0	1	0	0
T25	0	1	0	0
T30	54069	0	0	0
T47	14284	0	0	0
T65	13562	0	0	0
T66	6589	0	0	0
T67	0	1	0	0
T71	0	1	0	0
T118	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744089981	326716697	0	0
T1	88844	55240	0	0
T2	345478	345396	0	0
T3	989675	989605	0	0
T4	446434	390737	0	0
T5	121554	115896	0	0
T6	474636	474144	0	0
T15	400452	9887	0	0
T16	135194	135123	0	0
T17	46039	45945	0	0
T18	22913	22852	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	587	0	0
T1	88844	1	0	0
T2	345478	0	0	0
T3	989675	0	0	0
T4	446434	0	0	0
T5	121554	0	0	0
T6	474636	0	0	0
T7	0	4	0	0
T11	0	1	0	0
T13	0	3	0	0
T14	0	1	0	0
T15	400452	1	0	0
T16	135194	0	0	0
T17	46039	0	0	0
T18	22913	0	0	0
T19	0	4	0	0
T23	0	11	0	0
T42	0	1	0	0
T67	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	580	0	0
T1	88844	1	0	0
T2	345478	0	0	0
T3	989675	0	0	0
T4	446434	0	0	0
T5	121554	0	0	0
T6	474636	0	0	0
T7	0	4	0	0
T11	0	1	0	0
T13	0	2	0	0
T14	0	1	0	0
T15	400452	1	0	0
T16	135194	0	0	0
T17	46039	0	0	0
T18	22913	0	0	0
T19	0	4	0	0
T23	0	10	0	0
T42	0	1	0	0
T67	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	565	0	0
T1	88844	1	0	0
T2	345478	0	0	0
T3	989675	0	0	0
T4	446434	0	0	0
T5	121554	0	0	0
T6	474636	0	0	0
T7	0	3	0	0
T11	0	1	0	0
T13	0	2	0	0
T14	0	1	0	0
T15	400452	1	0	0
T16	135194	0	0	0
T17	46039	0	0	0
T18	22913	0	0	0
T19	0	4	0	0
T23	0	10	0	0
T42	0	1	0	0
T67	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	560	0	0
T1	88844	1	0	0
T2	345478	0	0	0
T3	989675	0	0	0
T4	446434	0	0	0
T5	121554	0	0	0
T6	474636	0	0	0
T7	0	3	0	0
T11	0	1	0	0
T13	0	2	0	0
T14	0	1	0	0
T15	400452	1	0	0
T16	135194	0	0	0
T17	46039	0	0	0
T18	22913	0	0	0
T19	0	4	0	0
T23	0	10	0	0
T42	0	1	0	0
T67	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	1384	0	0
T1	88844	9	0	0
T2	345478	0	0	0
T3	989675	0	0	0
T4	446434	0	0	0
T5	121554	0	0	0
T6	474636	0	0	0
T7	0	10	0	0
T15	400452	0	0	0
T16	135194	0	0	0
T17	46039	0	0	0
T18	22913	0	0	0
T19	0	4	0	0
T20	0	16	0	0
T21	0	2	0	0
T23	0	7	0	0
T24	0	2	0	0
T67	0	6	0	0
T74	0	2	0	0
T82	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	119494	0	0
T1	88844	563	0	0
T2	345478	0	0	0
T3	989675	0	0	0
T4	446434	0	0	0
T5	121554	0	0	0
T6	474636	0	0	0
T7	0	1893	0	0
T15	400452	0	0	0
T16	135194	0	0	0
T17	46039	0	0	0
T18	22913	0	0	0
T19	0	501	0	0
T20	0	3002	0	0
T21	0	124	0	0
T23	0	392	0	0
T24	0	253	0	0
T67	0	1155	0	0
T74	0	363	0	0
T82	0	133	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	1294	0	0
T1	88844	8	0	0
T2	345478	0	0	0
T3	989675	0	0	0
T4	446434	0	0	0
T5	121554	0	0	0
T6	474636	0	0	0
T7	0	7	0	0
T15	400452	0	0	0
T16	135194	0	0	0
T17	46039	0	0	0
T18	22913	0	0	0
T19	0	3	0	0
T20	0	16	0	0
T23	0	3	0	0
T24	0	1	0	0
T27	0	355	0	0
T67	0	4	0	0
T74	0	2	0	0
T83	0	8	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	68	0	0
T1	88844	1	0	0
T2	345478	0	0	0
T3	989675	0	0	0
T4	446434	0	0	0
T5	121554	0	0	0
T6	474636	0	0	0
T7	0	3	0	0
T15	400452	0	0	0
T16	135194	0	0	0
T17	46039	0	0	0
T18	22913	0	0	0
T19	0	1	0	0
T21	0	1	0	0
T23	0	4	0	0
T27	0	1	0	0
T52	0	1	0	0
T67	0	2	0	0
T82	0	1	0	0
T84	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	1518	0	0
T8	30551	376	0	0
T9	0	384	0	0
T10	0	183	0	0
T31	0	382	0	0
T32	0	193	0	0
T33	289747	0	0	0
T34	395733	0	0	0
T35	104610	0	0	0
T36	44917	0	0	0
T37	360970	0	0	0
T38	143378	0	0	0
T39	673474	0	0	0
T40	834681	0	0	0
T41	359927	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	1278	0	0
T8	30551	316	0	0
T9	0	324	0	0
T10	0	153	0	0
T31	0	322	0	0
T32	0	163	0	0
T33	289747	0	0	0
T34	395733	0	0	0
T35	104610	0	0	0
T36	44917	0	0	0
T37	360970	0	0	0
T38	143378	0	0	0
T39	673474	0	0	0
T40	834681	0	0	0
T41	359927	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744088754	744016179	0	0
T1	88844	88587	0	0
T2	345478	345397	0	0
T3	989675	989606	0	0
T4	446434	446369	0	0
T5	121554	121548	0	0
T6	474636	474630	0	0
T15	400452	400376	0	0
T16	135194	135124	0	0
T17	46039	45946	0	0
T18	22913	22853	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	744076518	0	0
T1	88844	88587	0	0
T2	345478	345397	0	0
T3	989675	989606	0	0
T4	446434	446369	0	0
T5	121554	121548	0	0
T6	474636	474630	0	0
T15	400452	400376	0	0
T16	135194	135124	0	0
T17	46039	45946	0	0
T18	22913	22853	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T15,T18
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T15,T18

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T15,T6

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T18,T19
1	0	1	Covered	T15,T11,T23
1	1	0	Covered	T1,T19,T7
1	1	1	Covered	T1,T18,T19

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T18,T19
0	1	Covered	T18,T24,T20
1	0	Covered	T27,T28,T102

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T18,T19
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T27,T28,T102

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T19
1	0	Covered	T22
1	1	Covered	T18,T24,T20

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T15,T6,T19
1	Covered	T1,T18,T19

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T15,T18
1	Covered	T14,T43,T44

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T18,T6
1	Covered	T15,T7,T13

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T15,T18
1	Covered	T6,T19,T23

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T18,T19,T23

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T15,T6,T19

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T18,T19

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T18,T6,T7

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T15,T18
Phase1St	198	Covered	T1,T15,T18
Phase2St	215	Covered	T1,T15,T18
Phase3St	233	Covered	T1,T15,T18
TerminalSt	249	Covered	T1,T15,T18
TimeoutSt	159	Covered	T1,T18,T19

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T1,T15,T6
IdleSt->TimeoutSt	159	Covered	T1,T18,T19
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T27,T119,T106
Phase0St->Phase1St	198	Covered	T1,T15,T18
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T24,T120,T106
Phase1St->Phase2St	215	Covered	T1,T15,T18
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T121,T93,T56
Phase2St->Phase3St	233	Covered	T1,T15,T18
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T21,T57,T122
Phase3St->TerminalSt	249	Covered	T1,T15,T18
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T19,T7
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T19,T7
TimeoutSt->Phase0St	172	Covered	T18,T24,T20

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T15,T6
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T18,T19
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T18,T24,T20
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T18,T19
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T19,T7
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T27,T119,T106
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T15,T18
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T15,T18
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T24,T120,T106
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T15,T18
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T15,T18
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T121,T93,T56
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T15,T18
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T15,T18
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T21,T57,T122
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T15,T18
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T15,T18
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T14,T23,T43
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T15,T18
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	744250956	271	0	0
CheckAccumTrig0_A	744250956	501	0	0
CheckAccumTrig1_A	744250956	26	0	0
CheckClr_A	744250956	227	0	0
CheckEn_A	744089981	364473621	0	0
CheckPhase0_A	744250956	592	0	0
CheckPhase1_A	744250956	581	0	0
CheckPhase2_A	744250956	568	0	0
CheckPhase3_A	744250956	562	0	0
CheckTimeout0_A	744250956	1883	0	0
CheckTimeoutSt1_A	744250956	159309	0	0
CheckTimeoutSt2_A	744250956	1781	0	0
CheckTimeoutStTrig_A	744250956	75	0	0
ErrorStAllEscAsserted_A	744250956	1496	0	0
ErrorStIsTerminal_A	744250956	1256	0	0
EscStateOut_A	744088754	744016179	0	0
u_state_regs_A	744250956	744076518	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	271	0	0
T8	30551	60	0	0
T9	0	65	0	0
T10	0	42	0	0
T31	0	58	0	0
T32	0	46	0	0
T33	289747	0	0	0
T34	395733	0	0	0
T35	104610	0	0	0
T36	44917	0	0	0
T37	360970	0	0	0
T38	143378	0	0	0
T39	673474	0	0	0
T40	834681	0	0	0
T41	359927	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	501	0	0
T1	88844	1	0	0
T2	345478	0	0	0
T3	989675	0	0	0
T4	446434	0	0	0
T5	121554	0	0	0
T6	474636	1	0	0
T7	0	1	0	0
T12	0	1	0	0
T13	0	1	0	0
T14	0	2	0	0
T15	400452	1	0	0
T16	135194	0	0	0
T17	46039	0	0	0
T18	22913	0	0	0
T19	0	2	0	0
T23	0	4	0	0
T43	0	3	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	26	0	0
T27	764538	1	0	0
T28	476198	1	0	0
T50	86513	0	0	0
T56	0	1	0	0
T57	0	1	0	0
T84	25008	0	0	0
T102	0	1	0	0
T107	25287	0	0	0
T108	0	1	0	0
T121	0	3	0	0
T123	0	1	0	0
T124	0	1	0	0
T125	0	1	0	0
T126	541431	0	0	0
T127	22703	0	0	0
T128	64764	0	0	0
T129	740952	0	0	0
T130	553249	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	227	0	0
T14	128978	1	0	0
T20	0	4	0	0
T21	0	3	0	0
T23	156180	1	0	0
T24	0	10	0	0
T25	0	5	0	0
T27	0	2	0	0
T42	509053	0	0	0
T43	106834	2	0	0
T44	49347	3	0	0
T67	66757	0	0	0
T79	91253	0	0	0
T84	0	1	0	0
T118	466793	0	0	0
T131	171104	0	0	0
T132	31338	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744089981	364473621	0	0
T1	88844	38472	0	0
T2	345478	2092	0	0
T3	989675	984463	0	0
T4	446434	432125	0	0
T5	121554	121548	0	0
T6	474636	27819	0	0
T15	400452	24197	0	0
T16	135194	135123	0	0
T17	46039	45945	0	0
T18	22913	884	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	592	0	0
T1	88844	1	0	0
T2	345478	0	0	0
T3	989675	0	0	0
T4	446434	0	0	0
T5	121554	0	0	0
T6	474636	1	0	0
T7	0	1	0	0
T12	0	1	0	0
T13	0	1	0	0
T14	0	2	0	0
T15	400452	1	0	0
T16	135194	0	0	0
T17	46039	0	0	0
T18	22913	1	0	0
T19	0	2	0	0
T23	0	4	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	581	0	0
T1	88844	1	0	0
T2	345478	0	0	0
T3	989675	0	0	0
T4	446434	0	0	0
T5	121554	0	0	0
T6	474636	1	0	0
T7	0	1	0	0
T12	0	1	0	0
T13	0	1	0	0
T14	0	2	0	0
T15	400452	1	0	0
T16	135194	0	0	0
T17	46039	0	0	0
T18	22913	1	0	0
T19	0	2	0	0
T23	0	4	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	568	0	0
T1	88844	1	0	0
T2	345478	0	0	0
T3	989675	0	0	0
T4	446434	0	0	0
T5	121554	0	0	0
T6	474636	1	0	0
T7	0	1	0	0
T12	0	1	0	0
T13	0	1	0	0
T14	0	2	0	0
T15	400452	1	0	0
T16	135194	0	0	0
T17	46039	0	0	0
T18	22913	1	0	0
T19	0	2	0	0
T23	0	4	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	562	0	0
T1	88844	1	0	0
T2	345478	0	0	0
T3	989675	0	0	0
T4	446434	0	0	0
T5	121554	0	0	0
T6	474636	1	0	0
T7	0	1	0	0
T12	0	1	0	0
T13	0	1	0	0
T14	0	2	0	0
T15	400452	1	0	0
T16	135194	0	0	0
T17	46039	0	0	0
T18	22913	1	0	0
T19	0	2	0	0
T23	0	4	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	1883	0	0
T1	88844	10	0	0
T2	345478	0	0	0
T3	989675	0	0	0
T4	446434	0	0	0
T5	121554	0	0	0
T6	474636	0	0	0
T7	0	96	0	0
T15	400452	0	0	0
T16	135194	0	0	0
T17	46039	0	0	0
T18	22913	1	0	0
T19	0	1	0	0
T23	0	5	0	0
T24	0	3	0	0
T43	0	1	0	0
T44	0	2	0	0
T67	0	5	0	0
T82	0	9	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	159309	0	0
T1	88844	429	0	0
T2	345478	0	0	0
T3	989675	0	0	0
T4	446434	0	0	0
T5	121554	0	0	0
T6	474636	0	0	0
T7	0	10802	0	0
T15	400452	0	0	0
T16	135194	0	0	0
T17	46039	0	0	0
T18	22913	141	0	0
T19	0	78	0	0
T23	0	204	0	0
T24	0	656	0	0
T43	0	171	0	0
T44	0	85	0	0
T67	0	1077	0	0
T82	0	1436	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	1781	0	0
T1	88844	10	0	0
T2	345478	0	0	0
T3	989675	0	0	0
T4	446434	0	0	0
T5	121554	0	0	0
T6	474636	0	0	0
T7	0	96	0	0
T15	400452	0	0	0
T16	135194	0	0	0
T17	46039	0	0	0
T18	22913	0	0	0
T19	0	1	0	0
T20	0	10	0	0
T23	0	5	0	0
T24	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T67	0	5	0	0
T82	0	9	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	75	0	0
T5	121554	0	0	0
T6	474636	0	0	0
T7	215578	0	0	0
T11	118692	0	0	0
T12	357293	0	0	0
T13	386904	0	0	0
T18	22913	1	0	0
T19	302904	0	0	0
T20	0	6	0	0
T24	0	2	0	0
T27	0	1	0	0
T30	54069	0	0	0
T39	0	2	0	0
T47	14284	0	0	0
T48	0	1	0	0
T84	0	1	0	0
T86	0	1	0	0
T91	0	2	0	0
T92	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	1496	0	0
T8	30551	360	0	0
T9	0	376	0	0
T10	0	201	0	0
T31	0	381	0	0
T32	0	178	0	0
T33	289747	0	0	0
T34	395733	0	0	0
T35	104610	0	0	0
T36	44917	0	0	0
T37	360970	0	0	0
T38	143378	0	0	0
T39	673474	0	0	0
T40	834681	0	0	0
T41	359927	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	1256	0	0
T8	30551	300	0	0
T9	0	316	0	0
T10	0	171	0	0
T31	0	321	0	0
T32	0	148	0	0
T33	289747	0	0	0
T34	395733	0	0	0
T35	104610	0	0	0
T36	44917	0	0	0
T37	360970	0	0	0
T38	143378	0	0	0
T39	673474	0	0	0
T40	834681	0	0	0
T41	359927	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744088754	744016179	0	0
T1	88844	88587	0	0
T2	345478	345397	0	0
T3	989675	989606	0	0
T4	446434	446369	0	0
T5	121554	121548	0	0
T6	474636	474630	0	0
T15	400452	400376	0	0
T16	135194	135124	0	0
T17	46039	45946	0	0
T18	22913	22853	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	744250956	744076518	0	0
T1	88844	88587	0	0
T2	345478	345397	0	0
T3	989675	989606	0	0
T4	446434	446369	0	0
T5	121554	121548	0	0
T6	474636	474630	0	0
T15	400452	400376	0	0
T16	135194	135124	0	0
T17	46039	45946	0	0
T18	22913	22853	0	0