Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	66363784	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

32246159

1

T1

125423

T2

115342

T3

63490

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	14655815	1			T1	47296		T2	46306		T3	24830
values[0x0]	40814647	1			T1	133782		T2	158602		T3	88460
values[0x1]	43139481	1			T1	169127		T2	158826		T3	88400

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	56543895	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

42066048

1

T1

174528

T2

145817

T3

80739

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	319348	1			T1	679		T2	1374		T15	15
valid_sources[0x01]	325918	1			T1	6422		T2	1366		T15	22
valid_sources[0x02]	322733	1			T1	545		T2	1374		T15	13
valid_sources[0x03]	325884	1			T1	1642		T2	1321		T15	16
valid_sources[0x04]	329784	1			T1	1705		T2	1345		T15	25
valid_sources[0x05]	320654	1			T1	372		T2	1415		T15	29
valid_sources[0x06]	322635	1			T1	513		T2	1402		T15	20
valid_sources[0x07]	319727	1			T1	498		T2	1378		T15	11
valid_sources[0x08]	316073	1			T1	526		T2	1425		T15	14
valid_sources[0x09]	313857	1			T1	480		T2	1344		T15	18
valid_sources[0x0a]	324433	1			T1	292		T2	1480		T15	26
valid_sources[0x0b]	314345	1			T1	577		T2	1421		T15	21
valid_sources[0x0c]	313678	1			T1	741		T2	1398		T15	17
valid_sources[0x0d]	328526	1			T1	594		T2	1347		T15	14
valid_sources[0x0e]	317144	1			T1	531		T2	1357		T15	20
valid_sources[0x0f]	331190	1			T1	3353		T2	1403		T15	24
valid_sources[0x10]	327991	1			T1	3403		T2	1386		T15	20
valid_sources[0x11]	327258	1			T1	698		T2	1372		T15	21
valid_sources[0x12]	325534	1			T1	590		T2	1378		T15	19
valid_sources[0x13]	336934	1			T1	1404		T2	1544		T15	22
valid_sources[0x14]	328746	1			T1	494		T2	1416		T15	17
valid_sources[0x15]	331731	1			T1	3238		T2	1393		T15	19
valid_sources[0x16]	784650	1			T1	524		T2	1404		T15	13
valid_sources[0x17]	321592	1			T1	548		T2	1387		T15	22
valid_sources[0x18]	325818	1			T1	2249		T2	1462		T15	16
valid_sources[0x19]	332360	1			T1	653		T2	1433		T15	20
valid_sources[0x1a]	316626	1			T1	659		T2	1343		T15	22
valid_sources[0x1b]	314079	1			T1	351		T2	1416		T15	18
valid_sources[0x1c]	535857	1			T1	1167		T2	1434		T15	16
valid_sources[0x1d]	309918	1			T1	411		T2	1452		T15	21
valid_sources[0x1e]	336143	1			T1	730		T2	1435		T15	21
valid_sources[0x1f]	325330	1			T1	3440		T2	1463		T15	13
valid_sources[0x20]	331476	1			T1	6268		T2	1433		T15	16
valid_sources[0x21]	316635	1			T1	2746		T2	1401		T15	14
valid_sources[0x22]	337496	1			T1	603		T2	1470		T15	25
valid_sources[0x23]	322606	1			T1	677		T2	1397		T15	28
valid_sources[0x24]	315406	1			T1	703		T2	1447		T15	25
valid_sources[0x25]	332731	1			T1	2110		T2	1410		T15	30
valid_sources[0x26]	325504	1			T1	1150		T2	1417		T15	22
valid_sources[0x27]	324003	1			T1	404		T2	1416		T15	27
valid_sources[0x28]	325010	1			T1	1498		T2	1512		T15	23
valid_sources[0x29]	318283	1			T1	493		T2	1413		T15	21
valid_sources[0x2a]	320026	1			T1	493		T2	1439		T15	20
valid_sources[0x2b]	320718	1			T1	718		T2	1431		T15	15
valid_sources[0x2c]	721947	1			T1	558		T2	1393		T15	21
valid_sources[0x2d]	326870	1			T1	689		T2	1484		T15	22
valid_sources[0x2e]	324981	1			T1	536		T2	1376		T15	18
valid_sources[0x2f]	363954	1			T1	481		T2	1350		T15	17
valid_sources[0x30]	540706	1			T1	2784		T2	1440		T15	18
valid_sources[0x31]	315295	1			T1	939		T2	1383		T15	16
valid_sources[0x32]	342091	1			T1	537		T2	1346		T15	22
valid_sources[0x33]	329624	1			T1	3592		T2	1418		T15	24
valid_sources[0x34]	332022	1			T1	5866		T2	1468		T15	12
valid_sources[0x35]	349822	1			T1	284		T2	1435		T15	23
valid_sources[0x36]	326226	1			T1	445		T2	1398		T15	17
valid_sources[0x37]	687143	1			T1	646		T2	1514		T15	19
valid_sources[0x38]	317732	1			T1	436		T2	1367		T15	17
valid_sources[0x39]	323422	1			T1	2626		T2	1419		T15	19
valid_sources[0x3a]	909169	1			T1	1122		T2	1404		T15	10
valid_sources[0x3b]	707157	1			T1	2675		T2	1462		T15	17
valid_sources[0x3c]	320569	1			T1	407		T2	1435		T15	19
valid_sources[0x3d]	334650	1			T1	400		T2	1383		T15	26
valid_sources[0x3e]	323566	1			T1	722		T2	1413		T15	18
valid_sources[0x3f]	327199	1			T1	585		T2	1427		T15	22
valid_sources[0x40]	321734	1			T1	680		T2	1438		T15	18
valid_sources[0x41]	341006	1			T1	513		T2	1395		T15	23
valid_sources[0x42]	938193	1			T1	1162		T2	1398		T15	11
valid_sources[0x43]	573864	1			T1	2271		T2	1394		T15	13
valid_sources[0x44]	959714	1			T1	5577		T2	1432		T15	13
valid_sources[0x45]	319401	1			T1	3826		T2	1361		T15	17
valid_sources[0x46]	328727	1			T1	817		T2	1424		T15	20
valid_sources[0x47]	334028	1			T1	3665		T2	1431		T15	25
valid_sources[0x48]	318002	1			T1	1801		T2	1423		T15	20
valid_sources[0x49]	326378	1			T1	1095		T2	1475		T15	21
valid_sources[0x4a]	336686	1			T1	3982		T2	1436		T15	20
valid_sources[0x4b]	316389	1			T1	536		T2	1394		T15	21
valid_sources[0x4c]	323910	1			T1	756		T2	1440		T15	19
valid_sources[0x4d]	333316	1			T1	3154		T2	1361		T15	21
valid_sources[0x4e]	316742	1			T1	538		T2	1466		T15	24
valid_sources[0x4f]	644196	1			T1	387		T2	1455		T15	19
valid_sources[0x50]	319727	1			T1	386		T2	1412		T15	14
valid_sources[0x51]	322186	1			T1	2817		T2	1344		T15	18
valid_sources[0x52]	609582	1			T1	2970		T2	1427		T15	16
valid_sources[0x53]	653954	1			T1	687		T2	1354		T15	20
valid_sources[0x54]	357227	1			T1	996		T2	1344		T15	25
valid_sources[0x55]	330829	1			T1	5132		T2	1445		T15	17
valid_sources[0x56]	588174	1			T1	909		T2	1440		T15	24
valid_sources[0x57]	521936	1			T1	412		T2	1415		T15	19
valid_sources[0x58]	317583	1			T1	602		T2	1462		T15	22
valid_sources[0x59]	320452	1			T1	898		T2	1444		T15	20
valid_sources[0x5a]	314794	1			T1	904		T2	1427		T15	25
valid_sources[0x5b]	336420	1			T1	584		T2	1497		T15	15
valid_sources[0x5c]	319921	1			T1	578		T2	1424		T15	12
valid_sources[0x5d]	528150	1			T1	570		T2	1436		T3	201690
valid_sources[0x5e]	335120	1			T1	2965		T2	1398		T15	18
valid_sources[0x5f]	315781	1			T1	489		T2	1374		T15	20
valid_sources[0x60]	336010	1			T1	4613		T2	1427		T15	20
valid_sources[0x61]	763334	1			T1	4172		T2	1438		T15	22
valid_sources[0x62]	316389	1			T1	650		T2	1369		T15	15
valid_sources[0x63]	325924	1			T1	460		T2	1376		T15	21
valid_sources[0x64]	652694	1			T1	734		T2	1460		T15	21
valid_sources[0x65]	315728	1			T1	390		T2	1422		T15	14
valid_sources[0x66]	328229	1			T1	3072		T2	1440		T15	15
valid_sources[0x67]	328215	1			T1	3585		T2	1489		T15	16
valid_sources[0x68]	325148	1			T1	635		T2	1461		T15	18
valid_sources[0x69]	326093	1			T1	468		T2	1425		T15	19
valid_sources[0x6a]	313562	1			T1	668		T2	1404		T15	9
valid_sources[0x6b]	595243	1			T1	839		T2	1435		T15	16
valid_sources[0x6c]	737192	1			T1	3680		T2	1441		T15	20
valid_sources[0x6d]	327686	1			T1	3776		T2	1478		T15	12
valid_sources[0x6e]	786294	1			T1	2775		T2	1379		T15	19
valid_sources[0x6f]	324882	1			T1	649		T2	1456		T15	15
valid_sources[0x70]	318254	1			T1	368		T2	1490		T15	17
valid_sources[0x71]	330824	1			T1	534		T2	1406		T15	22
valid_sources[0x72]	314171	1			T1	732		T2	1425		T15	29
valid_sources[0x73]	324031	1			T1	1977		T2	1427		T15	13
valid_sources[0x74]	322152	1			T1	2870		T2	1486		T15	20
valid_sources[0x75]	334237	1			T1	3777		T2	1436		T15	18
valid_sources[0x76]	337297	1			T1	736		T2	1446		T15	16
valid_sources[0x77]	511659	1			T1	585		T2	1396		T15	14
valid_sources[0x78]	326001	1			T1	647		T2	1490		T15	17
valid_sources[0x79]	328722	1			T1	383		T2	1323		T15	19
valid_sources[0x7a]	324654	1			T1	514		T2	1465		T15	14
valid_sources[0x7b]	701070	1			T1	2535		T2	1397		T15	30
valid_sources[0x7c]	662145	1			T1	2914		T2	1489		T15	31
valid_sources[0x7d]	331624	1			T1	992		T2	1355		T15	19
valid_sources[0x7e]	331910	1			T1	1915		T2	1466		T15	24
valid_sources[0x7f]	323597	1			T1	474		T2	1384		T15	27
valid_sources[0x80]	341784	1			T1	644		T2	1506		T15	26

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7352015

1

T1

27947

T2

23130

T3

12301

values[0x0]

all_enables

biggest_size

15687873

1

T1

58333

T2

59015

T3

32764

values[0x1]

all_enables

biggest_size

9206271

1

T1

39143

T2

33197

T3

18425